From acc276a612d4ea4babf47f8719225eb4a5833036 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 31 Aug 2012 09:54:31 +0930 Subject: ADC documentation added In adc.h additional defines needed to assist documentation - lines 172-191 added, and 384,436-451 are duplicates of earlier defines to complete parameter sets (compiler has no trouble with these). Minor doc corrections to other files. No code changes (apart from additional defines). --- include/libopencm3/stm32/f1/adc.h | 226 +++++++++++++++++++++++++++++++++++--- 1 file changed, 209 insertions(+), 17 deletions(-) (limited to 'include/libopencm3/stm32/f1/adc.h') diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 563e75d..64865f4 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -1,3 +1,17 @@ +/** @defgroup STM32F1xx_adc_defines ADC Defines + +@brief Defined Constants and Types for the STM32F1xx Analog to Digital Converters + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Edward Cheeseman + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,6 +31,8 @@ * along with this library. If not, see . */ +/**@{*/ + #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H @@ -26,9 +42,15 @@ /* --- Convenience macros -------------------------------------------------- */ /* ADC port base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup adc_reg_base ADC register base addresses +@ingroup STM32F1xx_adc_defines + +@{*/ #define ADC1 ADC1_BASE #define ADC2 ADC2_BASE #define ADC3 ADC3_BASE +/**@}*/ /* --- ADC registers ------------------------------------------------------- */ @@ -140,6 +162,35 @@ #define ADC2_DR ADC_DR(ADC2) #define ADC3_DR ADC_DR(ADC3) +/* --- ADC Channels ------------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup adc_channel ADC Channel Numbers +@ingroup STM32F1xx_adc_defines + +@{*/ +#define ADC_CHANNEL0 0x00 +#define ADC_CHANNEL1 0x01 +#define ADC_CHANNEL2 0x02 +#define ADC_CHANNEL3 0x03 +#define ADC_CHANNEL4 0x04 +#define ADC_CHANNEL5 0x05 +#define ADC_CHANNEL6 0x06 +#define ADC_CHANNEL7 0x07 +#define ADC_CHANNEL8 0x08 +#define ADC_CHANNEL9 0x09 +#define ADC_CHANNEL10 0x0A +#define ADC_CHANNEL11 0x0B +#define ADC_CHANNEL12 0x0C +#define ADC_CHANNEL13 0x0D +#define ADC_CHANNEL14 0x0E +#define ADC_CHANNEL15 0x0F +#define ADC_CHANNEL16 0x10 +#define ADC_CHANNEL17 0x11 +#define ADC_MASK 0x1F +#define ADC_SHIFT 0 +/**@}*/ + /* --- ADC_SR values ------------------------------------------------------- */ #define ADC_SR_STRT (1 << 4) @@ -171,20 +222,42 @@ * SIM: Slow interleaved mode only. * ATM: Alternate trigger mode only. */ +/****************************************************************************/ +/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */ +/** @defgroup adc_cr1_dualmod ADC Mode Selection +@ingroup STM32F1xx_adc_defines + +@{*/ +/** Independent (non-dual) mode */ #define ADC_CR1_DUALMOD_IND (0x0 << 16) +/** Combined regular simultaneous + injected simultaneous mode. */ #define ADC_CR1_DUALMOD_CRSISM (0x1 << 16) +/** Combined regular simultaneous + alternate trigger mode. */ #define ADC_CR1_DUALMOD_CRSATM (0x2 << 16) +/** Combined injected simultaneous + fast interleaved mode. */ #define ADC_CR1_DUALMOD_CISFIM (0x3 << 16) +/** Combined injected simultaneous + slow interleaved mode. */ #define ADC_CR1_DUALMOD_CISSIM (0x4 << 16) +/** Injected simultaneous mode only. */ #define ADC_CR1_DUALMOD_ISM (0x5 << 16) +/** Regular simultaneous mode only. */ #define ADC_CR1_DUALMOD_RSM (0x6 << 16) +/** Fast interleaved mode only. */ #define ADC_CR1_DUALMOD_FIM (0x7 << 16) +/** Slow interleaved mode only. */ #define ADC_CR1_DUALMOD_SIM (0x8 << 16) +/** Alternate trigger mode only. */ #define ADC_CR1_DUALMOD_ATM (0x9 << 16) #define ADC_CR1_DUALMOD_MASK (0xF << 16) #define ADC_CR1_DUALMOD_SHIFT 16 +/**@}*/ /* DISCNUM[2:0]: Discontinous mode channel count. */ +/****************************************************************************/ +/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. +@ingroup STM32F1xx_adc_defines + +@{*/ #define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) #define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) #define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) @@ -195,29 +268,30 @@ #define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) #define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_SHIFT 13 +/**@}*/ -/* JDISCEN: Discontinous mode on injected channels. */ +/* JDISCEN: */ /** Discontinous mode on injected channels. */ #define ADC_CR1_JDISCEN (1 << 12) -/* DISCEN: Discontinous mode on regular channels. */ +/* DISCEN: */ /** Discontinous mode on regular channels. */ #define ADC_CR1_DISCEN (1 << 11) -/* JAUTO: Automatic Injection Group conversion. */ +/* JAUTO: */ /** Automatic Injection Group conversion. */ #define ADC_CR1_JAUTO (1 << 10) -/* AWDSGL: Enable the watchdog on a single channel in scan mode. */ +/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ #define ADC_CR1_AWDSGL (1 << 9) -/* SCAN: Scan mode. */ +/* SCAN: */ /** Scan mode. */ #define ADC_CR1_SCAN (1 << 8) -/* JEOCIE: Interrupt enable for injected channels. */ +/* JEOCIE: */ /** Interrupt enable for injected channels. */ #define ADC_CR1_JEOCIE (1 << 7) -/* AWDIE: Analog watchdog interrupt enable. */ +/* AWDIE: */ /** Analog watchdog interrupt enable. */ #define ADC_CR1_AWDIE (1 << 6) -/* EOCIE: Interrupt enable EOC. */ +/* EOCIE: */ /** Interrupt enable EOC. */ #define ADC_CR1_EOCIE (1 << 5) /* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ @@ -227,6 +301,12 @@ * ADC2: Analog channel 16 and 17 are internally connected to V_SS. * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS. */ +/****************************************************************************/ +/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ +/** @defgroup adc_watchdog_channel ADC watchdog channel +@ingroup STM32F1xx_adc_defines + +@{*/ #define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) #define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) #define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) @@ -247,39 +327,70 @@ #define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) #define ADC_CR1_AWDCH_MASK (0x1F << 0) #define ADC_CR1_AWDCH_SHIFT 0 +/**@}*/ /* --- ADC_CR2 values ------------------------------------------------------ */ -/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */ +/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */ #define ADC_CR2_TSVREFE (1 << 23) -/* SWSTART: Start conversion of regular channels. */ +/* SWSTART: */ /** Start conversion of regular channels. */ #define ADC_CR2_SWSTART (1 << 22) -/* JSWSTART: Start conversion of injected channels. */ +/* JSWSTART: */ /** Start conversion of injected channels. */ #define ADC_CR2_JSWSTART (1 << 21) -/* EXTTRIG: External trigger conversion mode for regular channels. */ +/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */ #define ADC_CR2_EXTTRIG (1 << 20) /* EXTSEL[2:0]: External event select for regular group. */ /* The following are only valid for ADC1 and ADC2. */ +/****************************************************************************/ +/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */ +/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2 +@ingroup STM32F1xx_adc_defines + +@{*/ +/** Timer 1 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17) +/** Timer 1 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17) +/** Timer 1 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) +/** Timer 2 Compare Output 2 */ #define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17) +/** Timer 3 Trigger Output */ #define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17) +/** Timer 4 Compare Output 4 */ #define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17) +/** External Interrupt 11 */ #define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17) +/** Software Trigger */ #define ADC_CR2_EXTSEL_SWSTART (0x7 << 17) +/**@}*/ /* The following are only valid for ADC3 */ +/****************************************************************************/ +/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */ +/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3 +@ingroup STM32F1xx_adc_defines + +@{*/ +/** Timer 2 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17) +/** Timer 2 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) +/** Timer 8 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17) +/** Timer 8 Trigger Output */ #define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17) +/** Timer 5 Compare Output 1 */ #define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17) +/** Timer 5 Compare Output 3 */ #define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17) +/**@}*/ #define ADC_CR2_EXTSEL_MASK (0x7 << 17) #define ADC_CR2_EXTSEL_SHIFT 17 @@ -291,21 +402,54 @@ /* JEXTSEL[2:0]: External event selection for injected group. */ /* The following are only valid for ADC1 and ADC2. */ +/****************************************************************************/ +/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */ +/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2 +@ingroup STM32F1xx_adc_defines + +@{*/ +/** Timer 1 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) +/** Timer 1 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) +/** Timer 2 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12) +/** Timer 2 Compare Output 1 */ #define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12) +/** Timer 3 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12) +/** Timer 4 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12) +/** External Interrupt 15 */ #define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12) +/** Injected Software Trigger */ #define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ +/**@}*/ /* The following are the different meanings for ADC3 only. */ +/****************************************************************************/ +/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */ +/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3 +@ingroup STM32F1xx_adc_defines + +@{*/ +/** Timer 1 Trigger Output */ +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) +/** Timer 1 Compare Output 4 */ +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) +/** Timer 4 Compare Output 3 */ #define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12) +/** Timer 8 Compare Output 2 */ #define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12) +/** Timer 8 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12) +/** Timer 5 Trigger Output */ #define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12) +/** Timer53 Compare Output 4 */ #define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12) +/** Injected Software Trigger */ +#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ +/**@}*/ #define ADC_CR2_JEXTSEL_MASK (0x7 << 12) #define ADC_CR2_JEXTSEL_SHIFT 12 @@ -340,7 +484,6 @@ #define ADC_CR2_ADON (1 << 0) /* --- ADC_SMPR1 values ---------------------------------------------------- */ - #define ADC_SMPR1_SMP17_LSB 21 #define ADC_SMPR1_SMP16_LSB 18 #define ADC_SMPR1_SMP15_LSB 15 @@ -357,6 +500,12 @@ #define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) #define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) #define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) +/****************************************************************************/ +/* ADC_SMPR1 ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1 +@ingroup STM32F1xx_adc_defines + +@{*/ #define ADC_SMPR1_SMP_1DOT5CYC 0x0 #define ADC_SMPR1_SMP_7DOT5CYC 0x1 #define ADC_SMPR1_SMP_13DOT5CYC 0x2 @@ -365,6 +514,7 @@ #define ADC_SMPR1_SMP_55DOT5CYC 0x5 #define ADC_SMPR1_SMP_71DOT5CYC 0x6 #define ADC_SMPR1_SMP_239DOT5CYC 0x7 +/**@}*/ /* --- ADC_SMPR2 values ---------------------------------------------------- */ @@ -388,6 +538,12 @@ #define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) #define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) #define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) +/****************************************************************************/ +/* ADC_SMPR2 ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2 +@ingroup STM32F1xx_adc_defines + +@{*/ #define ADC_SMPR2_SMP_1DOT5CYC 0x0 #define ADC_SMPR2_SMP_7DOT5CYC 0x1 #define ADC_SMPR2_SMP_13DOT5CYC 0x2 @@ -396,9 +552,15 @@ #define ADC_SMPR2_SMP_55DOT5CYC 0x5 #define ADC_SMPR2_SMP_71DOT5CYC 0x6 #define ADC_SMPR2_SMP_239DOT5CYC 0x7 +/**@}*/ /* --- ADC_SMPRx generic values -------------------------------------------- */ +/****************************************************************************/ +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection Generic +@ingroup STM32F1xx_adc_defines +@{*/ #define ADC_SMPR_SMP_1DOT5CYC 0x0 #define ADC_SMPR_SMP_7DOT5CYC 0x1 #define ADC_SMPR_SMP_13DOT5CYC 0x2 @@ -407,6 +569,7 @@ #define ADC_SMPR_SMP_55DOT5CYC 0x5 #define ADC_SMPR_SMP_71DOT5CYC 0x6 #define ADC_SMPR_SMP_239DOT5CYC 0x7 +/**@}*/ /* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ @@ -429,6 +592,13 @@ #define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) #define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) #define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) +/* TODO Fix error +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) +*/ /* --- ADC_SQR2 values ----------------------------------------------------- */ @@ -444,6 +614,14 @@ #define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) #define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) #define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) +/* TODO Fix error +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) +*/ /* --- ADC_SQR3 values ----------------------------------------------------- */ @@ -459,7 +637,14 @@ #define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) #define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) #define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) - +/* TODO Fix error +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) +*/ /* --- ADC_JSQR values ----------------------------------------------------- */ #define ADC_JSQR_JL_LSB 20 @@ -472,6 +657,13 @@ #define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) +/* TODO Fix error +#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) +#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) +#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) +#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) +*/ /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ @@ -481,12 +673,10 @@ #define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) #define ADC_DATA_MSK (0xffff << ADC_DA) #define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) - /* ADC1 only (dual mode) */ + /* ADC1 only (dual mode) */ /* --- Function prototypes ------------------------------------------------- */ - -/* TODO */ void adc_enable_analog_watchdog_regular(u32 adc); void adc_disable_analog_watchdog_regular(u32 adc); void adc_enable_analog_watchdog_injected(u32 adc); @@ -533,3 +723,5 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); #endif +/**@}*/ + -- cgit v1.2.3