From e4f84278f2b62dee7b4e0ac718c7c6ce998240ba Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sun, 22 Jul 2012 21:58:09 +0000 Subject: Add most of the rcc functions. (Add the forgotten gpio.c file from before) --- .../l1/stm32l-discovery/miniblink/miniblink.c | 4 +- include/libopencm3/stm32/l1/rcc.h | 7 +- lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/gpio.c | 146 +++++++++ lib/stm32/l1/rcc.c | 357 +++++++++++++++++++++ 5 files changed, 511 insertions(+), 5 deletions(-) create mode 100644 lib/stm32/l1/gpio.c create mode 100644 lib/stm32/l1/rcc.c diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c index fbace3c..2f5c70f 100644 --- a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c +++ b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c @@ -29,9 +29,9 @@ void gpio_setup(void) { /* Enable GPIOB clock. */ /* Manually: */ - RCC_AHBENR |= RCC_AHBENR_GPIOBEN; + //RCC_AHBENR |= RCC_AHBENR_GPIOBEN; /* Using API functions: */ - //rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN); + rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN); /* Set GPIO6 (in GPIO port B) to 'output push-pull'. */ /* Using API functions: */ diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 07d3692..209d24f 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -84,6 +84,11 @@ LGPL License Terms @ref lgpl_license #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) +#define RCC_CR_RTCPRE_DIV2 0 +#define RCC_CR_RTCPRE_DIV4 1 +#define RCC_CR_RTCPRE_DIV8 2 +#define RCC_CR_RTCPRE_DIV18 3 + /* --- RCC_ICSCR values ---------------------------------------------------- */ // TODO @@ -360,7 +365,6 @@ typedef enum { PLL, HSE, HSI, MSI, LSE, LSI } osc_t; -#if FINISHED == 0 void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -400,6 +404,5 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); void rcc_backupdomain_reset(void); -#endif #endif diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 543c416..9bd942d 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = vector.o desig.o crc.o gpio.o +OBJS = vector.o desig.o crc.o gpio.o rcc.o VPATH += ../../usb:../ diff --git a/lib/stm32/l1/gpio.c b/lib/stm32/l1/gpio.c new file mode 100644 index 0000000..2314bd4 --- /dev/null +++ b/lib/stm32/l1/gpio.c @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * + * This is virtually a carbon copy of the F4 code... + * TODO: make this code shared by f2, f4, l1 + */ + +#include + +void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) +{ + u16 i; + u32 moder, pupd; + + /* + * We want to set the config only for the pins mentioned in gpios, + * but keeping the others, so read out the actual config first. + */ + moder = GPIO_MODER(gpioport); + pupd = GPIO_PUPDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + + moder &= ~GPIO_MODE_MASK(i); + moder |= GPIO_MODE(i, mode); + pupd &= ~GPIO_PUPD_MASK(i); + pupd |= GPIO_PUPD(i, pull_up_down); + } + + /* Set mode and pull up/down control registers. */ + GPIO_MODER(gpioport) = moder; + GPIO_PUPDR(gpioport) = pupd; +} + +void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) +{ + u16 i; + u32 ospeedr; + + if (otype == GPIO_OTYPE_OD) + GPIO_OTYPER(gpioport) |= gpios; + else + GPIO_OTYPER(gpioport) &= ~gpios; + + ospeedr = GPIO_OSPEEDR(gpioport); + + for (i = 0; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + ospeedr &= ~GPIO_OSPEED_MASK(i); + ospeedr |= GPIO_OSPEED(i, speed); + } + + GPIO_OSPEEDR(gpioport) = ospeedr; +} + +void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) +{ + u16 i; + u32 afrl, afrh; + + afrl = GPIO_AFRL(gpioport); + afrh = GPIO_AFRH(gpioport); + + for (i = 0; i < 8; i++) { + if (!((1 << i) & gpios)) + continue; + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR(i, alt_func_num); + } + + for (i = 8; i < 16; i++) { + if (!((1 << i) & gpios)) + continue; + afrl &= ~GPIO_AFR_MASK(i - 8); + afrh |= GPIO_AFR(i - 8, alt_func_num); + } + + GPIO_AFRL(gpioport) = afrl; + GPIO_AFRH(gpioport) = afrh; +} + +void gpio_set(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u16 gpios) +{ + GPIO_BSRR(gpioport) = gpios << 16; +} + +u16 gpio_get(u32 gpioport, u16 gpios) +{ + return gpio_port_read(gpioport) & gpios; +} + +void gpio_toggle(u32 gpioport, u16 gpios) +{ + GPIO_ODR(gpioport) ^= gpios; +} + +u16 gpio_port_read(u32 gpioport) +{ + return (u16)GPIO_IDR(gpioport); +} + +void gpio_port_write(u32 gpioport, u16 data) +{ + GPIO_ODR(gpioport) = data; +} + +void gpio_port_config_lock(u32 gpioport, u16 gpios) +{ + u32 reg32; + + /* Special "Lock Key Writing Sequence", see datasheet. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */ + GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ + reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ + + /* Tell the compiler the variable is actually used. It will get optimized out anyways. */ + reg32 = reg32; + + /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ +} diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c new file mode 100644 index 0000000..a023622 --- /dev/null +++ b/lib/stm32/l1/rcc.c @@ -0,0 +1,357 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * Based on the F4 code... + */ + +#include + +/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ +u32 rcc_ppre1_frequency = 2097000; +u32 rcc_ppre2_frequency = 2097000; + +void rcc_osc_ready_int_clear(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + case MSI: + RCC_CIR |= RCC_CIR_MSIRDYC; + break; + } +} + +void rcc_osc_ready_int_enable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + case MSI: + RCC_CIR |= RCC_CIR_MSIRDYIE; + break; + } +} + +void rcc_osc_ready_int_disable(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + case MSI: + RCC_CIR &= ~RCC_CIR_MSIRDYIE; + break; + } +} + +int rcc_osc_ready_int_flag(osc_t osc) +{ + switch (osc) { + case PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + case MSI: + return ((RCC_CIR & RCC_CIR_MSIRDYF) != 0); + break; + } + + /* Shouldn't be reached. */ + return -1; +} + +void rcc_css_int_clear(void) +{ + RCC_CIR |= RCC_CIR_CSSC; +} + +int rcc_css_int_flag(void) +{ + return ((RCC_CIR & RCC_CIR_CSSF) != 0); +} + +void rcc_wait_for_osc_ready(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case MSI: + while ((RCC_CR & RCC_CR_MSIRDY) == 0); + break; + case LSE: + while ((RCC_CSR & RCC_CSR_LSERDY) == 0); + break; + case LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } +} + +void rcc_wait_for_sysclk_status(osc_t osc) +{ + switch (osc) { + case PLL: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_PLLCLK); + break; + case HSE: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSECLK); + break; + case HSI: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSICLK); + break; + case MSI: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_MSICLK); + break; + default: + /* Shouldn't be reached. */ + break; + } +} + +void rcc_osc_on(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case MSI: + RCC_CR |= RCC_CR_MSION; + break; + case HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case HSI: + RCC_CR |= RCC_CR_HSION; + break; + case LSE: + RCC_CSR |= RCC_CSR_LSEON; + break; + case LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } +} + +void rcc_osc_off(osc_t osc) +{ + switch (osc) { + case PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case MSI: + RCC_CR &= ~RCC_CR_MSION; + break; + case HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case LSE: + RCC_CSR &= ~RCC_CSR_LSEON; + break; + case LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } +} + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +void rcc_osc_bypass_enable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR |= RCC_CR_HSEBYP; + break; + case LSE: + RCC_CSR |= RCC_CSR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + case MSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_osc_bypass_disable(osc_t osc) +{ + switch (osc) { + case HSE: + RCC_CR &= ~RCC_CR_HSEBYP; + break; + case LSE: + RCC_CSR &= ~RCC_CSR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + case MSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } +} + +void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) +{ + *reg |= en; +} + +void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) +{ + *reg &= ~en; +} + +void rcc_peripheral_reset(volatile u32 *reg, u32 reset) +{ + *reg |= reset; +} + +void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) +{ + *reg &= ~clear_reset; +} + +void rcc_set_sysclk_source(u32 clk) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | clk); +} + +void rcc_set_pll_source(u32 pllsrc) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(1 << 16); + RCC_CFGR = (reg32 | (pllsrc << 16)); +} + +void rcc_set_ppre2(u32 ppre2) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11)); + RCC_CFGR = (reg32 | (ppre2 << 11)); +} + +void rcc_set_ppre1(u32 ppre1) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8)); + RCC_CFGR = (reg32 | (ppre1 << 8)); +} + +void rcc_set_hpre(u32 hpre) +{ + u32 reg32; + + reg32 = RCC_CFGR; + reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); + RCC_CFGR = (reg32 | (hpre << 4)); +} + +void rcc_set_rtcpre(u32 rtcpre) +{ + u32 reg32; + + reg32 = RCC_CR; + reg32 &= ~((1 << 30) | (1 << 29)); + RCC_CR = (reg32 | (rtcpre << 29)); +} + +u32 rcc_system_clock_source(void) +{ + /* Return the clock source which is used as system clock. */ + return ((RCC_CFGR & 0x000c) >> 2); +} + -- cgit v1.2.3