From 1029597e7034bc088179227efe84bc0c00391082 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 5 Dec 2012 16:05:40 +1030 Subject: Move DAC to common area (Note there are now dummy source files dac.c (and others) that are not compiled but are needed for documentation). --- include/libopencm3/stm32/common/dac_common_all.h | 403 ++++++++++++++++++ include/libopencm3/stm32/dac.h | 409 +----------------- include/libopencm3/stm32/f1/dac.h | 40 ++ include/libopencm3/stm32/f2/dac.h | 40 ++ include/libopencm3/stm32/f4/dac.h | 40 ++ include/libopencm3/stm32/l1/dac.h | 40 ++ lib/stm32/common/dac_common_all.c | 516 ++++++++++++++++++++++ lib/stm32/dac.c | 520 ----------------------- lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/dac.c | 28 ++ lib/stm32/f2/Makefile | 2 +- lib/stm32/f2/dac.c | 28 ++ lib/stm32/f4/Makefile | 2 +- lib/stm32/f4/dac.c | 28 ++ lib/stm32/l1/Makefile | 7 +- lib/stm32/l1/dac.c | 28 ++ 16 files changed, 1209 insertions(+), 926 deletions(-) create mode 100644 include/libopencm3/stm32/common/dac_common_all.h create mode 100644 include/libopencm3/stm32/f1/dac.h create mode 100644 include/libopencm3/stm32/f2/dac.h create mode 100644 include/libopencm3/stm32/f4/dac.h create mode 100644 include/libopencm3/stm32/l1/dac.h create mode 100644 lib/stm32/common/dac_common_all.c delete mode 100644 lib/stm32/dac.c create mode 100644 lib/stm32/f1/dac.c create mode 100644 lib/stm32/f2/dac.c create mode 100644 lib/stm32/f4/dac.c create mode 100644 lib/stm32/l1/dac.c diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h new file mode 100644 index 0000000..c843c55 --- /dev/null +++ b/include/libopencm3/stm32/common/dac_common_all.h @@ -0,0 +1,403 @@ +/** @addtogroup dac_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_DAC_COMMON_ALL_H +#define LIBOPENCM3_DAC_COMMON_ALL_H + +#include + + +/* --- DAC registers ------------------------------------------------------- */ + +/* DAC control register (DAC_CR) */ +#define DAC_CR MMIO32(DAC_BASE + 0x00) + +/* DAC software trigger register (DAC_SWTRIGR) */ +#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) + +/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ +#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) + +/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ +#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) + +/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ +#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) + +/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ +#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) + +/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ +#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) + +/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ +#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) + +/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ +#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) + +/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ +#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) + +/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ +#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) + +/* DAC channel1 data output register (DAC_DOR1) */ +#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) + +/* DAC channel2 data output register (DAC_DOR2) */ +#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) + + +/* --- DAC_CR values ------------------------------------------------------- */ + +/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE2 (1 << 29) + +/* DMAEN2: DAC channel2 DMA enable */ +#define DAC_CR_DMAEN2 (1 << 28) + +/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ +/* DAC_CR_MAMP2_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP2_SHIFT 24 +/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values +@ingroup STM32F_dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 +@{*/ +#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) +/**@}*/ + +/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + */ +#define DAC_CR_WAVE2_SHIFT 22 +#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) +/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable +@ingroup STM32F_dac_defines + +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) +#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) +/**@}*/ + +/* TSEL2[2:0]: DAC channel2 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event + * T8: Timer 8 TRGO event + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL2_SHIFT 19 +/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection +@ingroup STM32F_dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is not valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) +@{*/ +#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) +/**@}*/ + +/* TEN2: DAC channel2 trigger enable */ +#define DAC_CR_TEN2 (1 << 18) + +/* BOFF2: DAC channel2 output buffer disable */ +#define DAC_CR_BOFF2 (1 << 17) + +/* EN2: DAC channel2 enable */ +#define DAC_CR_EN2 (1 << 16) + +/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE1 (1 << 13) + +/* DMAEN1: DAC channel1 DMA enable */ +#define DAC_CR_DMAEN1 (1 << 12) + +/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ +/* DAC_CR_MAMP1_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP1_SHIFT 8 +/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values +@ingroup STM32F_dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 +@{*/ +#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) +/**@}*/ + +/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + */ +#define DAC_CR_WAVE1_SHIFT 6 +#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) +/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable +@ingroup STM32F_dac_defines + +@li DIS: wave generation disabled +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) +#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) +/**@}*/ + +/* TSEL1[2:0]: DAC channel1 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event in connectivity line devices + * T8: Timer 8 TRGO event in high-density and XL-density devices + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL1_SHIFT 3 +/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection +@ingroup STM32F_dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line 9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is not valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). +@{*/ +#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) +/**@}*/ + +/* TEN1: DAC channel1 trigger enable */ +#define DAC_CR_TEN1 (1 << 2) + +/* BOFF1: DAC channel1 output buffer disable */ +#define DAC_CR_BOFF1 (1 << 1) + +/* EN1: DAC channel1 enable */ +#define DAC_CR_EN1 (1 << 0) + + +/* --- DAC_SWTRIGR values -------------------------------------------------- */ + +/* SWTRIG2: DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) + +/* SWTRIG1: DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) + + +/* --- DAC_DHR12R1 values -------------------------------------------------- */ +#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12L1 values -------------------------------------------------- */ +#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) +#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R1 values --------------------------------------------------- */ +#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12R2 values -------------------------------------------------- */ +#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) + + +/* --- DAC_DHR12L2 values -------------------------------------------------- */ +#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) +#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R2 values --------------------------------------------------- */ +#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12RD values -------------------------------------------------- */ +#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) +#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12LD values -------------------------------------------------- */ +#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) +#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8RD values --------------------------------------------------- */ +#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) +#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) +#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DOR1 values ----------------------------------------------------- */ +#define DAC_DOR1_DACC1DOR_LSB (1 << 0) +#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) + + +/* --- DAC_DOR2 values ----------------------------------------------------- */ +#define DAC_DOR2_DACC2DOR_LSB (1 << 0) +#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) + +/** DAC channel identifier */ +typedef enum { + CHANNEL_1, CHANNEL_2, CHANNEL_D +} data_channel; + +/** DAC data size (8/12 bits), alignment (right/left) */ +typedef enum { + RIGHT8, RIGHT12, LEFT12 +} data_align; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dac_enable(data_channel dac_channel); +void dac_disable(data_channel dac_channel); +void dac_buffer_enable(data_channel dac_channel); +void dac_buffer_disable(data_channel dac_channel); +void dac_dma_enable(data_channel dac_channel); +void dac_dma_disable(data_channel dac_channel); +void dac_trigger_enable(data_channel dac_channel); +void dac_trigger_disable(data_channel dac_channel); +void dac_set_trigger_source(u32 dac_trig_src); +void dac_set_waveform_generation(u32 dac_wave_ens); +void dac_disable_waveform_generation(data_channel dac_channel); +void dac_set_waveform_characteristics(u32 dac_mamp); +void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel); +void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format); +void dac_software_trigger(data_channel dac_channel); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h index 75d4edb..242ef89 100644 --- a/include/libopencm3/stm32/dac.h +++ b/include/libopencm3/stm32/dac.h @@ -1,24 +1,8 @@ -/** @defgroup STM32F_dac_defines DAC Defines - -@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Felix Held -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ +/* This provides unification of code over STM32F subfamilies */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2012 Felix Held - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -33,386 +17,15 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -/**@{*/ - -#ifndef LIBOPENCM3_DAC_H -#define LIBOPENCM3_DAC_H - -#include -#include - - -/* --- DAC registers ------------------------------------------------------- */ - -/* DAC control register (DAC_CR) */ -#define DAC_CR MMIO32(DAC_BASE + 0x00) - -/* DAC software trigger register (DAC_SWTRIGR) */ -#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) - -/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ -#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) - -/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ -#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) - -/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ -#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) - -/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ -#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) - -/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ -#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) - -/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ -#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) - -/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ -#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) - -/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ -#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) - -/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ -#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) - -/* DAC channel1 data output register (DAC_DOR1) */ -#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) - -/* DAC channel2 data output register (DAC_DOR2) */ -#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) - - -/* --- DAC_CR values ------------------------------------------------------- */ - -/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ -/* doesn't exist in most members of the STM32F1 family */ -#define DAC_CR_DMAUDRIE2 (1 << 29) - -/* DMAEN2: DAC channel2 DMA enable */ -#define DAC_CR_DMAEN2 (1 << 28) - -/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ -/* DAC_CR_MAMP2_n: - * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 - */ -#define DAC_CR_MAMP2_SHIFT 24 -/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values -@ingroup STM32F_dac_defines - -Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 -@{*/ -#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) -#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) -/**@}*/ - -/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ -/* Legend: - * DIS: wave generation disabled - * NOISE: Noise wave generation enabled - * TRI: Triangle wave generation enabled - * - * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) - */ -#define DAC_CR_WAVE2_SHIFT 22 -#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) -/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable -@ingroup STM32F_dac_defines - -@li NOISE: Noise wave generation enabled -@li TRI: Triangle wave generation enabled - -@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) -@{*/ -#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) -#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) -/**@}*/ - -/* TSEL2[2:0]: DAC channel2 trigger selection */ -/* Legend: - * - * T6: Timer 6 TRGO event - * T3: Timer 3 TRGO event - * T8: Timer 8 TRGO event - * T7: Timer 7 TRGO event - * T5: Timer 5 TRGO event - * T15: Timer 15 TRGO event - * T2: Timer 2 TRGO event - * T4: Timer 4 TRGO event - * E9: External line9 - * SW: Software trigger - * - * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) - * Note: T3 == T8; T5 == T15; not both present on one device - * Note: this is *not* valid for the STM32L1 family - */ -#define DAC_CR_TSEL2_SHIFT 19 -/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection -@ingroup STM32F_dac_defines - -@li T6: Timer 6 TRGO event -@li T3: Timer 3 TRGO event -@li T8: Timer 8 TRGO event -@li T7: Timer 7 TRGO event -@li T5: Timer 5 TRGO event -@li T15: Timer 15 TRGO event -@li T2: Timer 2 TRGO event -@li T4: Timer 4 TRGO event -@li E9: External line9 -@li SW: Software trigger - -@note: Refer to the timer documentation for details of the TRGO event. -@note: T3 replaced by T8 and T5 replaced by T15 in some devices. -@note: this is not valid for the STM32L1 family. -@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) -@{*/ -#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) -#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) -/**@}*/ - -/* TEN2: DAC channel2 trigger enable */ -#define DAC_CR_TEN2 (1 << 18) - -/* BOFF2: DAC channel2 output buffer disable */ -#define DAC_CR_BOFF2 (1 << 17) - -/* EN2: DAC channel2 enable */ -#define DAC_CR_EN2 (1 << 16) - -/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ -/* doesn't exist in most members of the STM32F1 family */ -#define DAC_CR_DMAUDRIE1 (1 << 13) - -/* DMAEN1: DAC channel1 DMA enable */ -#define DAC_CR_DMAEN1 (1 << 12) - -/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ -/* DAC_CR_MAMP1_n: - * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 - */ -#define DAC_CR_MAMP1_SHIFT 8 -/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values -@ingroup STM32F_dac_defines - -Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 -@{*/ -#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) -#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) -/**@}*/ - -/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ -/* Legend: - * DIS: wave generation disabled - * NOISE: Noise wave generation enabled - * TRI: Triangle wave generation enabled - * - * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) - */ -#define DAC_CR_WAVE1_SHIFT 6 -#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) -/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable -@ingroup STM32F_dac_defines - -@li DIS: wave generation disabled -@li NOISE: Noise wave generation enabled -@li TRI: Triangle wave generation enabled - -@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) -@{*/ -#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) -#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) -/**@}*/ - -/* TSEL1[2:0]: DAC channel1 trigger selection */ -/* Legend: - * - * T6: Timer 6 TRGO event - * T3: Timer 3 TRGO event in connectivity line devices - * T8: Timer 8 TRGO event in high-density and XL-density devices - * T7: Timer 7 TRGO event - * T5: Timer 5 TRGO event - * T15: Timer 15 TRGO event - * T2: Timer 2 TRGO event - * T4: Timer 4 TRGO event - * E9: External line9 - * SW: Software trigger - * - * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) - * Note: T3 == T8; T5 == T15; not both present on one device - * Note: this is *not* valid for the STM32L1 family - */ -#define DAC_CR_TSEL1_SHIFT 3 -/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection -@ingroup STM32F_dac_defines - -@li T6: Timer 6 TRGO event -@li T3: Timer 3 TRGO event -@li T8: Timer 8 TRGO event -@li T7: Timer 7 TRGO event -@li T5: Timer 5 TRGO event -@li T15: Timer 15 TRGO event -@li T2: Timer 2 TRGO event -@li T4: Timer 4 TRGO event -@li E9: External line 9 -@li SW: Software trigger - -@note: Refer to the timer documentation for details of the TRGO event. -@note: T3 replaced by T8 and T5 replaced by T15 in some devices. -@note: this is not valid for the STM32L1 family. -@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). -@{*/ -#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) -#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) -/**@}*/ - -/* TEN1: DAC channel1 trigger enable */ -#define DAC_CR_TEN1 (1 << 2) - -/* BOFF1: DAC channel1 output buffer disable */ -#define DAC_CR_BOFF1 (1 << 1) - -/* EN1: DAC channel1 enable */ -#define DAC_CR_EN1 (1 << 0) - - -/* --- DAC_SWTRIGR values -------------------------------------------------- */ - -/* SWTRIG2: DAC channel2 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) - -/* SWTRIG1: DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) - - -/* --- DAC_DHR12R1 values -------------------------------------------------- */ -#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) - - -/* --- DAC_DHR12L1 values -------------------------------------------------- */ -#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) -#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8R1 values --------------------------------------------------- */ -#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) -#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) - - -/* --- DAC_DHR12R2 values -------------------------------------------------- */ -#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) -#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) - - -/* --- DAC_DHR12L2 values -------------------------------------------------- */ -#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) -#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8R2 values --------------------------------------------------- */ -#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) -#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) - - -/* --- DAC_DHR12RD values -------------------------------------------------- */ -#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) -#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) -#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) - - -/* --- DAC_DHR12LD values -------------------------------------------------- */ -#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) -#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) -#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) - - -/* --- DAC_DHR8RD values --------------------------------------------------- */ -#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) -#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) -#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) -#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) - - -/* --- DAC_DOR1 values ----------------------------------------------------- */ -#define DAC_DOR1_DACC1DOR_LSB (1 << 0) -#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) - - -/* --- DAC_DOR2 values ----------------------------------------------------- */ -#define DAC_DOR2_DACC2DOR_LSB (1 << 0) -#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) - -/** DAC channel identifier */ -typedef enum { - CHANNEL_1, CHANNEL_2, CHANNEL_D -} data_channel; - -/** DAC data size (8/12 bits), alignment (right/left) */ -typedef enum { - RIGHT8, RIGHT12, LEFT12 -} data_align; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void dac_enable(data_channel dac_channel); -void dac_disable(data_channel dac_channel); -void dac_buffer_enable(data_channel dac_channel); -void dac_buffer_disable(data_channel dac_channel); -void dac_dma_enable(data_channel dac_channel); -void dac_dma_disable(data_channel dac_channel); -void dac_trigger_enable(data_channel dac_channel); -void dac_trigger_disable(data_channel dac_channel); -void dac_set_trigger_source(u32 dac_trig_src); -void dac_set_waveform_generation(u32 dac_wave_ens); -void dac_disable_waveform_generation(data_channel dac_channel); -void dac_set_waveform_characteristics(u32 dac_mamp); -void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel); -void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format); -void dac_software_trigger(data_channel dac_channel); - -END_DECLS - +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." #endif -/**@}*/ diff --git a/include/libopencm3/stm32/f1/dac.h b/include/libopencm3/stm32/f1/dac.h new file mode 100644 index 0000000..a4e07aa --- /dev/null +++ b/include/libopencm3/stm32/f1/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F1xx DAC + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f2/dac.h b/include/libopencm3/stm32/f2/dac.h new file mode 100644 index 0000000..87bd456 --- /dev/null +++ b/include/libopencm3/stm32/f2/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F2xx DAC + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f4/dac.h b/include/libopencm3/stm32/f4/dac.h new file mode 100644 index 0000000..4c6b43f --- /dev/null +++ b/include/libopencm3/stm32/f4/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F4xx DAC + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/l1/dac.h b/include/libopencm3/stm32/l1/dac.h new file mode 100644 index 0000000..9ec57ea --- /dev/null +++ b/include/libopencm3/stm32/l1/dac.h @@ -0,0 +1,40 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32L1xx DAC + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include +#include + +#endif + diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c new file mode 100644 index 0000000..a6be233 --- /dev/null +++ b/lib/stm32/common/dac_common_all.c @@ -0,0 +1,516 @@ +/** @addtogroup dac_file + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 18 August 2012 + +This library supports the Digital to Analog Conversion System in the +STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. + +The DAC is present only in a limited set of devices, notably some +of the connection line, high density and XL devices. + +Two DAC channels are available, however unlike the ADC channels these +are separate DAC devices controlled by the same register block. + +The DAC is on APB1. Its clock must be enabled in RCC and the GPIO +ports set to alternate function output before it can be used. +The digital output driver is disabled so the output driver mode +(push-pull/open drain) is arbitrary. + +The DAC has a holding (buffer) register and an output register from +which the analog output is derived. The holding register must be +loaded first. If triggering is enabled the output register is loaded +from the holding register after a trigger occurs. If triggering is +not enabled the holding register contents are transferred directly +to the output register. + +@note To avoid nonlinearities, do not allow outputs to range close +to zero or V_analog. + +@section dac_api_dual Dual Channel Conversion + +There are dual modes in which both DACs are used to output data +simultaneously or independently on both channels. The data must be +presented according to the formats described in the datasheets. A +convenience function @ref dac_load_data_buffer_dual is provided +for software controlled use. + +A variety of modes are available depending on whether independent +or simultaneous output is desired, and whether waveforms are to be +superimposed. Refer to the datasheets. + +If DMA is used, only enable it for one of the channels. The DMA +requests will then serve data in dual format to the data register +dedicated to dual mode. The data will then be split and loaded to the +appropriate DAC following the next trigger. There are three registers +available, one for each of the formats: 12 bit right-aligned, 12 bit +left-aligned and 8 bit right-aligned. The desired format is determined +by specifying the appropriate register to the DMA controller. + +@section dac_api_basic_ex Basic DAC handling API. + +Set the DAC's GPIO port to any alternate function output mode. Enable the +DAC clock. Enable the DAC, set a trigger source and load the buffer +with the first value. After the DAC is triggered, load the buffer with +the next value. This example uses software triggering and added noise. +The trigger and further buffer load calls are made when data is to be +sent out. + +@code + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN); + dac_disable(CHANNEL_1); + dac_set_waveform_characteristics(DAC_CR_MAMP1_8); + dac_set_waveform_generation(DAC_CR_WAVE1_NOISE); + dac_enable(CHANNEL_1); + dac_set_trigger_source(DAC_CR_TSEL1_SW); + dac_load_data_buffer_single(0, RIGHT12, CHANNEL_1); + .... + dac_software_trigger(CHANNEL_1); + dac_load_data_buffer_single(value, RIGHT12, CHANNEL_1); +@endcode + +@section dac_api_dma_ex Simultaneous Dual DAC with DMA. + +This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read +16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD. +Both DAC channels are enabled, and both triggers are set to the same timer +2 input as required for simultaneous operation. DMA is enabled for DAC channel +1 only to ensure that only one DMA request is generated. + +@code + dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT); + dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT); + dma_set_read_from_memory(DMA2,DMA_CHANNEL3); + dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD); + dma_enable_channel(DMA2,DMA_CHANNEL3); + ... + dac_trigger_enable(CHANNEL_D); + dac_set_trigger_source(DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2); + dac_dma_enable(CHANNEL_1); + dac_enable(CHANNEL_D); +@endcode + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +#define MASK8 0xFF +#define MASK12 0xFFF + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Enable. + +Enable a digital to analog converter channel. After setting this enable, the DAC +requires a twakeup time typically around 10 microseconds before it +actually wakes up. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_EN1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_EN2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_EN1 | DAC_CR_EN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Disable. + +Disable a digital to analog converter channel. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_EN1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_EN2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_EN1 | DAC_CR_EN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Output Buffer Enable. + +Enable a digital to analog converter channel output drive buffer. This is an optional +amplifying buffer that provides additional drive for the output signal. The +buffer is enabled by default after a reset and needs to be explicitly disabled +if required. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_buffer_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_BOFF1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_BOFF2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_BOFF1 | DAC_CR_BOFF2); + break; + } +} +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Output Buffer Disable. + +Disable a digital to analog converter channel output drive buffer. Disabling this will +reduce power consumption slightly and will increase the output impedance of the DAC. +The buffers are enabled by default after a reset. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_buffer_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_BOFF1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_BOFF2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_BOFF1 | DAC_CR_BOFF2); + break; + } +} +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel DMA Enable. + +Enable a digital to analog converter channel DMA mode (connected to DMA2 channel +3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is +generated following an external trigger. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_dma_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_DMAEN1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_DMAEN2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel DMA Disable. + +Disable a digital to analog converter channel DMA mode. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_dma_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_DMAEN1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_DMAEN2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Trigger Enable. + +Enable a digital to analog converter channel external trigger mode. This allows an +external trigger to initiate register transfers from the buffer register to the DAC +output register, followed by a DMA transfer to the buffer register if DMA is enabled. +The trigger source must also be selected. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_trigger_enable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR |= DAC_CR_TEN1; + break; + case CHANNEL_2: + DAC_CR |= DAC_CR_TEN2; + break; + case CHANNEL_D: + DAC_CR |= (DAC_CR_TEN1 | DAC_CR_TEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief DAC Channel Trigger Disable. + +Disable a digital to analog converter channel external trigger. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_trigger_disable(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_TEN1; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_TEN2; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_TEN1 | DAC_CR_TEN2); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set DAC Channel Trigger Source. + +Sets the digital to analog converter trigger source, which can be taken from various +timers, an external trigger or a software trigger. + +@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or +a logical OR of one of each of these to set both channels simultaneously. +*/ + +void dac_set_trigger_source(u32 dac_trig_src) +{ + DAC_CR |= dac_trig_src; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Enable and Set DAC Channel Waveform Generation. + +Enable the digital to analog converter waveform generation as either pseudo-random +noise or triangular wave. These signals are superimposed on existing output values +in the DAC output registers. + +@note The DAC trigger must be enabled for this to work. + +@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or +a logical OR of one of each of these to set both channels simultaneously. +*/ + +void dac_set_waveform_generation(u32 dac_wave_ens) +{ + DAC_CR |= dac_wave_ens; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Disable DAC Channel Waveform Generation. + +Disable a digital to analog converter channel superimposed waveform generation. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_disable_waveform_generation(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_CR &= ~DAC_CR_WAVE1_DIS; + break; + case CHANNEL_2: + DAC_CR &= ~DAC_CR_WAVE2_DIS; + break; + case CHANNEL_D: + DAC_CR &= ~(DAC_CR_WAVE1_DIS | DAC_CR_WAVE2_DIS); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude. + +Sets the digital to analog converter superimposed waveform generation characteristics. +@li If the noise generation mode is set, this sets the length of the PRBS sequence and +hence the amplitude of the output noise signal. Default setting is length 1. +@li If the triangle wave generation mode is set, this sets the amplitude of the +output signal as 2^(n)-1 where n is the parameter value. Default setting is 1. + +@note High amplitude levels of these waveforms can overload the DAC and distort the +signal output. +@note This must be called before enabling the DAC as the settings will then become read-only. +@note The DAC trigger must be enabled for this to work. + +@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR +of one of each of these to set both channels simultaneously. +*/ + +void dac_set_waveform_characteristics(u32 dac_mamp) +{ + DAC_CR |= dac_mamp; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Load DAC Data Register. + +Loads the appropriate digital to analog converter data register with 12 or 8 bit +data to be converted on a channel. The data can be aligned as follows: +@li right-aligned 8 bit data in bits 0-7 +@li right-aligned 12 bit data in bits 0-11 +@li left aligned 12 bit data in bits 4-15 + +This function can also be used to load the dual channel registers if the data is +formatted according to the datasheets: +@li right-aligned 8 bit data in bits 0-7 for channel 1 and 8-15 for channel 2 +@li right-aligned 12 bit data in bits 0-11 for channel 1 and 16-27 for channel 2 +@li left aligned 12 bit data in bits 4-15 for channel 1 and 20-31 for channel 2 + +@param[in] dac_data u32 with appropriate alignment. +@param[in] dac_data_format enum ::data_align. Alignment and size. +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel) +{ + if (dac_channel == CHANNEL_1) + { + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8R1 = dac_data; + break; + case RIGHT12: + DAC_DHR12R1 = dac_data; + break; + case LEFT12: + DAC_DHR12L1 = dac_data; + break; + } + } + else if (dac_channel == CHANNEL_2) + { + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8R2 = dac_data; + break; + case RIGHT12: + DAC_DHR12R2 = dac_data; + break; + case LEFT12: + DAC_DHR12L2 = dac_data; + break; + } + } + else + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8RD = dac_data; + break; + case RIGHT12: + DAC_DHR12RD = dac_data; + break; + case LEFT12: + DAC_DHR12LD = dac_data; + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Load DAC Dual Data Register. + +Loads the appropriate digital to analog converter dual data register with 12 or +8 bit data to be converted for both channels. This allows high bandwidth +simultaneous or independent analog output. The data in both channels are aligned +identically. + +@param[in] dac_data1 u32 for channel 1 with appropriate alignment. +@param[in] dac_data2 u32 for channel 2 with appropriate alignment. +@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit. +*/ + +void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format) +{ + switch (dac_data_format) { + case RIGHT8: + DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8)); + break; + case RIGHT12: + DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 12)); + break; + case LEFT12: + DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); + break; + } +} + +/*-----------------------------------------------------------------------------*/ +/** @brief Trigger the DAC by a Software Trigger. + +If the trigger source is set to be a software trigger, cause a trigger to occur. +The trigger is cleared by hardware after conversion. + +@param[in] dac_channel enum ::data_channel. +*/ + +void dac_software_trigger(data_channel dac_channel) +{ + switch (dac_channel) { + case CHANNEL_1: + DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG1; + break; + case CHANNEL_2: + DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG2; + break; + case CHANNEL_D: + DAC_SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2); + break; + } +} +/**@}*/ + diff --git a/lib/stm32/dac.c b/lib/stm32/dac.c deleted file mode 100644 index 55440bf..0000000 --- a/lib/stm32/dac.c +++ /dev/null @@ -1,520 +0,0 @@ -/** @defgroup STM32F_dac_file DAC - -@ingroup STM32F_files - -@brief libopencm3 STM32Fxx Digital to Analog Converter - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies - -@date 18 August 2012 - -This library supports the Digital to Analog Conversion System in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. - -The DAC is present only in a limited set of devices, notably some -of the connection line, high density and XL devices. - -Two DAC channels are available, however unlike the ADC channels these -are separate DAC devices controlled by the same register block. - -The DAC is on APB1. Its clock must be enabled in RCC and the GPIO -ports set to alternate function output before it can be used. -The digital output driver is disabled so the output driver mode -(push-pull/open drain) is arbitrary. - -The DAC has a holding (buffer) register and an output register from -which the analog output is derived. The holding register must be -loaded first. If triggering is enabled the output register is loaded -from the holding register after a trigger occurs. If triggering is -not enabled the holding register contents are transferred directly -to the output register. - -@note To avoid nonlinearities, do not allow outputs to range close -to zero or V_analog. - -@section dac_api_dual Dual Channel Conversion - -There are dual modes in which both DACs are used to output data -simultaneously or independently on both channels. The data must be -presented according to the formats described in the datasheets. A -convenience function @ref dac_load_data_buffer_dual is provided -for software controlled use. - -A variety of modes are available depending on whether independent -or simultaneous output is desired, and whether waveforms are to be -superimposed. Refer to the datasheets. - -If DMA is used, only enable it for one of the channels. The DMA -requests will then serve data in dual format to the data register -dedicated to dual mode. The data will then be split and loaded to the -appropriate DAC following the next trigger. There are three registers -available, one for each of the formats: 12 bit right-aligned, 12 bit -left-aligned and 8 bit right-aligned. The desired format is determined -by specifying the appropriate register to the DMA controller. - -@section dac_api_basic_ex Basic DAC handling API. - -Set the DAC's GPIO port to any alternate function output mode. Enable the -DAC clock. Enable the DAC, set a trigger source and load the buffer -with the first value. After the DAC is triggered, load the buffer with -the next value. This example uses software triggering and added noise. -The trigger and further buffer load calls are made when data is to be -sent out. - -@code - gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, - GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4); - rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN); - dac_disable(CHANNEL_1); - dac_set_waveform_characteristics(DAC_CR_MAMP1_8); - dac_set_waveform_generation(DAC_CR_WAVE1_NOISE); - dac_enable(CHANNEL_1); - dac_set_trigger_source(DAC_CR_TSEL1_SW); - dac_load_data_buffer_single(0, RIGHT12, CHANNEL_1); - .... - dac_software_trigger(CHANNEL_1); - dac_load_data_buffer_single(value, RIGHT12, CHANNEL_1); -@endcode - -@section dac_api_dma_ex Simultaneous Dual DAC with DMA. - -This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read -16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD. -Both DAC channels are enabled, and both triggers are set to the same timer -2 input as required for simultaneous operation. DMA is enabled for DAC channel -1 only to ensure that only one DMA request is generated. - -@code - dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT); - dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT); - dma_set_read_from_memory(DMA2,DMA_CHANNEL3); - dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD); - dma_enable_channel(DMA2,DMA_CHANNEL3); - ... - dac_trigger_enable(CHANNEL_D); - dac_set_trigger_source(DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2); - dac_dma_enable(CHANNEL_1); - dac_enable(CHANNEL_D); -@endcode - -LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 Ken Sarkies - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#include - -#define MASK8 0xFF -#define MASK12 0xFFF - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Enable. - -Enable a digital to analog converter channel. After setting this enable, the DAC -requires a twakeup time typically around 10 microseconds before it -actually wakes up. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_EN1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_EN2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_EN1 | DAC_CR_EN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Disable. - -Disable a digital to analog converter channel. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_EN1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_EN2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_EN1 | DAC_CR_EN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Output Buffer Enable. - -Enable a digital to analog converter channel output drive buffer. This is an optional -amplifying buffer that provides additional drive for the output signal. The -buffer is enabled by default after a reset and needs to be explicitly disabled -if required. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_buffer_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_BOFF1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_BOFF2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_BOFF1 | DAC_CR_BOFF2); - break; - } -} -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Output Buffer Disable. - -Disable a digital to analog converter channel output drive buffer. Disabling this will -reduce power consumption slightly and will increase the output impedance of the DAC. -The buffers are enabled by default after a reset. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_buffer_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_BOFF1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_BOFF2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_BOFF1 | DAC_CR_BOFF2); - break; - } -} -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel DMA Enable. - -Enable a digital to analog converter channel DMA mode (connected to DMA2 channel -3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is -generated following an external trigger. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_dma_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_DMAEN1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_DMAEN2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel DMA Disable. - -Disable a digital to analog converter channel DMA mode. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_dma_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_DMAEN1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_DMAEN2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Trigger Enable. - -Enable a digital to analog converter channel external trigger mode. This allows an -external trigger to initiate register transfers from the buffer register to the DAC -output register, followed by a DMA transfer to the buffer register if DMA is enabled. -The trigger source must also be selected. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_trigger_enable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR |= DAC_CR_TEN1; - break; - case CHANNEL_2: - DAC_CR |= DAC_CR_TEN2; - break; - case CHANNEL_D: - DAC_CR |= (DAC_CR_TEN1 | DAC_CR_TEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief DAC Channel Trigger Disable. - -Disable a digital to analog converter channel external trigger. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_trigger_disable(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_TEN1; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_TEN2; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_TEN1 | DAC_CR_TEN2); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set DAC Channel Trigger Source. - -Sets the digital to analog converter trigger source, which can be taken from various -timers, an external trigger or a software trigger. - -@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or -a logical OR of one of each of these to set both channels simultaneously. -*/ - -void dac_set_trigger_source(u32 dac_trig_src) -{ - DAC_CR |= dac_trig_src; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Enable and Set DAC Channel Waveform Generation. - -Enable the digital to analog converter waveform generation as either pseudo-random -noise or triangular wave. These signals are superimposed on existing output values -in the DAC output registers. - -@note The DAC trigger must be enabled for this to work. - -@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or -a logical OR of one of each of these to set both channels simultaneously. -*/ - -void dac_set_waveform_generation(u32 dac_wave_ens) -{ - DAC_CR |= dac_wave_ens; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Disable DAC Channel Waveform Generation. - -Disable a digital to analog converter channel superimposed waveform generation. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_disable_waveform_generation(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_CR &= ~DAC_CR_WAVE1_DIS; - break; - case CHANNEL_2: - DAC_CR &= ~DAC_CR_WAVE2_DIS; - break; - case CHANNEL_D: - DAC_CR &= ~(DAC_CR_WAVE1_DIS | DAC_CR_WAVE2_DIS); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude. - -Sets the digital to analog converter superimposed waveform generation characteristics. -@li If the noise generation mode is set, this sets the length of the PRBS sequence and -hence the amplitude of the output noise signal. Default setting is length 1. -@li If the triangle wave generation mode is set, this sets the amplitude of the -output signal as 2^(n)-1 where n is the parameter value. Default setting is 1. - -@note High amplitude levels of these waveforms can overload the DAC and distort the -signal output. -@note This must be called before enabling the DAC as the settings will then become read-only. -@note The DAC trigger must be enabled for this to work. - -@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR -of one of each of these to set both channels simultaneously. -*/ - -void dac_set_waveform_characteristics(u32 dac_mamp) -{ - DAC_CR |= dac_mamp; -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Load DAC Data Register. - -Loads the appropriate digital to analog converter data register with 12 or 8 bit -data to be converted on a channel. The data can be aligned as follows: -@li right-aligned 8 bit data in bits 0-7 -@li right-aligned 12 bit data in bits 0-11 -@li left aligned 12 bit data in bits 4-15 - -This function can also be used to load the dual channel registers if the data is -formatted according to the datasheets: -@li right-aligned 8 bit data in bits 0-7 for channel 1 and 8-15 for channel 2 -@li right-aligned 12 bit data in bits 0-11 for channel 1 and 16-27 for channel 2 -@li left aligned 12 bit data in bits 4-15 for channel 1 and 20-31 for channel 2 - -@param[in] dac_data u32 with appropriate alignment. -@param[in] dac_data_format enum ::data_align. Alignment and size. -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel) -{ - if (dac_channel == CHANNEL_1) - { - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8R1 = dac_data; - break; - case RIGHT12: - DAC_DHR12R1 = dac_data; - break; - case LEFT12: - DAC_DHR12L1 = dac_data; - break; - } - } - else if (dac_channel == CHANNEL_2) - { - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8R2 = dac_data; - break; - case RIGHT12: - DAC_DHR12R2 = dac_data; - break; - case LEFT12: - DAC_DHR12L2 = dac_data; - break; - } - } - else - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8RD = dac_data; - break; - case RIGHT12: - DAC_DHR12RD = dac_data; - break; - case LEFT12: - DAC_DHR12LD = dac_data; - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Load DAC Dual Data Register. - -Loads the appropriate digital to analog converter dual data register with 12 or -8 bit data to be converted for both channels. This allows high bandwidth -simultaneous or independent analog output. The data in both channels are aligned -identically. - -@param[in] dac_data1 u32 for channel 1 with appropriate alignment. -@param[in] dac_data2 u32 for channel 2 with appropriate alignment. -@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit. -*/ - -void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format) -{ - switch (dac_data_format) { - case RIGHT8: - DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8)); - break; - case RIGHT12: - DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 12)); - break; - case LEFT12: - DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); - break; - } -} - -/*-----------------------------------------------------------------------------*/ -/** @brief Trigger the DAC by a Software Trigger. - -If the trigger source is set to be a software trigger, cause a trigger to occur. -The trigger is cleared by hardware after conversion. - -@param[in] dac_channel enum ::data_channel. -*/ - -void dac_software_trigger(data_channel dac_channel) -{ - switch (dac_channel) { - case CHANNEL_1: - DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG1; - break; - case CHANNEL_2: - DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG2; - break; - case CHANNEL_D: - DAC_SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2); - break; - } -} -/**@}*/ - diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 845ae0c..7da3449 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,9 +31,9 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o adc.o flash.o \ rtc.o i2c.o dma.o exti.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \ + timer.o usb_f107.o desig.o crc.o iwdg.o pwr.o \ usb_fx07_common.o \ - gpio_common_all.o spi_common_all.o + gpio_common_all.o spi_common_all.o dac_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f1/dac.c b/lib/stm32/f1/dac.c new file mode 100644 index 0000000..90dc029 --- /dev/null +++ b/lib/stm32/f1/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 174dbce..190812c 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ ARFLAGS = rcs OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o timer.o \ - gpio_common_all.o gpio_common_f24.o spi_common_all.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/dac.c b/lib/stm32/f2/dac.c new file mode 100644 index 0000000..5d20703 --- /dev/null +++ b/lib/stm32/f2/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32F2xx + +@brief libopencm3 STM32F2xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 0bd9a10..282ed48 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -33,7 +33,7 @@ OBJS = rcc.o gpio.o usart.o flash.o \ i2c.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ - gpio_common_all.o gpio_common_f24.o spi_common_all.o + gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f4/dac.c b/lib/stm32/f4/dac.c new file mode 100644 index 0000000..4776c41 --- /dev/null +++ b/lib/stm32/f4/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32F4xx + +@brief libopencm3 STM32F4xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index b533acf..ee50b6c 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -28,10 +28,9 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ -ffunction-sections -fdata-sections -MD -DSTM32L1 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o desig.o crc.o usart.o exti2.o -OBJS += flash.o gpio_common_all.o gpio_common_f24.o spi_common_all.o -OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o -OBJS += timer.o +OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o +OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o +OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/dac.c b/lib/stm32/l1/dac.c new file mode 100644 index 0000000..534f9f1 --- /dev/null +++ b/lib/stm32/l1/dac.c @@ -0,0 +1,28 @@ +/** @defgroup dac_file DAC + +@ingroup STM32L1xx + +@brief libopencm3 STM32L1xx DAC + +*/ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + -- cgit v1.2.3