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path: root/lib/stm32/l1/Makefile
AgeCommit message (Collapse)Author
2013-03-09This mainly moves the STM32 timers' code to the common area.Ken Sarkies
F2 and F4 have a common section to deal with the options register (TIM2 and TIM5 only) L1 has been made common with timer_common_all as its options register has very different settings to F2/F4. Code is in the L1/timer.c L1/timer.h files Note that F3 and F05 timers should fit into this scheme, with F3 having additional features. Bundled with this is L1/pwr.h to change a documentation setting Also all the Doxyfiles have added "ENABLE_PREPROCESSING = NO" to fix a problem introduced by commit 118.
2013-02-26Added more warning CFLAGS to all makefiles.Piotr Esden-Tempski
2013-01-22[stm32] Support the "new" BCD style RTC peripheralKarl Palsson
Add the register definitions and some of the most basic helper functions for the new style BCD RTC module found on the F2, F4, L1, F3 and F0. This tries to keep as close to HACKING_COMMON_DOC as possible, while maintaining sane names.
2013-01-22[l1] PWR: fix style for common codeKarl Palsson
Code added for L1 to support the PWR Control block didn't properly follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and some headers were missing. This commit has no functional changes, it only addresses the style and structure problems.
2013-01-08CRC moved to common areaKen Sarkies
2013-01-08I2C to common areaKen Sarkies
F2/4 has now I2C3 included
2013-01-08IWDG moved to common areaKen Sarkies
2013-01-08Move usart files to common areaKen Sarkies
Again added to L1 which is similar to F1
2013-01-08Move DAC to common areaKen Sarkies
(Note there are now dummy source files dac.c (and others) that are not compiled but are needed for documentation).
2013-01-08STM32: Moved SPI code into the common area.Ken Sarkies
Updated the documentation so that it appears in all families Also added it to the L1 area, but is untested. An addition to the memorymap allows commonality and a #ifdef added to the spi_common_all code to exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those. An rcc dispatch header was added to remove same code from the spi header.
2012-11-14[l1] Add common timer code support.Karl Palsson
This has only been tested functionally with basic timers, and basic operations. Advanced timer support has been #ifdefed to compile, but this probably needs more testing.
2012-11-14[l1] Add rcc clock setup helper routinesKarl Palsson
Despite the L1 being a low power device, my initial focus is on making it basically compatible with existing devices. To that end, provide clock setup helper routines that configure it for maximum performance, allowing some similar clock speeds to F1 devices to help with testing. This requires adding the power chipset routines to set the voltage range. Clock setup style is similar to the F4 code, which seems nicer than the overflow of different routines used on the F1 code. NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power code, even though it should be compatible
2012-11-14[l1] Add Flash Memory Controller Register defns for L1.Karl Palsson
Also, some of the most basic essential helper functions.
2012-11-13Change to make L1 series fit with common filesKen Sarkies
2012-11-07Eliminate redundant gpio code from f2/f4/l1Karl Palsson
Implemented as per exti2
2012-11-07Enable nvic and exti support for L1Karl Palsson
And include an example that uses it.
2012-11-07Add usart support for L1.Karl Palsson
Only tested with basic tx blocking, ie, the same example code as on F2/F4, but the description of the block is almost identical.
2012-11-07STM32L1 support, rebased onto upstream generalizations branch.Karl Palsson
Working example again.
2012-11-07Add most of the rcc functions.Karl Palsson
(Add the forgotten gpio.c file from before)
2012-11-07More progress towards L1 support.Karl Palsson
Believe gpio is complete, but untested without finishing at least the RCC defines. RCC defines are a work in progress
2012-11-07Vectors and Memory Map for STM32L1 seriesKarl Palsson