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-rw-r--r--lib/cm3/assert.c34
-rw-r--r--lib/lm3s/Makefile4
-rw-r--r--lib/lm3s/libopencm3_lm3s.ld36
-rw-r--r--lib/lm3s/vector.c5
-rw-r--r--lib/lpc13xx/Makefile4
-rw-r--r--lib/lpc13xx/libopencm3_lpc13xx.ld36
-rw-r--r--lib/lpc17xx/Makefile4
-rw-r--r--lib/lpc17xx/libopencm3_lpc17xx.ld34
-rw-r--r--lib/lpc17xx/vector.c7
-rw-r--r--lib/lpc43xx/Makefile5
-rw-r--r--lib/lpc43xx/libopencm3_lpc43xx.ld32
-rw-r--r--lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld32
-rw-r--r--lib/lpc43xx/vector.c7
-rw-r--r--lib/stm32/dac.c4
-rw-r--r--lib/stm32/f1/Makefile4
-rw-r--r--lib/stm32/f1/adc.c735
-rw-r--r--lib/stm32/f1/libopencm3_stm32f1.ld19
-rw-r--r--lib/stm32/f1/rcc.c4
-rw-r--r--lib/stm32/f1/vector.c6
-rw-r--r--lib/stm32/f2/Makefile4
-rw-r--r--lib/stm32/f2/libopencm3_stm32f2.ld19
-rw-r--r--lib/stm32/f2/rcc.c4
-rw-r--r--lib/stm32/f2/vector.c4
-rw-r--r--lib/stm32/f4/Makefile6
-rw-r--r--lib/stm32/f4/libopencm3_stm32f4.ld30
-rw-r--r--lib/stm32/f4/rcc.c4
-rw-r--r--lib/stm32/f4/vector.c9
-rw-r--r--lib/stm32/iwdg.c4
-rw-r--r--lib/stm32/nvic.c4
-rw-r--r--lib/stm32/systick.c4
30 files changed, 925 insertions, 179 deletions
diff --git a/lib/cm3/assert.c b/lib/cm3/assert.c
new file mode 100644
index 0000000..d76c578
--- /dev/null
+++ b/lib/cm3/assert.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Tomaz Solc <tomaz.solc@tablix.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/cm3/assert.h>
+
+void __attribute__((weak)) cm3_assert_failed(void)
+{
+ while(1);
+}
+
+void __attribute__((weak)) cm3_assert_failed_verbose(
+ const char *file __attribute__((unused)),
+ int line __attribute__((unused)),
+ const char *func __attribute__((unused)),
+ const char *assert_expr __attribute__((unused)))
+{
+ cm3_assert_failed();
+}
diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile
index bdad3a4..e471a00 100644
--- a/lib/lm3s/Makefile
+++ b/lib/lm3s/Makefile
@@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
-ffunction-sections -fdata-sections -MD
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = gpio.o vector.o
+OBJS = gpio.o vector.o assert.o
-# VPATH += ../usb
+VPATH += ../cm3
include ../Makefile.include
diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld
index c1453fe..ceb391a 100644
--- a/lib/lm3s/libopencm3_lm3s.ld
+++ b/lib/lm3s/libopencm3_lm3s.ld
@@ -24,31 +24,50 @@
/* Enforce emmition of the vector table. */
EXTERN (vector_table)
+/* Define the entry point of the output file. */
+ENTRY(reset_handler)
+
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
*(.vectors) /* Vector table */
*(.text*) /* Program code */
+ . = ALIGN(4);
*(.rodata*) /* Read-only data */
- _etext = .;
+ . = ALIGN(4);
} >rom
- . = ORIGIN(ram);
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >rom
+
+ . = ALIGN(4);
+ _etext = .;
.data : {
_data = .;
*(.data*) /* Read-write initialized data */
+ . = ALIGN(4);
_edata = .;
} >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
+ . = ALIGN(4);
_ebss = .;
- } >ram AT >rom
+ } >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
@@ -56,12 +75,7 @@ SECTIONS
*/
/DISCARD/ : { *(.eh_frame) }
- /*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support - discard it for now.
- */
- /DISCARD/ : { *(.ARM.exidx) }
-
+ . = ALIGN(4);
end = .;
}
diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c
index 5968d76..3a1c4d1 100644
--- a/lib/lm3s/vector.c
+++ b/lib/lm3s/vector.c
@@ -20,7 +20,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s): */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -61,9 +61,10 @@ void (*const vector_table[]) (void) = {
void reset_handler(void)
{
volatile unsigned *src, *dest;
+
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile
index 158a5bf..e1e69f7 100644
--- a/lib/lpc13xx/Makefile
+++ b/lib/lpc13xx/Makefile
@@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
-ffunction-sections -fdata-sections -MD
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = gpio.o
+OBJS = gpio.o assert.o
-# VPATH += ../usb
+VPATH += ../cm3
include ../Makefile.include
diff --git a/lib/lpc13xx/libopencm3_lpc13xx.ld b/lib/lpc13xx/libopencm3_lpc13xx.ld
index 5f1630f..4e0f1df 100644
--- a/lib/lpc13xx/libopencm3_lpc13xx.ld
+++ b/lib/lpc13xx/libopencm3_lpc13xx.ld
@@ -24,31 +24,50 @@
/* Enforce emmition of the vector table. */
EXTERN (vector_table)
+/* Define the entry point of the output file. */
+ENTRY(reset_handler)
+
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
*(.vectors) /* Vector table */
*(.text*) /* Program code */
+ . = ALIGN(4);
*(.rodata*) /* Read-only data */
- _etext = .;
+ . = ALIGN(4);
} >rom
- . = ORIGIN(ram);
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >rom
+
+ . = ALIGN(4);
+ _etext = .;
.data : {
_data = .;
*(.data*) /* Read-write initialized data */
+ . = ALIGN(4);
_edata = .;
} >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
+ . = ALIGN(4);
_ebss = .;
- } >ram AT >rom
+ } >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
@@ -56,12 +75,7 @@ SECTIONS
*/
/DISCARD/ : { *(.eh_frame) }
- /*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support - discard it for now.
- */
- /DISCARD/ : { *(.ARM.exidx) }
-
+ . = ALIGN(4);
end = .;
}
diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile
index f688716..d1da64a 100644
--- a/lib/lpc17xx/Makefile
+++ b/lib/lpc17xx/Makefile
@@ -28,8 +28,8 @@ CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \
-ffunction-sections -fdata-sections -MD
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = gpio.o vector.o
+OBJS = gpio.o vector.o assert.o
-# VPATH += ../usb
+VPATH += ../cm3
include ../Makefile.include
diff --git a/lib/lpc17xx/libopencm3_lpc17xx.ld b/lib/lpc17xx/libopencm3_lpc17xx.ld
index 30a2c0f..4e0f1df 100644
--- a/lib/lpc17xx/libopencm3_lpc17xx.ld
+++ b/lib/lpc17xx/libopencm3_lpc17xx.ld
@@ -1,4 +1,3 @@
-
/*
* This file is part of the libopencm3 project.
*
@@ -31,28 +30,44 @@ ENTRY(reset_handler)
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
*(.vectors) /* Vector table */
*(.text*) /* Program code */
+ . = ALIGN(4);
*(.rodata*) /* Read-only data */
- _etext = .;
+ . = ALIGN(4);
} >rom
- . = ORIGIN(ram);
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >rom
+
+ . = ALIGN(4);
+ _etext = .;
.data : {
_data = .;
*(.data*) /* Read-write initialized data */
+ . = ALIGN(4);
_edata = .;
} >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
+ . = ALIGN(4);
_ebss = .;
- } >ram AT >rom
+ } >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
@@ -60,12 +75,7 @@ SECTIONS
*/
/DISCARD/ : { *(.eh_frame) }
- /*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support - discard it for now.
- */
- /DISCARD/ : { *(.ARM.exidx) }
-
+ . = ALIGN(4);
end = .;
}
diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c
index 016db7a..518f562 100644
--- a/lib/lpc17xx/vector.c
+++ b/lib/lpc17xx/vector.c
@@ -19,8 +19,8 @@
#define WEAK __attribute__ ((weak))
-/* Symbols exported by the linker script(s). */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+/* Symbols exported by the linker script(s): */
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -60,9 +60,10 @@ void (*const vector_table[]) (void) = {
void reset_handler(void)
{
volatile unsigned *src, *dest;
+
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile
index 67e74d7..6e08ea0 100644
--- a/lib/lpc43xx/Makefile
+++ b/lib/lpc43xx/Makefile
@@ -31,8 +31,9 @@ CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \
-mfloat-abi=hard -mfpu=fpv4-sp-d16
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o
+OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o \
+ assert.o
-# VPATH += ../usb
+VPATH += ../cm3
include ../Makefile.include
diff --git a/lib/lpc43xx/libopencm3_lpc43xx.ld b/lib/lpc43xx/libopencm3_lpc43xx.ld
index 47b403b..9402a54 100644
--- a/lib/lpc43xx/libopencm3_lpc43xx.ld
+++ b/lib/lpc43xx/libopencm3_lpc43xx.ld
@@ -32,8 +32,6 @@ ENTRY(reset_handler)
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
. = ALIGN(0x400);
_text_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */
@@ -44,25 +42,31 @@ SECTIONS
. = ALIGN(4);
} >rom
- /* exception index - required due to libgcc.a issuing /0 exceptions */
- __exidx_start = .;
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
.ARM.exidx : {
+ __exidx_start = .;
*(.ARM.exidx*)
- } > rom
- __exidx_end = .;
+ __exidx_end = .;
+ } >rom
+ . = ALIGN(4);
_etext = .;
_etext_ram = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */
_etext_rom = 0; /* Start of Code in RAM NULL because Copy of Code from ROM to RAM disabled */
- . = ORIGIN(ram);
-
.data : {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
} >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
@@ -71,23 +75,13 @@ SECTIONS
_ebss = .;
} >ram
- /* exception unwind data - required due to libgcc.a issuing /0 exceptions */
- .ARM.extab : {
- *(.ARM.extab*)
- } >ram
-
/*
* The .eh_frame section appears to be used for C++ exception handling.
* You may need to fix this if you're using C++.
*/
/DISCARD/ : { *(.eh_frame) }
- /*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support - discard it for now.
- */
- /DISCARD/ : { *(.ARM.exidx) }
-
+ . = ALIGN(4);
end = .;
/* Leave room above stack for IAP to run. */
diff --git a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld
index 0270ea8..06f7708 100644
--- a/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld
+++ b/lib/lpc43xx/libopencm3_lpc43xx_rom_to_ram.ld
@@ -32,8 +32,6 @@ ENTRY(reset_handler)
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
. = ALIGN(0x400);
_text_ram = (. - ORIGIN(rom)) + ORIGIN(ram); /* Start of Code in RAM */
@@ -45,13 +43,20 @@ SECTIONS
. = ALIGN(4);
} >rom
- /* exception index - required due to libgcc.a issuing /0 exceptions */
- __exidx_start = .;
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
.ARM.exidx : {
+ __exidx_start = .;
*(.ARM.exidx*)
- } > rom
- __exidx_end = .;
+ __exidx_end = .;
+ } >rom
+ . = ALIGN(4);
_etext = .;
_etext_ram = (. - ORIGIN(rom)) + ORIGIN(ram);
_etext_rom = (. - ORIGIN(rom)) + ORIGIN(rom_flash);
@@ -62,33 +67,22 @@ SECTIONS
. = ALIGN(4);
_edata = .;
} >ram_data AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
- . = _edata;
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >ram_data
- /* exception unwind data - required due to libgcc.a issuing /0 exceptions */
- .ARM.extab : {
- . = _ebss;
- *(.ARM.extab*)
- } >ram_data
-
/*
* The .eh_frame section appears to be used for C++ exception handling.
* You may need to fix this if you're using C++.
*/
/DISCARD/ : { *(.eh_frame) }
- /*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support - discard it for now.
- */
- /DISCARD/ : { *(.ARM.exidx) }
-
+ . = ALIGN(4);
end = .;
/* Leave room above stack for IAP to run. */
diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c
index daef5a9..23008bc 100644
--- a/lib/lpc43xx/vector.c
+++ b/lib/lpc43xx/vector.c
@@ -20,8 +20,8 @@
#define WEAK __attribute__ ((weak))
-/* Symbols exported by the linker script(s). */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+/* Symbols exported by the linker script(s): */
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
extern unsigned _etext_ram, _text_ram, _etext_rom;
void main(void);
@@ -165,6 +165,7 @@ void (*const vector_table[]) (void) = {
void reset_handler(void)
{
volatile unsigned *src, *dest;
+
__asm__("MSR msp, %0" : : "r"(&_stack));
/* Copy the code from ROM to Real RAM (if enabled) */
@@ -185,7 +186,7 @@ void reset_handler(void)
/* Continue Execution in RAM */
}
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/stm32/dac.c b/lib/stm32/dac.c
index 7978059..55440bf 100644
--- a/lib/stm32/dac.c
+++ b/lib/stm32/dac.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32F-dac-file DAC
+/** @defgroup STM32F_dac_file DAC
-@ingroup STM32F-files
+@ingroup STM32F_files
@brief <b>libopencm3 STM32Fxx Digital to Analog Converter</b>
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 3b4252b..4fdbf43 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -31,9 +31,9 @@ ARFLAGS = rcs
OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
- timer.o usb_f107.o desig.o crc.o
+ timer.o usb_f107.o desig.o crc.o assert.o
-VPATH += ../../usb:../
+VPATH += ../../usb:../:../../cm3
include ../../Makefile.include
diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c
index f07164f..0a05aac 100644
--- a/lib/stm32/f1/adc.c
+++ b/lib/stm32/f1/adc.c
@@ -1,3 +1,74 @@
+/** @defgroup STM32F1xx_adc_file ADC
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx Analog to Digital Converters</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 August 2012
+
+This library supports the A/D Converter Control System in the STM32F1xx series
+of ARM Cortex Microcontrollers by ST Microelectronics.
+
+Devices can have up to three A/D converters each with their own set of registers.
+However all the A/D converters share a common clock which is prescaled from the APB2
+clock by default by a minimum factor of 2 to a maximum of 8.
+
+Each A/D converter has up to 18 channels:
+@li On ADC1 the analog channels 16 and 17 are internally connected to the temperature
+sensor and V<sub>REFINT</sub>, respectively.
+@li On ADC2 the analog channels 16 and 17 are internally connected to V<sub>SS</sub>.
+@li On ADC3 the analog channels 9, 14, 15, 16 and 17 are internally connected to V<sub>SS</sub>.
+
+The conversions can occur as a one-off conversion whereby the process stops once
+conversion is complete. The conversions can also be continuous wherein a new
+conversion starts immediately the previous conversion has ended.
+
+Conversion can occur as a single channel conversion or a scan of a group of
+channels in either continuous or one-off mode. If more than one channel is converted
+in a scan group, DMA must be used to transfer the data as there is only one
+result register available. An interrupt can be set to occur at the end of
+conversion, which occurs after all channels have been scanned.
+
+A discontinuous mode allows a subgroup of group of a channels to be converted in
+bursts of a given length.
+
+Injected conversions allow a second group of channels to be converted separately
+from the regular group. An interrupt can be set to occur at the end of
+conversion, which occurs after all channels have been scanned.
+
+@section adc_api_ex Basic ADC Handling API.
+
+Example 1: Simple single channel conversion polled. Enable the peripheral clock
+and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
+(default). Enable triggering for a software trigger.
+
+@code
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
+ adc_off(ADC1);
+ rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
+ rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
+ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
+ adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
+ adc_disable_scan_mode(ADC1);
+ adc_set_single_conversion_mode(ADC1);
+ adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
+ adc_set_single_channel(ADC1, ADC_CHANNEL0);
+ adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART);
+ adc_power_on(ADC1);
+ adc_reset_calibration(ADC1);
+ adc_calibration(ADC1);
+ adc_start_conversion_regular(ADC1);
+ while (! adc_eoc(ADC1));
+ reg16 = adc_read_regular(ADC1);
+@endcode
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -27,93 +98,365 @@
* rcc_peripheral_clear_reset(&RCC_APB2RSTR, ADC1RST);
*
* rcc_set_adc_clk(ADC_PRE_PLCK2_DIV2);
- * adc_set_mode(ADC1, TODO);
+ * adc_set_dual_mode(ADC1, TODO);
* reg16 = adc_read(ADC1, ADC_CH_0);
*/
+/**@{*/
+
#include <libopencm3/stm32/f1/adc.h>
-void rcc_set_adc_clk(u32 prescaler)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Power On
+
+If the ADC is in power-down mode then it is powered up. The application needs
+to wait a time of about 3 microseconds for stabilization before using the ADC.
+If the ADC is already on this function call has no effect.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_power_on(u32 adc)
+{
+ if (!(ADC_CR2(adc) & ADC_CR2_ADON))
+ ADC_CR2(adc) |= ADC_CR2_ADON;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Start a Conversion Without Trigger
+
+This initiates a conversion by software without a trigger. The ADC needs to be
+powered on before this is called, otherwise this function has no effect.
+
+Note that this is not available in other STM32F families. To ensure code compatibility,
+enable triggering and use a software trigger source @see adc_start_conversion_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_start_conversion_direct(u32 adc)
+{
+ if (ADC_CR2(adc) & ADC_CR2_ADON)
+ ADC_CR2(adc) |= ADC_CR2_ADON;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Dual A/D Mode
+
+The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting
+is applied to ADC1 only. Start of conversion when triggered can cause simultaneous
+conversion with ADC2, or alternate conversion. Regular and injected conversions
+can be configured, each one being separately simultaneous or alternate.
+
+Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock
+cycles later.
+
+Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock
+cycles later, followed by ADC1 fourteen cycles later again. This can only be used
+on a single channel.
+
+Alternate trigger mode must occur on an injected channel group, and alternates
+between the ADCs on each trigger.
+
+Note that sampling must not overlap between ADCs on the same channel.
+
+Dual A/D converter modes possible:
+
+@li IND: Independent mode.
+@li CRSISM: Combined regular simultaneous + injected simultaneous mode.
+@li CRSATM: Combined regular simultaneous + alternate trigger mode.
+@li CISFIM: Combined injected simultaneous + fast interleaved mode.
+@li CISSIM: Combined injected simultaneous + slow interleaved mode.
+@li ISM: Injected simultaneous mode only.
+@li RSM: Regular simultaneous mode only.
+@li FIM: Fast interleaved mode only.
+@li SIM: Slow interleaved mode only.
+@li ATM: Alternate trigger mode only.
+
+@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
+*/
+
+void adc_set_dual_mode(u32 mode)
{
- /* TODO */
+ ADC1_CR1 |= mode;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag
+
+This flag is set after all channels of a regular or injected group have been
+converted.
- /* FIXME: QUICK HACK to prevent compiler warnings. */
- prescaler = prescaler;
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc(u32 adc)
+{
+ return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
}
-void adc_set_mode(u32 block, /* TODO */ u8 mode)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
+
+This flag is set after all channels of an injected group have been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc_injected(u32 adc)
{
- /* TODO */
+ return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read from the Regular Conversion Result Register
+
+The result read back is 12 bits, right or left aligned within the first 16 bits.
+For ADC1 only, the higher 16 bits will hold the result from ADC2 if
+an appropriate dual mode has been set @see adc_set_dual_mode.
- /* FIXME: QUICK HACK to prevent compiler warnings. */
- block = block;
- mode = mode;
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns Unsigned int32 conversion result.
+*/
+
+u32 adc_read_regular(u32 adc)
+{
+ return ADC_DR(adc);
}
-void adc_read(u32 block, u32 channel)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Read from an Injected Conversion Result Register
+
+The result read back from the selected injected result register (one of four) is
+12 bits, right or left aligned within the first 16 bits. The result can have a
+negative value if the injected channel offset has been set @see adc_set_injected_offset.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@returns Unsigned int32 conversion result.
+*/
+
+u32 adc_read_injected(u32 adc, u8 reg)
{
- /* TODO */
+ switch (reg) {
+ case 1:
+ return ADC_JDR1(adc);
+ case 2:
+ return ADC_JDR2(adc);
+ case 3:
+ return ADC_JDR3(adc);
+ case 4:
+ return ADC_JDR4(adc);
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Injected Channel Data Offset
- /* FIXME: QUICK HACK to prevent compiler warnings. */
- block = block;
- channel = channel;
+This value is subtracted from the injected channel results after conversion
+is complete, and can result in negative results. A separate value can be specified
+for each injected data register.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@param[in] offset Unsigned int32.
+*/
+
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
+{
+ switch (reg) {
+ case 1:
+ ADC_JOFR1(adc) = offset;
+ break;
+ case 2:
+ ADC_JOFR2(adc) = offset;
+ break;
+ case 3:
+ ADC_JOFR3(adc) = offset;
+ break;
+ case 4:
+ ADC_JOFR4(adc) = offset;
+ break;
+ }
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for Regular Conversions
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_analog_watchdog_regular(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog for Regular Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_analog_watchdog_regular(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for Injected Conversions
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_analog_watchdog_injected(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog for Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_analog_watchdog_injected(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
-void adc_enable_discontinous_mode_regular(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Discontinuous Mode for Regular Conversions
+
+In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
+defined regular channel group. The subgroup is defined by the number of
+consecutive channels to be converted. After a subgroup has been converted
+the next trigger will start conversion of the immediately following subgroup
+of the same length or until the whole group has all been converted. When the
+the whole group has been converted, the next trigger will restart conversion
+of the subgroup at the beginning of the whole group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
+*/
+
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
{
- ADC_CR1(adc) |= ADC_CR1_DISCEN;
+ if ( (length-1) > 7 ) return;
+ ADC_CR1(adc) |= ADC_CR1_DISCEN;
+ ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
}
-void adc_disable_discontinous_mode_regular(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Discontinuous Mode for Regular Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_discontinuous_mode_regular(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
-void adc_enable_discontinous_mode_injected(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Discontinuous Mode for Injected Conversions
+
+In this mode the ADC converts sequentially one channel of the defined group of
+injected channels, cycling back to the first channel in the group once the
+entire group has been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_discontinuous_mode_injected(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
-void adc_disable_discontinous_mode_injected(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Discontinuous Mode for Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_discontinuous_mode_injected(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Automatic Injected Conversions
+
+The ADC converts a defined injected group of channels immediately after the
+regular channels have been converted. The external trigger on the injected
+channels is disabled as required.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_automatic_injected_group_conversion(u32 adc)
{
+ adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Automatic Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_automatic_injected_group_conversion(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@note The analog watchdog must be enabled for either or both of the regular or
+injected channels. If neither are enabled, the analog watchdog feature will be
+disabled.
+@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
{
- ADC_CR1(adc) |= ADC_CR1_AWDSGL;
+ ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for a Selected Channel
+
+The analog watchdog allows the monitoring of an analog signal between two threshold
+levels. The thresholds must be preset. Comparison is done before data alignment
+takes place, so the thresholds are left-aligned.
+
+@note The analog watchdog must be enabled for either or both of the regular or
+injected channels. If neither are enabled, the analog watchdog feature will be
+disabled. If both are enabled, the same channel number is monitored.
+@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
+*/
+
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
{
u32 reg32;
@@ -122,59 +465,143 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
if (channel < 18)
reg32 |= channel;
ADC_CR1(adc) = reg32;
- ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
+ ADC_CR1(adc) |= ADC_CR1_AWDSGL;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Scan Mode
+
+In this mode a conversion consists of a scan of the predefined set of channels,
+regular and injected, each channel conversion immediately following the
+previous one. It can use single, continuous or discontinuous mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_scan_mode(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Scan Mode
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_scan_mode(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
-void adc_enable_jeoc_interrupt(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Injected End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_eoc_interrupt_injected(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
-void adc_disable_jeoc_interrupt(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Injected End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_eoc_interrupt_injected(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_awd_interrupt(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_awd_interrupt(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Regular End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_eoc_interrupt(u32 adc)
{
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable Regular End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_eoc_interrupt(u32 adc)
{
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable The Temperature Sensor
+
+This enables both the sensor and the reference voltage measurements on channels
+16 and 17.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_temperature_sensor(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_TSVREFE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable The Temperature Sensor
+
+Disabling this will reduce power consumption from the sensor and the reference
+voltage measurements.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_temperature_sensor(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Software Triggered Conversion on Regular Channels
+
+This starts conversion on a set of defined regular channels if the ADC trigger
+is set to be a software trigger. It is cleared by hardware once conversion
+starts.
+
+Note this is a software trigger and requires triggering to be enabled and the
+trigger source to be set appropriately otherwise conversion will not start.
+This is not the same as the ADC start conversion operation.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_start_conversion_regular(u32 adc)
{
/* Start conversion on regular channels. */
@@ -184,6 +611,20 @@ void adc_start_conversion_regular(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Software Triggered Conversion on Injected Channels
+
+This starts conversion on a set of defined injected channels if the ADC trigger
+is set to be a software trigger. It is cleared by hardware once conversion
+starts.
+
+Note this is a software trigger and requires triggering to be enabled and the
+trigger source to be set appropriately otherwise conversion will not start.
+This is not the same as the ADC start conversion operation.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_start_conversion_injected(u32 adc)
{
/* Start conversion on injected channels. */
@@ -193,93 +634,260 @@ void adc_start_conversion_injected(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable an External Trigger for Regular Channels
+
+This enables an external trigger for set of defined regular channels.
+
+For ADC1 and ADC2
+@li Timer 1 CC1 event
+@li Timer 1 CC2 event
+@li Timer 1 CC3 event
+@li Timer 2 CC2 event
+@li Timer 3 TRGO event
+@li Timer 4 CC4 event
+@li EXTI (TIM8_TRGO is also possible on some devices, see datasheet)
+@li Software Start
+
+For ADC3
+@li Timer 3 CC1 event
+@li Timer 2 CC3 event
+@li Timer 1 CC3 event
+@li Timer 8 CC1 event
+@li Timer 8 TRGO event
+@li Timer 5 CC1 event
+@li Timer 5 CC3 event
+@li Software Start
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_regular_12
+for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3
+*/
+
void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
{
u32 reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
- if (trigger < 8)
- reg32 |= (trigger);
+ reg32 |= (trigger);
ADC_CR2(adc) = reg32;
ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable an External Trigger for Regular Channels
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_external_trigger_regular(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable an External Trigger for Injected Channels
+
+This enables an external trigger for set of defined injected channels.
+
+For ADC1 and ADC2
+@li Timer 1 TRGO event
+@li Timer 1 CC4 event
+@li Timer 2 TRGO event
+@li Timer 2 CC1 event
+@li Timer 3 CC4 event
+@li Timer 4 TRGO event
+@li EXTI (TIM8 CC4 is also possible on some devices, see datasheet)
+@li Software Start
+
+For ADC3
+@li Timer 1 TRGO event
+@li Timer 1 CC4 event
+@li Timer 4 CC3 event
+@li Timer 8 CC2 event
+@li Timer 8 CC4 event
+@li Timer 5 TRGO event
+@li Timer 5 CC4 event
+@li Software Start
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12
+for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3
+*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
{
u32 reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */
- if (trigger < 8)
- reg32 |= (trigger);
+ reg32 |= (trigger);
ADC_CR2(adc) = reg32;
ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable an External Trigger for Injected Channels
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_external_trigger_injected(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Data as Left Aligned
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_set_left_aligned(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Data as Right Aligned
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_set_right_aligned(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable DMA Transfers
+
+Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5.
+ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer
+mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_enable_dma(u32 adc)
{
if ((adc == ADC1) | (adc == ADC3))
ADC_CR2(adc) |= ADC_CR2_DMA;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Disable DMA Transfers
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_disable_dma(u32 adc)
{
if ((adc == ADC1) | (adc == ADC3))
ADC_CR2(adc) &= ~ADC_CR2_DMA;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Initialize Calibration Registers
+
+This resets the calibration registers. It is not clear if this is required to be
+done before every calibration operation.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_reset_calibration(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_RSTCAL;
while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Calibration
+
+The calibration data for the ADC is recomputed. The hardware clears the
+calibration status flag when calibration is complete. This function does not return
+until this happens and the ADC is ready for use.
+
+The ADC must have been powered down for at least 2 ADC clock cycles, then powered on.
+before calibration starts
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_calibration(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_CAL;
while (ADC_CR2(adc) & ADC_CR2_CAL);
}
-void adc_set_continous_conversion_mode(u32 adc)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Continuous Conversion Mode
+
+In this mode the ADC starts a new conversion of a single channel or a channel
+group immediately following completion of the previous channel group conversion.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_continuous_conversion_mode(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_CONT;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Enable Single Conversion Mode
+
+In this mode the ADC performs a conversion of one channel or a channel group
+and stops.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_set_single_conversion_mode(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Power On
+
+If the ADC is in power-down mode then it is powered up. The application needs
+to wait a time of about 3 microseconds for stabilization before using the ADC.
+If the ADC is already on this function call will initiate a conversion.
+
+@deprecated to be removed in a later release
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_on(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_ADON;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Off
+
+Turn off the ADC to reduce power consumption to a few microamps.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
void adc_off(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
-void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for a Single Channel
+
+The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+*/
+
+void adc_set_sample_time(u32 adc, u8 channel, u8 time)
{
u32 reg32;
@@ -296,7 +904,17 @@ void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
}
}
-void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for All Channels
+
+The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for
+all channels.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+*/
+
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
{
u8 i;
u32 reg32 = 0;
@@ -310,6 +928,13 @@ void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
ADC_SMPR1(adc) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Analog Watchdog Upper Threshold
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] threshold Unsigned int8. Upper threshold value
+*/
+
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
{
u32 reg32 = 0;
@@ -319,6 +944,13 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
ADC_HTR(adc) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set Analog Watchdog Lower Threshold
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] threshold Unsigned int8. Lower threshold value
+*/
+
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
{
u32 reg32 = 0;
@@ -328,6 +960,18 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
ADC_LTR(adc) = reg32;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set a Regular Channel Conversion Sequence
+
+Define a sequence of channels to be converted as a regular group with a length
+from 1 to 16 channels. If this is called during conversion, the current conversion
+is reset and conversion begins again with the newly defined group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group.
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
+*/
+
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
{
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
@@ -352,6 +996,18 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
ADC_SQR3(adc) = reg32_3;
}
+/*-----------------------------------------------------------------------------*/
+/** @brief ADC Set an Injected Channel Conversion Sequence
+
+Defines a sequence of channels to be converted as an injected group with a length
+from 1 to 4 channels. If this is called during conversion, the current conversion
+is reset and conversion begins again with the newly defined group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group.
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
+*/
+
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
{
u32 reg32 = 0;
@@ -362,9 +1018,24 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
return;
for (i = 1; i <= length; i++)
- reg32 |= (channel[i - 1] << ((i - 1) * 5));
+ reg32 |= (channel[4 - i] << ((4 - i) * 5));
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
ADC_JSQR(adc) = reg32;
}
+
+/*-----------------------------------------------------------------------------*/
+
+/* Aliases */
+
+#ifdef __GNUC__
+void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((alias("adc_set_continuous_conversion_mode")));
+void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((alias ("adc_set_sample_time")));
+void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((alias ("adc_set_sample_time_on_all_channels")));
+void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_enable_eoc_interrupt_injected")));
+void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_disable_eoc_interrupt_injected")));
+#endif
+
+/**@}*/
+
diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld
index a64a1f7..9d165f6 100644
--- a/lib/stm32/f1/libopencm3_stm32f1.ld
+++ b/lib/stm32/f1/libopencm3_stm32f1.ld
@@ -30,21 +30,18 @@ ENTRY(reset_handler)
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read-only data */
. = ALIGN(4);
- _etext = .;
} >rom
/*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support
- */
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
.ARM.extab : {
*(.ARM.extab*)
} >rom
@@ -54,21 +51,23 @@ SECTIONS
__exidx_end = .;
} >rom
- . = ORIGIN(ram);
+ . = ALIGN(4);
+ _etext = .;
- .data : AT (__exidx_end) {
+ .data : {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
- } >ram
+ } >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
- } >ram AT >rom
+ } >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c
index 5fd9c62..ab3350b 100644
--- a/lib/stm32/f1/rcc.c
+++ b/lib/stm32/f1/rcc.c
@@ -48,6 +48,7 @@ LGPL License Terms @ref lgpl_license
/**@{*/
+#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
@@ -166,8 +167,7 @@ int rcc_osc_ready_int_flag(osc_t osc)
break;
}
- /* Shouldn't be reached. */
- return -1;
+ cm3_assert_not_reached();
}
/*-----------------------------------------------------------------------------*/
diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c
index 119ce30..f496ae4 100644
--- a/lib/stm32/f1/vector.c
+++ b/lib/stm32/f1/vector.c
@@ -19,8 +19,8 @@
#define WEAK __attribute__ ((weak))
-/* Symbols exported by the linker script(s). */
-extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
+/* Symbols exported by the linker script(s): */
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -197,7 +197,7 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index bd6f275..c127d61 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -29,8 +29,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
# ARFLAGS = rcsv
ARFLAGS = rcs
OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \
- i2c.o systick.o exti.o scb.o timer.o \
+ i2c.o systick.o exti.o scb.o timer.o assert.o
-VPATH += ../../usb:../
+VPATH += ../../usb:../:../../cm3
include ../../Makefile.include
diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld
index a64a1f7..9d165f6 100644
--- a/lib/stm32/f2/libopencm3_stm32f2.ld
+++ b/lib/stm32/f2/libopencm3_stm32f2.ld
@@ -30,21 +30,18 @@ ENTRY(reset_handler)
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read-only data */
. = ALIGN(4);
- _etext = .;
} >rom
/*
- * Another section used by C++ stuff, appears when using newlib with
- * 64bit (long long) printf support
- */
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
.ARM.extab : {
*(.ARM.extab*)
} >rom
@@ -54,21 +51,23 @@ SECTIONS
__exidx_end = .;
} >rom
- . = ORIGIN(ram);
+ . = ALIGN(4);
+ _etext = .;
- .data : AT (__exidx_end) {
+ .data : {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
- } >ram
+ } >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
- } >ram AT >rom
+ } >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c
index 9461a24..cc2c9bb 100644
--- a/lib/stm32/f2/rcc.c
+++ b/lib/stm32/f2/rcc.c
@@ -19,6 +19,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/f2/rcc.h>
#include <libopencm3/stm32/f2/flash.h>
@@ -125,8 +126,7 @@ int rcc_osc_ready_int_flag(osc_t osc)
break;
}
- /* Shouldn't be reached. */
- return -1;
+ cm3_assert_not_reached();
}
void rcc_css_int_clear(void)
diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c
index 64d2426..3429bfb 100644
--- a/lib/stm32/f2/vector.c
+++ b/lib/stm32/f2/vector.c
@@ -21,7 +21,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s): */
-extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -224,7 +224,7 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
+ for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index 5760d29..fd0b279 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -24,14 +24,16 @@ PREFIX ?= arm-none-eabi
CC = $(PREFIX)-gcc
AR = $(PREFIX)-ar
CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
- -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
+ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
+ -Wstrict-prototypes \
-ffunction-sections -fdata-sections -MD -DSTM32F4
# ARFLAGS = rcsv
ARFLAGS = rcs
OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \
i2c.o systick.o exti.o scb.o pwr.o timer.o \
usb.o usb_standard.o usb_control.o usb_f107.o \
+ assert.o
-VPATH += ../../usb:../
+VPATH += ../../usb:../:../../cm3
include ../../Makefile.include
diff --git a/lib/stm32/f4/libopencm3_stm32f4.ld b/lib/stm32/f4/libopencm3_stm32f4.ld
index 0624b96..9d165f6 100644
--- a/lib/stm32/f4/libopencm3_stm32f4.ld
+++ b/lib/stm32/f4/libopencm3_stm32f4.ld
@@ -30,8 +30,6 @@ ENTRY(reset_handler)
/* Define sections. */
SECTIONS
{
- . = ORIGIN(rom);
-
.text : {
*(.vectors) /* Vector table */
*(.text*) /* Program code */
@@ -40,14 +38,20 @@ SECTIONS
. = ALIGN(4);
} >rom
- /* exception index - required due to libgcc.a issuing /0 exceptions */
- __exidx_start = .;
+ /*
+ * Another section used by C++ stuff, appears when using newlib with
+ * 64bit (long long) printf support
+ */
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } >rom
.ARM.exidx : {
- *(.ARM.exidx*)
- } > rom
- __exidx_end = .;
-
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >rom
+ . = ALIGN(4);
_etext = .;
.data : {
@@ -56,6 +60,7 @@ SECTIONS
. = ALIGN(4);
_edata = .;
} >ram AT >rom
+ _data_loadaddr = LOADADDR(.data);
.bss : {
*(.bss*) /* Read-write zero initialized data */
@@ -64,10 +69,11 @@ SECTIONS
_ebss = .;
} >ram
- /* exception unwind data - required due to libgcc.a issuing /0 exceptions */
- .ARM.extab : {
- *(.ARM.extab*)
- } >ram
+ /*
+ * The .eh_frame section appears to be used for C++ exception handling.
+ * You may need to fix this if you're using C++.
+ */
+ /DISCARD/ : { *(.eh_frame) }
. = ALIGN(4);
end = .;
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index 6294ff7..f506d4b 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -19,6 +19,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/f4/rcc.h>
#include <libopencm3/stm32/f4/pwr.h>
#include <libopencm3/stm32/f4/flash.h>
@@ -139,8 +140,7 @@ int rcc_osc_ready_int_flag(osc_t osc)
break;
}
- /* Shouldn't be reached. */
- return -1;
+ cm3_assert_not_reached();
}
void rcc_css_int_clear(void)
diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c
index 1c901da..01b5e64 100644
--- a/lib/stm32/f4/vector.c
+++ b/lib/stm32/f4/vector.c
@@ -18,10 +18,12 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <libopencm3/stm32/f4/scb.h>
+
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s): */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -224,7 +226,10 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
- for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+ /* Enable access to Floating-Point coprocessor. */
+ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
+
+ for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
diff --git a/lib/stm32/iwdg.c b/lib/stm32/iwdg.c
index 84304ad..251bec1 100644
--- a/lib/stm32/iwdg.c
+++ b/lib/stm32/iwdg.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32F-iwdg-file IWDG
+/** @defgroup STM32F_iwdg_file IWDG
-@ingroup STM32F-files
+@ingroup STM32F_files
@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>
diff --git a/lib/stm32/nvic.c b/lib/stm32/nvic.c
index e17e78c..84fa674 100644
--- a/lib/stm32/nvic.c
+++ b/lib/stm32/nvic.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32F-nvic-file NVIC
+/** @defgroup STM32F_nvic_file NVIC
-@ingroup STM32F-files
+@ingroup STM32F_files
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
diff --git a/lib/stm32/systick.c b/lib/stm32/systick.c
index cfac213..36077cc 100644
--- a/lib/stm32/systick.c
+++ b/lib/stm32/systick.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32F-systick-file SysTick
+/** @defgroup STM32F_systick_file SysTick
-@ingroup STM32F-files
+@ingroup STM32F_files
@brief <b>libopencm3 STM32Fxx System Tick Timer</b>