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-rw-r--r--lib/stm32/common/pwr_common_all.c217
-rw-r--r--lib/stm32/common/rtc_common_bcd.c78
-rw-r--r--lib/stm32/f1/Makefile2
-rw-r--r--lib/stm32/f2/Makefile3
-rw-r--r--lib/stm32/f2/rtc.c27
-rw-r--r--lib/stm32/f4/Makefile4
-rw-r--r--lib/stm32/f4/rtc.c27
-rw-r--r--lib/stm32/l1/Makefile3
-rw-r--r--lib/stm32/l1/pwr.c (renamed from lib/stm32/l1/pwr_chipset.c)2
-rw-r--r--lib/stm32/l1/rcc.c75
-rw-r--r--lib/stm32/l1/rtc.c27
11 files changed, 458 insertions, 7 deletions
diff --git a/lib/stm32/common/pwr_common_all.c b/lib/stm32/common/pwr_common_all.c
new file mode 100644
index 0000000..451ed1c
--- /dev/null
+++ b/lib/stm32/common/pwr_common_all.c
@@ -0,0 +1,217 @@
+/** @defgroup STM32F1xx-pwr-file PWR
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx Power Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 August 2012
+
+This library supports the power control system for the
+STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics.
+
+LGPL License Terms @ref lgpl_license
+*/
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/pwr.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable Backup Domain Write Protection.
+
+This allows backup domain registers to be changed. These registers are write
+protected after a reset.
+*/
+
+void pwr_disable_backup_domain_write_protect(void)
+{
+ PWR_CR |= PWR_CR_DBP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Re-enable Backup Domain Write Protection.
+
+This protects backup domain registers from inadvertent change.
+*/
+
+void pwr_enable_backup_domain_write_protect(void)
+{
+ PWR_CR &= ~PWR_CR_DBP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable Power Voltage Detector.
+
+This provides voltage level threshold detection. The result of detection is
+provided in the power voltage detector output flag (see @ref pwr_voltage_high)
+or by setting the EXTI16 interrupt (see datasheet for configuration details).
+
+@param[in] pvd_level u32. Taken from @ref pwr_pls.
+*/
+
+void pwr_enable_power_voltage_detect(u32 pvd_level)
+{
+ PWR_CR &= ~PWR_CR_PLS_MASK;
+ PWR_CR |= (PWR_CR_PVDE | pvd_level);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable Power Voltage Detector.
+
+*/
+
+void pwr_disable_power_voltage_detect(void)
+{
+ PWR_CR &= ~PWR_CR_PVDE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Clear the Standby Flag.
+
+This is set when the processor returns from a standby mode.
+*/
+
+void pwr_clear_standby_flag(void)
+{
+ PWR_CR |= PWR_CR_CSBF;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Clear the Wakeup Flag.
+
+This is set when the processor receives a wakeup signal.
+*/
+
+void pwr_clear_wakeup_flag(void)
+{
+ PWR_CR |= PWR_CR_CWUF;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set Standby Mode in Deep Sleep.
+
+*/
+
+void pwr_set_standby_mode(void)
+{
+ PWR_CR |= PWR_CR_PDDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set Stop Mode in Deep Sleep.
+
+*/
+
+void pwr_set_stop_mode(void)
+{
+ PWR_CR &= ~PWR_CR_PDDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Voltage Regulator On in Stop Mode.
+
+*/
+
+void pwr_voltage_regulator_on_in_stop(void)
+{
+ PWR_CR &= ~PWR_CR_LPDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Voltage Regulator Low Power in Stop Mode.
+
+*/
+
+void pwr_voltage_regulator_low_power_in_stop(void)
+{
+ PWR_CR |= PWR_CR_LPDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable Wakeup Pin.
+
+The wakeup pin is used for waking the processor from standby mode.
+*/
+
+void pwr_enable_wakeup_pin(void)
+{
+ PWR_CSR |= PWR_CSR_EWUP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Release Wakeup Pin.
+
+The wakeup pin is used for general purpose I/O.
+*/
+
+void pwr_disable_wakeup_pin(void)
+{
+ PWR_CSR &= ~PWR_CSR_EWUP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Get Voltage Detector Output.
+
+The voltage detector threshold must be set when the power voltage detector is
+enabled, see @ref pwr_enable_power_voltage_detect.
+
+@returns boolean: TRUE if the power voltage is above the preset voltage
+threshold.
+*/
+
+bool pwr_voltage_high(void)
+{
+ return (PWR_CSR & PWR_CSR_PVDO);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Get Standby Flag.
+
+The standby flag is set when the processor returns from a standby state. It is
+cleared by software (see @ref pwr_clear_standby_flag).
+
+@returns boolean: TRUE if the processor was in standby state.
+*/
+
+bool pwr_get_standby_flag(void)
+{
+ return (PWR_CSR & PWR_CSR_SBF);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Get Wakeup Flag.
+
+The wakeup flag is set when a wakeup event has been received. It is
+cleared by software (see @ref pwr_clear_wakeup_flag).
+
+@returns boolean: TRUE if a wakeup event was received.
+*/
+
+bool pwr_get_wakeup_flag(void)
+{
+ return (PWR_CSR & PWR_CSR_WUF);
+}
+/**@}*/
+
diff --git a/lib/stm32/common/rtc_common_bcd.c b/lib/stm32/common/rtc_common_bcd.c
new file mode 100644
index 0000000..c302ea2
--- /dev/null
+++ b/lib/stm32/common/rtc_common_bcd.c
@@ -0,0 +1,78 @@
+/** @addtogroup rtc_file */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/rtc.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set RTC prescalars.
+
+This sets the RTC synchronous and asynchronous prescalars.
+*/
+
+void rtc_set_prescaler(u32 sync, u32 async) {
+ /*
+ * Even if only one of the two fields needs to be changed,
+ * 2 separate write accesses must be performed to the RTC_PRER register.
+ */
+ RTC_PRER = (sync & RTC_PRER_PREDIV_S_MASK);
+ RTC_PRER |= (async << RTC_PRER_PREDIV_A_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Wait for RTC registers to be synchronised with the APB1 bus
+
+ Time and Date are accessed through shadow registers which must be synchronized
+*/
+
+void rtc_wait_for_synchro(void) {
+ /* Unlock RTC registers */
+ RTC_WPR = 0xca;
+ RTC_WPR = 0x53;
+
+ RTC_ISR &= ~(RTC_ISR_RSF);
+
+ while (!(RTC_ISR & RTC_ISR_RSF)) {
+ ;
+ }
+ /* disable write protection again */
+ RTC_WPR = 0xff;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Unlock write access to the RTC registers
+
+*/
+void rtc_unlock(void) {
+ RTC_WPR = 0xca;
+ RTC_WPR = 0x53;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Lock write access to the RTC registers
+
+*/
+void rtc_lock(void) {
+ RTC_WPR = 0xff;
+}
+
+/**@}*/
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 6bc21f7..ba0d4b8 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
ARFLAGS = rcs
OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
- timer.o usb_f107.o desig.o pwr.o \
+ timer.o usb_f107.o desig.o pwr_common_all.o \
usb_fx07_common.o \
gpio_common_all.o dma_common_f13.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o \
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index 3d3c756..85e6458 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -31,7 +31,8 @@ ARFLAGS = rcs
OBJS = rcc.o gpio.o flash.o exti2.o timer.o \
gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
- crc_common_all.o
+ crc_common_all.o \
+ rtc_common_bcd.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f2/rtc.c b/lib/stm32/f2/rtc.c
new file mode 100644
index 0000000..461d0b1
--- /dev/null
+++ b/lib/stm32/f2/rtc.c
@@ -0,0 +1,27 @@
+/** @defgroup rtc_file RTC
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx RTC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index 2b02281..8ff7c6a 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -32,9 +32,11 @@ ARFLAGS = rcs
OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
usb_f207.o adc.o dma.o \
+ pwr_common_all.o \
gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
- crc_common_all.o
+ crc_common_all.o \
+ rtc_common_bcd.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c
new file mode 100644
index 0000000..1b301fa
--- /dev/null
+++ b/lib/stm32/f4/rtc.c
@@ -0,0 +1,27 @@
+/** @defgroup rtc_file RTC
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx RTC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index 32c8fd3..9b677ab 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -31,7 +31,8 @@ ARFLAGS = rcs
OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o
OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o
OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o
-OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
+OBJS += pwr_common_all.o pwr.o
+OBJS += rtc_common_bcd.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/l1/pwr_chipset.c b/lib/stm32/l1/pwr.c
index 9f4f599..8541851 100644
--- a/lib/stm32/l1/pwr_chipset.c
+++ b/lib/stm32/l1/pwr.c
@@ -17,7 +17,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <libopencm3/stm32/l1/pwr.h>
+#include <libopencm3/stm32/pwr.h>
void pwr_set_vos_scale(vos_scale_t scale)
{
diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c
index bbba9a9..9b2df24 100644
--- a/lib/stm32/l1/rcc.c
+++ b/lib/stm32/l1/rcc.c
@@ -23,13 +23,13 @@
#include <libopencm3/stm32/l1/rcc.h>
#include <libopencm3/stm32/l1/flash.h>
-#include <libopencm3/stm32/l1/pwr.h>
+#include <libopencm3/stm32/pwr.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 2097000;
u32 rcc_ppre2_frequency = 2097000;
-const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
+const clock_scale_t clock_config[CLOCK_CONFIG_END] =
{
{ /* 24MHz PLL from HSI */
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
@@ -64,6 +64,35 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.apb1_frequency = 16000000,
.apb2_frequency = 16000000,
},
+ { /* 4MHz HSI raw */
+ .hpre = RCC_CFGR_HPRE_SYSCLK_DIV4,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE1,
+ .flash_config = FLASH_LATENCY_0WS,
+ .apb1_frequency = 4000000,
+ .apb2_frequency = 4000000,
+ },
+ { /* 4MHz MSI raw */
+ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE1,
+ .flash_config = FLASH_LATENCY_0WS,
+ .apb1_frequency = 4194000,
+ .apb2_frequency = 4194000,
+ .msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
+ },
+ { /* 2MHz MSI raw */
+ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE1,
+ .flash_config = FLASH_LATENCY_0WS,
+ .apb1_frequency = 2097000,
+ .apb2_frequency = 2097000,
+ .msi_range = RCC_ICSCR_MSIRANGE_2MHZ,
+ },
};
void rcc_osc_ready_int_clear(osc_t osc)
@@ -408,6 +437,48 @@ u32 rcc_system_clock_source(void)
return ((RCC_CFGR & 0x000c) >> 2);
}
+void rcc_rtc_select_clock(u32 clock)
+{
+ RCC_CSR &= ~(RCC_CSR_RTCSEL_MASK << RCC_CSR_RTCSEL_SHIFT);
+ RCC_CSR |= (clock << RCC_CSR_RTCSEL_SHIFT);
+}
+
+void rcc_clock_setup_msi(const clock_scale_t *clock)
+{
+ /* Enable internal multi-speed oscillator. */
+
+ u32 reg = RCC_ICSCR;
+ reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
+ reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
+ RCC_ICSCR = reg;
+
+ rcc_osc_on(MSI);
+ rcc_wait_for_osc_ready(MSI);
+
+ /* Select MSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_MSICLK);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(clock->hpre);
+ rcc_set_ppre1(clock->ppre1);
+ rcc_set_ppre2(clock->ppre2);
+
+ pwr_set_vos_scale(clock->voltage_scale);
+
+ // I guess this should be in the settings?
+ flash_64bit_enable();
+ flash_prefetch_enable();
+ /* Configure flash settings. */
+ flash_set_ws(clock->flash_config);
+
+ /* Set the peripheral clock frequencies used. */
+ rcc_ppre1_frequency = clock->apb1_frequency;
+ rcc_ppre2_frequency = clock->apb2_frequency;
+}
+
void rcc_clock_setup_hsi(const clock_scale_t *clock)
{
/* Enable internal high-speed oscillator. */
diff --git a/lib/stm32/l1/rtc.c b/lib/stm32/l1/rtc.c
new file mode 100644
index 0000000..bc7f87f
--- /dev/null
+++ b/lib/stm32/l1/rtc.c
@@ -0,0 +1,27 @@
+/** @defgroup rtc_file RTC
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx RTC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>