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-rw-r--r--include/libopencm3/cm3/assert.h136
-rw-r--r--include/libopencm3/cm3/common.h10
-rw-r--r--include/libopencm3/cm3/doc-cm3.h22
-rw-r--r--include/libopencm3/cm3/docmain.h70
-rw-r--r--include/libopencm3/docmain.dox21
-rw-r--r--include/libopencm3/license.dox16
-rw-r--r--include/libopencm3/lm3s/doc-lm3s.h32
-rw-r--r--include/libopencm3/lm3s/gpio.h4
-rw-r--r--include/libopencm3/lpc13xx/doc-lpc13xx.h32
-rw-r--r--include/libopencm3/lpc17xx/doc-lpc17xx.h32
-rw-r--r--include/libopencm3/lpc17xx/gpio.h4
-rw-r--r--include/libopencm3/lpc43xx/doc-lpc43xx.h32
-rw-r--r--include/libopencm3/lpc43xx/gpio.h4
-rw-r--r--include/libopencm3/lpc43xx/i2c.h6
-rw-r--r--include/libopencm3/lpc43xx/nvic.h4
-rw-r--r--include/libopencm3/lpc43xx/scu.h4
-rw-r--r--include/libopencm3/lpc43xx/ssp.h4
-rw-r--r--include/libopencm3/lpc43xx/systick.h4
-rw-r--r--include/libopencm3/stm32/can.h4
-rw-r--r--include/libopencm3/stm32/crc.h4
-rw-r--r--include/libopencm3/stm32/dac.h4
-rw-r--r--include/libopencm3/stm32/doc-stm32f.h23
-rw-r--r--include/libopencm3/stm32/exti.h4
-rw-r--r--include/libopencm3/stm32/f1/adc.h297
-rw-r--r--include/libopencm3/stm32/f1/desig.h4
-rw-r--r--include/libopencm3/stm32/f1/dma.h4
-rw-r--r--include/libopencm3/stm32/f1/doc-stm32f1.h29
-rw-r--r--include/libopencm3/stm32/f1/flash.h4
-rw-r--r--include/libopencm3/stm32/f1/gpio.h4
-rw-r--r--include/libopencm3/stm32/f1/nvic_f1.h8
-rw-r--r--include/libopencm3/stm32/f1/rcc.h4
-rw-r--r--include/libopencm3/stm32/f1/rtc.h4
-rw-r--r--include/libopencm3/stm32/f1/scb.h5
-rw-r--r--include/libopencm3/stm32/f2/doc-stm32f2.h33
-rw-r--r--include/libopencm3/stm32/f2/flash.h4
-rw-r--r--include/libopencm3/stm32/f2/gpio.h4
-rw-r--r--include/libopencm3/stm32/f2/rcc.h4
-rw-r--r--include/libopencm3/stm32/f2/scb.h5
-rw-r--r--include/libopencm3/stm32/f2/timer.h4
-rw-r--r--include/libopencm3/stm32/f4/doc-stm32f4.h32
-rw-r--r--include/libopencm3/stm32/f4/flash.h4
-rw-r--r--include/libopencm3/stm32/f4/gpio.h4
-rw-r--r--include/libopencm3/stm32/f4/pwr.h4
-rw-r--r--include/libopencm3/stm32/f4/rcc.h4
-rw-r--r--include/libopencm3/stm32/f4/scb.h74
-rw-r--r--include/libopencm3/stm32/f4/timer.h4
-rw-r--r--include/libopencm3/stm32/i2c.h4
-rw-r--r--include/libopencm3/stm32/iwdg.h4
-rw-r--r--include/libopencm3/stm32/nvic.h8
-rw-r--r--include/libopencm3/stm32/pwr.h4
-rw-r--r--include/libopencm3/stm32/sdio.h2
-rw-r--r--include/libopencm3/stm32/spi.h4
-rw-r--r--include/libopencm3/stm32/systick.h4
-rw-r--r--include/libopencm3/stm32/timer.h5
-rw-r--r--include/libopencm3/stm32/usart.h4
-rw-r--r--include/libopencm3/usb/usbd.h4
56 files changed, 918 insertions, 144 deletions
diff --git a/include/libopencm3/cm3/assert.h b/include/libopencm3/cm3/assert.h
new file mode 100644
index 0000000..0ccb0f7
--- /dev/null
+++ b/include/libopencm3/cm3/assert.h
@@ -0,0 +1,136 @@
+/** @defgroup debugging Debugging
+
+@brief Macros and functions to aid in debugging
+
+@version 1.0.0
+
+@date 25 September 2012
+
+Two preprocessor defines control the behavior of assertion check macros in
+this module. They allow the choice between generated code size and ease of
+debugging.
+
+If NDEBUG is defined, all assertion checks are disabled and macros do not
+generate any code.
+
+If CM3_ASSERT_VERBOSE is defined, information regarding the position of
+assertion checks will be stored in the binary, allowing for more
+informative error messages, but also significantly increased code size. As
+default assertion checks do not use this information it is only useful if
+the application linked with libopencm3 defines its own
+cm3_assert_failed_verbose() implementation.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Tomaz Solc <tomaz.solc@tablix.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_CM3_ASSERT_H
+#define LIBOPENCM3_CM3_ASSERT_H
+
+#include <libopencm3/cm3/common.h>
+
+#define CM3_LIKELY(expr) (__builtin_expect (!!(expr), 1))
+
+#ifdef NDEBUG
+# define cm3_assert(expr) do { (void)0; } while(0)
+# define cm3_assert_not_reached() while(1)
+#else
+# ifdef CM3_ASSERT_VERBOSE
+# define cm3_assert(expr) do { \
+ if(CM3_LIKELY(expr)) { (void)0; } else { \
+ cm3_assert_failed_verbose( \
+ __FILE__, __LINE__, \
+ __func__, #expr); \
+ } \
+ } while(0)
+# define cm3_assert_not_reached() do { \
+ cm3_assert_failed_verbose( \
+ __FILE__, __LINE__, \
+ __func__, 0); \
+ } while(0)
+# else
+/** @brief Check if assertion is true.
+ *
+ * If NDEBUG macro is defined, this macro generates no code. Otherwise
+ * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion
+ * is false.
+ *
+ * The purpose of this macro is to aid in debugging libopencm3 and
+ * applications using it. It can be used for example to check if function
+ * arguments are within expected ranges and stop execution in case an
+ * unexpected state is reached.
+ *
+ * @param expr expression to check */
+# define cm3_assert(expr) do { \
+ if(CM3_LIKELY(expr)) { (void)0; } else { \
+ cm3_assert_failed(); \
+ } \
+ } while(0)
+/** @brief Check if unreachable code is reached.
+ *
+ * If NDEBUG macro is defined, this macro generates code for an infinite loop.
+ * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if
+ * the macro is ever reached.
+ *
+ * The purpose of this macro is to aid in debugging libopencm3 and
+ * applications using it. It can be used for example to stop execution if an
+ * unreachable portion of code is reached. */
+# define cm3_assert_not_reached() do { \
+ cm3_assert_failed(); \
+ } while(0)
+# endif
+#endif
+
+BEGIN_DECLS
+
+/** @brief Called on a failed assertion.
+ *
+ * Halts execution in an infinite loop. This function never returns.
+ *
+ * Defined as a weak symbol, so applications can define their own
+ * implementation. Usually, a custom implementation of this function should
+ * report an error in some way (print a message to a debug console, display,
+ * LED, ...) and halt execution or reboot the device. */
+void cm3_assert_failed(void) __attribute__ ((__noreturn__));
+
+/** @brief Called on a failed assertion with verbose messages enabled.
+ *
+ * Halts execution in an infinite loop. This function never returns.
+ *
+ * Defined as a weak symbol, so applications can define their own
+ * implementation. Usually, a custom implementation of this function should
+ * report an error in some way (print a message to a debug console, display,
+ * LED, ...) and halt execution or reboot the device.
+ *
+ * @param file File name where the failed assertion occurred
+ * @param line Line number where the failed assertion occurred
+ * @param func Name of the function where the failed assertion occurred
+ * @param assert_expr Expression that evaluated to false (can be NULL) */
+void cm3_assert_failed_verbose(const char *file, int line, const char *func,
+ const char *assert_expr) __attribute__ ((__noreturn__));
+
+END_DECLS
+
+#endif
+
+/**@}*/
diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h
index 54cd2e4..7ef18fe 100644
--- a/include/libopencm3/cm3/common.h
+++ b/include/libopencm3/cm3/common.h
@@ -32,6 +32,16 @@ typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
+/* This must be placed around external function declaration for C++
+ * support. */
+#ifdef __cplusplus
+# define BEGIN_DECLS extern "C" {
+# define END_DECLS }
+#else
+# define BEGIN_DECLS
+# define END_DECLS
+#endif
+
/* Generic memory-mapped I/O accessor functions */
#define MMIO8(addr) (*(volatile u8 *)(addr))
#define MMIO16(addr) (*(volatile u16 *)(addr))
diff --git a/include/libopencm3/cm3/doc-cm3.h b/include/libopencm3/cm3/doc-cm3.h
new file mode 100644
index 0000000..0f76370
--- /dev/null
+++ b/include/libopencm3/cm3/doc-cm3.h
@@ -0,0 +1,22 @@
+/** @mainpage libopencm3 Core CM3
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for Cortex M3 core features.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup CM3_defines CM3 Defines
+
+@brief Defined Constants and Types for Cortex M3 core features
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/cm3/docmain.h b/include/libopencm3/cm3/docmain.h
deleted file mode 100644
index 9407ceb..0000000
--- a/include/libopencm3/cm3/docmain.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**
- * @mainpage libopencm3 Developer Documentation
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
-
-@date 18 August 2012
-
- * The libopencm3 project (previously known as libopenstm32) aims to create
- * a free/libre/open-source (GPL v3, or later) firmware library for various
- * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
- * Atmel SAM3U, NXP LPC1000 and others.
- *
- * @par ""
- *
- * See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
- * more information.
-
-LGPL License Terms @ref lgpl_license
-
-*/
-
-/** @page lgpl_license libopencm3 License
-
-libopencm3 is free software: you can redistribute it and/or modify
-it under the terms of the GNU Lesser General Public License as published by the Free
-Software Foundation, either version 3 of the License, or (at your option) any
-later version.
-
-libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public License along with this
-program. If not, see <http://www.gnu.org/licenses/>.
-
-*/
-
-/** @defgroup LM3S LM3S
-Libraries for Texas instruments LM3S series.
-*/
-
-/** @defgroup LPC13xx LPC13xx
-Libraries for NXP Semiconductor LPC13xx series.
-*/
-
-/** @defgroup LPC17xx LPC17xx
-Libraries for NXP Semiconductor LPC17xx series.
-*/
-
-/** @defgroup STM32F STM32F
-Libraries for ST Microelectronics STM32F series.
-*/
-
-/** @defgroup STM32F1xx STM32F1xx
-@ingroup STM32F
-Libraries for ST Microelectronics STM32F1xx series.
-*/
-
-/** @defgroup STM32F2xx STM32F2xx
-@ingroup STM32F
-Libraries for ST Microelectronics STM32F2xx series.
-*/
-
-/** @defgroup STM32F4xx STM32F4xx
-@ingroup STM32F
-Libraries for ST Microelectronics STM32F4xx series.
-*/
-
diff --git a/include/libopencm3/docmain.dox b/include/libopencm3/docmain.dox
new file mode 100644
index 0000000..f85aeb8
--- /dev/null
+++ b/include/libopencm3/docmain.dox
@@ -0,0 +1,21 @@
+/** @mainpage libopencm3 Developer Documentation
+
+@version 1.0.0
+
+@date 7 September 2012
+
+ * The libopencm3 project (previously known as libopenstm32) aims to create
+ * a free/libre/open-source (GPL v3, or later) firmware library for various
+ * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
+ * Atmel SAM3U, NXP LPC1000 and others.
+ *
+ * @par ""
+ *
+ * See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
+ * more information.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+
+
diff --git a/include/libopencm3/license.dox b/include/libopencm3/license.dox
new file mode 100644
index 0000000..3aa9331
--- /dev/null
+++ b/include/libopencm3/license.dox
@@ -0,0 +1,16 @@
+/** @page lgpl_license libopencm3 License
+
+libopencm3 is free software: you can redistribute it and/or modify
+it under the terms of the GNU Lesser General Public License as published by the Free
+Software Foundation, either version 3 of the License, or (at your option) any
+later version.
+
+libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public License along with this
+program. If not, see <http://www.gnu.org/licenses/>.
+
+*/
+
diff --git a/include/libopencm3/lm3s/doc-lm3s.h b/include/libopencm3/lm3s/doc-lm3s.h
new file mode 100644
index 0000000..2503a7b
--- /dev/null
+++ b/include/libopencm3/lm3s/doc-lm3s.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LM3S
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for TI Stellaris LM3S Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LM3S LM3S
+Libraries for TI Stellaris LM3S series.
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LM3S_defines LM3S Defines
+
+@brief Defined Constants and Types for the LM3S series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/lm3s/gpio.h b/include/libopencm3/lm3s/gpio.h
index 852609f..5296b74 100644
--- a/include/libopencm3/lm3s/gpio.h
+++ b/include/libopencm3/lm3s/gpio.h
@@ -69,7 +69,11 @@
#define GPIO_CR(port) MMIO32(port + 0x524)
#define GPIO_AMSEL(port) MMIO32(port + 0x528)
+BEGIN_DECLS
+
void gpio_set(u32 gpioport, u8 gpios);
void gpio_clear(u32 gpioport, u8 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc13xx/doc-lpc13xx.h b/include/libopencm3/lpc13xx/doc-lpc13xx.h
new file mode 100644
index 0000000..5ed7cae
--- /dev/null
+++ b/include/libopencm3/lpc13xx/doc-lpc13xx.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LPC13xx
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for NXP Semiconductors LPC13xx Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC13xx LPC13xx
+Libraries for NXP Semiconductors LPC13xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC13xx_defines LPC13xx Defines
+
+@brief Defined Constants and Types for the LPC13xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/lpc17xx/doc-lpc17xx.h b/include/libopencm3/lpc17xx/doc-lpc17xx.h
new file mode 100644
index 0000000..5ed7cae
--- /dev/null
+++ b/include/libopencm3/lpc17xx/doc-lpc17xx.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LPC13xx
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for NXP Semiconductors LPC13xx Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC13xx LPC13xx
+Libraries for NXP Semiconductors LPC13xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC13xx_defines LPC13xx Defines
+
+@brief Defined Constants and Types for the LPC13xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/lpc17xx/gpio.h b/include/libopencm3/lpc17xx/gpio.h
index 7b07ac5..15afd87 100644
--- a/include/libopencm3/lpc17xx/gpio.h
+++ b/include/libopencm3/lpc17xx/gpio.h
@@ -132,7 +132,11 @@
/* Overall interrupt status */
#define GPIO_IS MMIO32(GPIOINTERRPUT_BASE + 0x80)
+BEGIN_DECLS
+
void gpio_set(u32 gpioport, u32 gpios);
void gpio_clear(u32 gpioport, u32 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc43xx/doc-lpc43xx.h b/include/libopencm3/lpc43xx/doc-lpc43xx.h
new file mode 100644
index 0000000..3c21aae
--- /dev/null
+++ b/include/libopencm3/lpc43xx/doc-lpc43xx.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LPC43xx
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for NXP Semiconductors LPC43xx Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC43xx LPC43xx
+Libraries for NXP Semiconductors LPC43xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC43xx_defines LPC43xx Defines
+
+@brief Defined Constants and Types for the LPC43xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h
index 8abd546..daa21fd 100644
--- a/include/libopencm3/lpc43xx/gpio.h
+++ b/include/libopencm3/lpc43xx/gpio.h
@@ -153,8 +153,12 @@
//TODO interrupts
+BEGIN_DECLS
+
void gpio_set(u32 gpioport, u32 gpios);
void gpio_clear(u32 gpioport, u32 gpios);
void gpio_toggle(u32 gpioport, u32 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc43xx/i2c.h b/include/libopencm3/lpc43xx/i2c.h
index 249962c..29e797e 100644
--- a/include/libopencm3/lpc43xx/i2c.h
+++ b/include/libopencm3/lpc43xx/i2c.h
@@ -131,7 +131,9 @@
#define I2C_WRITE 0
#define I2C_READ 1
-/* --- I2C funtion prototypes----------------------------------------------- */
+/* --- I2C function prototypes --------------------------------------------- */
+
+BEGIN_DECLS
void i2c0_init(void);
void i2c0_tx_start(void);
@@ -139,4 +141,6 @@ void i2c0_tx_byte(u8 byte);
u8 i2c0_rx_byte(void);
void i2c0_stop(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h
index b996ab8..cdbf070 100644
--- a/include/libopencm3/lpc43xx/nvic.h
+++ b/include/libopencm3/lpc43xx/nvic.h
@@ -134,6 +134,8 @@
/* --- NVIC functions ------------------------------------------------------ */
+BEGIN_DECLS
+
void nvic_enable_irq(u8 irqn);
void nvic_disable_irq(u8 irqn);
u8 nvic_get_pending_irq(u8 irqn);
@@ -144,4 +146,6 @@ u8 nvic_get_irq_enabled(u8 irqn);
void nvic_set_priority(u8 irqn, u8 priority);
void nvic_generate_software_interrupt(u8 irqn);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h
index 6e1be7f..c1b9fc2 100644
--- a/include/libopencm3/lpc43xx/scu.h
+++ b/include/libopencm3/lpc43xx/scu.h
@@ -725,6 +725,10 @@ typedef enum {
#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+BEGIN_DECLS
+
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h
index ed69668..b3d95db 100644
--- a/include/libopencm3/lpc43xx/ssp.h
+++ b/include/libopencm3/lpc43xx/ssp.h
@@ -157,6 +157,8 @@ typedef enum {
SSP_SLAVE_OUT_DISABLE = BIT3
} ssp_slave_option_t; /* This option is relevant only in slave mode */
+BEGIN_DECLS
+
void ssp_disable(ssp_num_t ssp_num);
/*
@@ -178,4 +180,6 @@ u16 ssp_read(ssp_num_t ssp_num);
void ssp_write(ssp_num_t ssp_num, u16 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/lpc43xx/systick.h b/include/libopencm3/lpc43xx/systick.h
index 9f8b38d..2ae52c2 100644
--- a/include/libopencm3/lpc43xx/systick.h
+++ b/include/libopencm3/lpc43xx/systick.h
@@ -70,6 +70,8 @@
/* --- Function Prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void systick_set_reload(u32 value);
u32 systick_get_value(void);
void systick_set_clocksource(u8 clocksource);
@@ -81,4 +83,6 @@ u8 systick_get_countflag(void);
u32 systick_get_calib(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
index 0a05798..d6636d5 100644
--- a/include/libopencm3/stm32/can.h
+++ b/include/libopencm3/stm32/can.h
@@ -615,6 +615,8 @@
/* --- CAN functions -------------------------------------------------------- */
+BEGIN_DECLS
+
void can_reset(u32 canport);
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp);
@@ -639,4 +641,6 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
void can_fifo_release(u32 canport, u8 fifo);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h
index 7d80259..3848191 100644
--- a/include/libopencm3/stm32/crc.h
+++ b/include/libopencm3/stm32/crc.h
@@ -53,6 +53,8 @@
/* --- CRC function prototypes --------------------------------------------- */
+BEGIN_DECLS
+
/* TODO */
/**
@@ -75,4 +77,6 @@ u32 crc_calculate(u32 data);
*/
u32 crc_calculate_block(u32 *datap, int size);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h
index 3a57132..75d4edb 100644
--- a/include/libopencm3/stm32/dac.h
+++ b/include/libopencm3/stm32/dac.h
@@ -393,6 +393,8 @@ typedef enum {
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void dac_enable(data_channel dac_channel);
void dac_disable(data_channel dac_channel);
void dac_buffer_enable(data_channel dac_channel);
@@ -409,6 +411,8 @@ void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_
void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
void dac_software_trigger(data_channel dac_channel);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/doc-stm32f.h b/include/libopencm3/stm32/doc-stm32f.h
index 0f3f850..7b0a1a3 100644
--- a/include/libopencm3/stm32/doc-stm32f.h
+++ b/include/libopencm3/stm32/doc-stm32f.h
@@ -1,24 +1,29 @@
-/** @defgroup STM32F_defines STM32F Top Level Defines
+/** @mainpage libopencm3 STM32 Common
-@brief Defined Constants and Types for the STM32F series
+@version 1.0.0
-@ingroup STM32F
+@date 7 September 2012
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+API documentation for common files for ST Microelectronics STM32 Cortex M3 series.
-@version 1.0.0
+LGPL License Terms @ref lgpl_license
+*/
-@date 18 August 2012
+/** @defgroup STM32F_defines STM32F Common Defines
+
+@brief Defined Constants and Types for the STM32F series
LGPL License Terms @ref lgpl_license
*/
-/** @defgroup STM32F-files STM32F Top Level Files
+/** @defgroup STM32F_files STM32F Common Files
@brief Common Files for ST Microelectronics STM32F series.
-@ingroup STM32F
+@version 1.0.0
-*/
+@date 7 September 2012
+LGPL License Terms @ref lgpl_license
+*/
diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h
index d1935ad..7645825 100644
--- a/include/libopencm3/stm32/exti.h
+++ b/include/libopencm3/stm32/exti.h
@@ -61,10 +61,14 @@ typedef enum trigger_e {
EXTI_TRIGGER_BOTH,
} exti_trigger_type;
+BEGIN_DECLS
+
void exti_set_trigger(u32 extis, exti_trigger_type trig);
void exti_enable_request(u32 extis);
void exti_disable_request(u32 extis);
void exti_reset_request(u32 extis);
void exti_select_source(u32 exti, u32 gpioport);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h
index 563e75d..aa54bdf 100644
--- a/include/libopencm3/stm32/f1/adc.h
+++ b/include/libopencm3/stm32/f1/adc.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_adc_defines ADC Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital Converters</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H
@@ -26,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */
/* ADC port base addresses (for convenience) */
+/****************************************************************************/
+/** @defgroup adc_reg_base ADC register base addresses
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC1 ADC1_BASE
#define ADC2 ADC2_BASE
#define ADC3 ADC3_BASE
+/**@}*/
/* --- ADC registers ------------------------------------------------------- */
@@ -140,6 +162,35 @@
#define ADC2_DR ADC_DR(ADC2)
#define ADC3_DR ADC_DR(ADC3)
+/* --- ADC Channels ------------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup adc_channel ADC Channel Numbers
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+#define ADC_CHANNEL0 0x00
+#define ADC_CHANNEL1 0x01
+#define ADC_CHANNEL2 0x02
+#define ADC_CHANNEL3 0x03
+#define ADC_CHANNEL4 0x04
+#define ADC_CHANNEL5 0x05
+#define ADC_CHANNEL6 0x06
+#define ADC_CHANNEL7 0x07
+#define ADC_CHANNEL8 0x08
+#define ADC_CHANNEL9 0x09
+#define ADC_CHANNEL10 0x0A
+#define ADC_CHANNEL11 0x0B
+#define ADC_CHANNEL12 0x0C
+#define ADC_CHANNEL13 0x0D
+#define ADC_CHANNEL14 0x0E
+#define ADC_CHANNEL15 0x0F
+#define ADC_CHANNEL16 0x10
+#define ADC_CHANNEL17 0x11
+/**@}*/
+#define ADC_MASK 0x1F
+#define ADC_SHIFT 0
+
/* --- ADC_SR values ------------------------------------------------------- */
#define ADC_SR_STRT (1 << 4)
@@ -171,20 +222,42 @@
* SIM: Slow interleaved mode only.
* ATM: Alternate trigger mode only.
*/
+/****************************************************************************/
+/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
+/** @defgroup adc_cr1_dualmod ADC Mode Selection
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Independent (non-dual) mode */
#define ADC_CR1_DUALMOD_IND (0x0 << 16)
+/** Combined regular simultaneous + injected simultaneous mode. */
#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
+/** Combined regular simultaneous + alternate trigger mode. */
#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
+/** Combined injected simultaneous + fast interleaved mode. */
#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
+/** Combined injected simultaneous + slow interleaved mode. */
#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
+/** Injected simultaneous mode only. */
#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
+/** Regular simultaneous mode only. */
#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
+/** Fast interleaved mode only. */
#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
+/** Slow interleaved mode only. */
#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
+/** Alternate trigger mode only. */
#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
+/**@}*/
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
-/* DISCNUM[2:0]: Discontinous mode channel count. */
+/* DISCNUM[2:0]: Discontinuous mode channel count. */
+/****************************************************************************/
+/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
@@ -193,31 +266,32 @@
#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
+/**@}*/
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
-/* JDISCEN: Discontinous mode on injected channels. */
+/* JDISCEN: */ /** Discontinuous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
-/* DISCEN: Discontinous mode on regular channels. */
+/* DISCEN: */ /** Discontinuous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
-/* JAUTO: Automatic Injection Group conversion. */
+/* JAUTO: */ /** Automatic Injection Group conversion. */
#define ADC_CR1_JAUTO (1 << 10)
-/* AWDSGL: Enable the watchdog on a single channel in scan mode. */
+/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
#define ADC_CR1_AWDSGL (1 << 9)
-/* SCAN: Scan mode. */
+/* SCAN: */ /** Scan mode. */
#define ADC_CR1_SCAN (1 << 8)
-/* JEOCIE: Interrupt enable for injected channels. */
+/* JEOCIE: */ /** Interrupt enable for injected channels. */
#define ADC_CR1_JEOCIE (1 << 7)
-/* AWDIE: Analog watchdog interrupt enable. */
+/* AWDIE: */ /** Analog watchdog interrupt enable. */
#define ADC_CR1_AWDIE (1 << 6)
-/* EOCIE: Interrupt enable EOC. */
+/* EOCIE: */ /** Interrupt enable EOC. */
#define ADC_CR1_EOCIE (1 << 5)
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
@@ -227,6 +301,12 @@
* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
*/
+/****************************************************************************/
+/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
+/** @defgroup adc_watchdog_channel ADC watchdog channel
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
@@ -245,41 +325,72 @@
#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
+/**@}*/
#define ADC_CR1_AWDCH_MASK (0x1F << 0)
#define ADC_CR1_AWDCH_SHIFT 0
/* --- ADC_CR2 values ------------------------------------------------------ */
-/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */
+/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */
#define ADC_CR2_TSVREFE (1 << 23)
-/* SWSTART: Start conversion of regular channels. */
+/* SWSTART: */ /** Start conversion of regular channels. */
#define ADC_CR2_SWSTART (1 << 22)
-/* JSWSTART: Start conversion of injected channels. */
+/* JSWSTART: */ /** Start conversion of injected channels. */
#define ADC_CR2_JSWSTART (1 << 21)
-/* EXTTRIG: External trigger conversion mode for regular channels. */
+/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */
#define ADC_CR2_EXTTRIG (1 << 20)
/* EXTSEL[2:0]: External event select for regular group. */
/* The following are only valid for ADC1 and ADC2. */
+/****************************************************************************/
+/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
+/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
+/** Timer 1 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
+/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
+/** Timer 2 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
+/** Timer 3 Trigger Output */
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
+/** Timer 4 Compare Output 4 */
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
+/** External Interrupt 11 */
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
+/** Software Trigger */
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
+/**@}*/
/* The following are only valid for ADC3 */
+/****************************************************************************/
+/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
+/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 2 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
+/** Timer 2 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
+/** Timer 1 Compare Output 3 */
+#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
+/** Timer 8 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
+/** Timer 8 Trigger Output */
#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
+/** Timer 5 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
+/** Timer 5 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
+/**@}*/
#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
#define ADC_CR2_EXTSEL_SHIFT 17
@@ -291,21 +402,54 @@
/* JEXTSEL[2:0]: External event selection for injected group. */
/* The following are only valid for ADC1 and ADC2. */
+/****************************************************************************/
+/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
+/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
+/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
+/** Timer 2 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
+/** Timer 2 Compare Output 1 */
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
+/** Timer 3 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
+/** Timer 4 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
+/** External Interrupt 15 */
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
+/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
+/**@}*/
/* The following are the different meanings for ADC3 only. */
+/****************************************************************************/
+/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
+/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+/** Timer 1 Trigger Output */
+#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
+/** Timer 1 Compare Output 4 */
+#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
+/** Timer 4 Compare Output 3 */
#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
+/** Timer 8 Compare Output 2 */
#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
+/** Timer 8 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
+/** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
+/** Timer53 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
+/** Injected Software Trigger */
+#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
+/**@}*/
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12
@@ -340,7 +484,6 @@
#define ADC_CR2_ADON (1 << 0)
/* --- ADC_SMPR1 values ---------------------------------------------------- */
-
#define ADC_SMPR1_SMP17_LSB 21
#define ADC_SMPR1_SMP16_LSB 18
#define ADC_SMPR1_SMP15_LSB 15
@@ -357,6 +500,12 @@
#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+/****************************************************************************/
+/* ADC_SMPR1 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_SMPR1_SMP_1DOT5CYC 0x0
#define ADC_SMPR1_SMP_7DOT5CYC 0x1
#define ADC_SMPR1_SMP_13DOT5CYC 0x2
@@ -365,6 +514,7 @@
#define ADC_SMPR1_SMP_55DOT5CYC 0x5
#define ADC_SMPR1_SMP_71DOT5CYC 0x6
#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_SMPR2 values ---------------------------------------------------- */
@@ -388,6 +538,12 @@
#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+/****************************************************************************/
+/* ADC_SMPR2 ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_r2 ADC Sample Time Selection for ADC2
+@ingroup STM32F1xx_adc_defines
+
+@{*/
#define ADC_SMPR2_SMP_1DOT5CYC 0x0
#define ADC_SMPR2_SMP_7DOT5CYC 0x1
#define ADC_SMPR2_SMP_13DOT5CYC 0x2
@@ -396,9 +552,15 @@
#define ADC_SMPR2_SMP_55DOT5CYC 0x5
#define ADC_SMPR2_SMP_71DOT5CYC 0x6
#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_SMPRx generic values -------------------------------------------- */
+/****************************************************************************/
+/* ADC_SMPRG ADC Sample Time Selection for Channels */
+/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
+@ingroup STM32F1xx_adc_defines
+@{*/
#define ADC_SMPR_SMP_1DOT5CYC 0x0
#define ADC_SMPR_SMP_7DOT5CYC 0x1
#define ADC_SMPR_SMP_13DOT5CYC 0x2
@@ -407,6 +569,7 @@
#define ADC_SMPR_SMP_55DOT5CYC 0x5
#define ADC_SMPR_SMP_71DOT5CYC 0x6
#define ADC_SMPR_SMP_239DOT5CYC 0x7
+/**@}*/
/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
@@ -424,11 +587,11 @@
#define ADC_SQR1_SQ15_LSB 10
#define ADC_SQR1_SQ14_LSB 5
#define ADC_SQR1_SQ13_LSB 0
-#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB)
-#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB)
-#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
-#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
-#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
+#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
/* --- ADC_SQR2 values ----------------------------------------------------- */
@@ -438,12 +601,12 @@
#define ADC_SQR2_SQ9_LSB 10
#define ADC_SQR2_SQ8_LSB 5
#define ADC_SQR2_SQ7_LSB 0
-#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB)
-#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB)
-#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB)
-#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
-#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
-#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
/* --- ADC_SQR3 values ----------------------------------------------------- */
@@ -453,13 +616,12 @@
#define ADC_SQR3_SQ3_LSB 10
#define ADC_SQR3_SQ2_LSB 5
#define ADC_SQR3_SQ1_LSB 0
-#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB)
-#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB)
-#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB)
-#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
-#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
-#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
-
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
@@ -467,11 +629,24 @@
#define ADC_JSQR_JSQ3_LSB 10
#define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0
-#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB)
-#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB)
-#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
-#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
-#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
+
+/* JL[2:0]: Discontinous mode channel count injected channels. */
+/****************************************************************************/
+/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
+@ingroup STM32F1xx_adc_defines
+
+@{*/
+#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
+/**@}*/
+#define ADC_JSQR_JL_SHIFT 13
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@@ -481,28 +656,37 @@
#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
#define ADC_DATA_MSK (0xffff << ADC_DA)
#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
- /* ADC1 only (dual mode) */
+ /* ADC1 only (dual mode) */
/* --- Function prototypes ------------------------------------------------- */
-
-/* TODO */
+BEGIN_DECLS
+
+void adc_power_on(u32 adc);
+void adc_start_conversion_direct(u32 adc);
+void adc_set_single_channel(u32 adc, u8 channel);
+void adc_set_dual_mode(u32 mode);
+bool adc_eoc(u32 adc);
+bool adc_eoc_injected(u32 adc);
+u32 adc_read_regular(u32 adc);
+u32 adc_read_injected(u32 adc, u8 reg);
+void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc);
void adc_disable_analog_watchdog_injected(u32 adc);
-void adc_enable_discontinous_mode_regular(u32 adc);
-void adc_disable_discontinous_mode_regular(u32 adc);
-void adc_enable_discontinous_mode_injected(u32 adc);
-void adc_disable_discontinous_mode_injected(u32 adc);
+void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
+void adc_disable_discontinuous_mode_regular(u32 adc);
+void adc_enable_discontinuous_mode_injected(u32 adc);
+void adc_disable_discontinuous_mode_injected(u32 adc);
void adc_enable_automatic_injected_group_conversion(u32 adc);
void adc_disable_automatic_injected_group_conversion(u32 adc);
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
void adc_enable_scan_mode(u32 adc);
void adc_disable_scan_mode(u32 adc);
-void adc_enable_jeoc_interrupt(u32 adc);
-void adc_disable_jeoc_interrupt(u32 adc);
+void adc_enable_eoc_interrupt_injected(u32 adc);
+void adc_disable_eoc_interrupt_injected(u32 adc);
void adc_enable_awd_interrupt(u32 adc);
void adc_disable_awd_interrupt(u32 adc);
void adc_enable_eoc_interrupt(u32 adc);
@@ -521,15 +705,30 @@ void adc_enable_dma(u32 adc);
void adc_disable_dma(u32 adc);
void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
-void adc_set_continous_conversion_mode(u32 adc);
+void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
+#ifdef __GNUC__
+void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release")));
+#else
void adc_on(u32 adc);
+#endif
void adc_off(u32 adc);
-void adc_set_conversion_time(u32 adc, u8 channel, u8 time);
-void adc_set_conversion_time_on_all_channels(u32 adc, u8 time);
+void adc_set_sample_time(u32 adc, u8 channel, u8 time);
+void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+#ifdef __GNUC__
+void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode")));
+void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time")));
+void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels")));
+void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected")));
+void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected")));
#endif
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/f1/desig.h
index 743e946..74cfb35 100644
--- a/include/libopencm3/stm32/f1/desig.h
+++ b/include/libopencm3/stm32/f1/desig.h
@@ -36,6 +36,8 @@
#define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04)
#define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08)
+BEGIN_DECLS
+
/**
* Read the onboard flash size
* @return flash size in KB
@@ -49,4 +51,6 @@ u16 desig_get_flash_size(void);
*/
void desig_get_unique_id(u32 result[]);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 64eafe0..b08803f 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -346,6 +346,8 @@ LGPL License Terms @ref lgpl_license
/* --- function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void dma_channel_reset(u32 dma, u8 channel);
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
void dma_set_priority(u32 dma, u8 channel, u32 prio);
@@ -368,6 +370,8 @@ void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/f1/doc-stm32f1.h b/include/libopencm3/stm32/f1/doc-stm32f1.h
index 04293a6..4e1407e 100644
--- a/include/libopencm3/stm32/f1/doc-stm32f1.h
+++ b/include/libopencm3/stm32/f1/doc-stm32f1.h
@@ -1,15 +1,32 @@
-/** @defgroup STM32F1xx_defines STM32F1xx Defines
+/** @mainpage libopencm3 STM32F1
-@brief Defined Constants and Types for the STM32F1xx series
+@version 1.0.0
+
+@date 7 September 2012
-@ingroup STM32F1xx
+API documentation for ST Microelectronics STM32F1 Cortex M3 series.
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F1xx STM32F1xx
+Libraries for ST Microelectronics STM32F1xx series.
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F1xx_defines STM32F1xx Defines
+
+@brief Defined Constants and Types for the STM32F1xx series
@version 1.0.0
-@date 18 August 2012
+@date 7 September 2012
LGPL License Terms @ref lgpl_license
- */
+*/
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 2c026d6..919b4d4 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -89,6 +89,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_halfcycle_enable(void);
@@ -110,4 +112,6 @@ void flash_wait_for_last_operation(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index 2f4292a..a1e74cc 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -950,6 +950,8 @@ Line Devices only
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
void gpio_set(u32 gpioport, u16 gpios);
void gpio_clear(u32 gpioport, u16 gpios);
@@ -962,6 +964,8 @@ void gpio_set_eventout(u8 evoutport, u8 evoutpin);
void gpio_primary_remap(u8 swjenable, u32 maps);
void gpio_secondary_remap(u32 maps);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h
index bb0e03d..5223bb6 100644
--- a/include/libopencm3/stm32/f1/nvic_f1.h
+++ b/include/libopencm3/stm32/f1/nvic_f1.h
@@ -1,8 +1,4 @@
-/** @defgroup STM32F_nvic_f1_defines STM32F NVIC Defines
-
-@brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
-
-@ingroup STM32F_defines
+/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
@version 1.0.0
@@ -113,6 +109,6 @@ LGPL License Terms @ref lgpl_license
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
-/*@}*/
+/**@}*/
#endif
diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h
index 63f6770..855e43b 100644
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -476,6 +476,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -512,6 +514,8 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index 5e203ab..04aea01 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -126,6 +126,8 @@ typedef enum {
RTC_SEC, RTC_ALR, RTC_OW,
} rtcflag_t;
+BEGIN_DECLS
+
void rtc_awake_from_off(osc_t clock_source);
void rtc_enter_config_mode(void);
void rtc_exit_config_mode(void);
@@ -144,4 +146,6 @@ u32 rtc_check_flag(rtcflag_t flag_val);
void rtc_awake_from_standby(void);
void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f1/scb.h b/include/libopencm3/stm32/f1/scb.h
index 12a74a2..181aa7a 100644
--- a/include/libopencm3/stm32/f1/scb.h
+++ b/include/libopencm3/stm32/f1/scb.h
@@ -293,10 +293,15 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/doc-stm32f2.h b/include/libopencm3/stm32/f2/doc-stm32f2.h
new file mode 100644
index 0000000..faa7f29
--- /dev/null
+++ b/include/libopencm3/stm32/f2/doc-stm32f2.h
@@ -0,0 +1,33 @@
+/** @mainpage libopencm3 STM32F2
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for ST Microelectronics STM32F2 Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+
+/** @defgroup STM32F2xx STM32F2xx
+Libraries for ST Microelectronics STM32F2xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F2xx_defines STM32F2xx Defines
+
+@brief Defined Constants and Types for the STM32F2xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h
index 5b4483f..2c78757 100644
--- a/include/libopencm3/stm32/f2/flash.h
+++ b/include/libopencm3/stm32/f2/flash.h
@@ -116,6 +116,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_dcache_enable(void);
void flash_dcache_disable(void);
void flash_icache_enable(void);
@@ -145,4 +147,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h
index 1a9fd0f..6616769 100644
--- a/include/libopencm3/stm32/f2/gpio.h
+++ b/include/libopencm3/stm32/f2/gpio.h
@@ -254,6 +254,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
/*
* Note: The F2 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
@@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h
index dfce266..4ffa242 100644
--- a/include/libopencm3/stm32/f2/rcc.h
+++ b/include/libopencm3/stm32/f2/rcc.h
@@ -479,6 +479,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -509,4 +511,6 @@ u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/scb.h b/include/libopencm3/stm32/f2/scb.h
index 12a74a2..181aa7a 100644
--- a/include/libopencm3/stm32/f2/scb.h
+++ b/include/libopencm3/stm32/f2/scb.h
@@ -293,10 +293,15 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f2/timer.h b/include/libopencm3/stm32/f2/timer.h
index 3436bba..737d6f0 100644
--- a/include/libopencm3/stm32/f2/timer.h
+++ b/include/libopencm3/stm32/f2/timer.h
@@ -52,6 +52,10 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void timer_set_option(u32 timer_peripheral, u32 option);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/doc-stm32f4.h b/include/libopencm3/stm32/f4/doc-stm32f4.h
new file mode 100644
index 0000000..39d7091
--- /dev/null
+++ b/include/libopencm3/stm32/f4/doc-stm32f4.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 STM32F4
+
+@version 1.0.0
+
+@date 7 September 2012
+
+API documentation for ST Microelectronics STM32F4 Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F4xx STM32F4xx
+Libraries for ST Microelectronics STM32F4xx series.
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F4xx_defines STM32F4xx Defines
+
+@brief Defined Constants and Types for the STM32F4xx series
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
index f85d56f..2221333 100644
--- a/include/libopencm3/stm32/f4/flash.h
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -115,6 +115,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_dcache_enable(void);
void flash_dcache_disable(void);
void flash_icache_enable(void);
@@ -144,4 +146,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
index a5b4361..b7da9c6 100644
--- a/include/libopencm3/stm32/f4/gpio.h
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -254,6 +254,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
/*
* Note: The F4 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
@@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
index ede1ae7..25fb163 100644
--- a/include/libopencm3/stm32/f4/pwr.h
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -63,6 +63,10 @@ typedef enum {
SCALE2,
} vos_scale_t;
+BEGIN_DECLS
+
void pwr_set_vos_scale(vos_scale_t scale);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 648ccb0..1688584 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -482,6 +482,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -512,4 +514,6 @@ u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h
index 12a74a2..7187ca9 100644
--- a/include/libopencm3/stm32/f4/scb.h
+++ b/include/libopencm3/stm32/f4/scb.h
@@ -72,6 +72,63 @@
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+/* ID_PFR0: Processor Feature Register 0 */
+#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
+
+/* ID_PFR1: Processor Feature Register 1 */
+#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
+
+/* ID_DFR0: Debug Features Register 0 */
+#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
+
+/* ID_AFR0: Auxiliary Features Register 0 */
+#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
+
+/* ID_MMFR0: Memory Model Feature Register 0 */
+#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
+
+/* ID_MMFR1: Memory Model Feature Register 1 */
+#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
+
+/* ID_MMFR2: Memory Model Feature Register 2 */
+#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
+
+/* ID_MMFR3: Memory Model Feature Register 3 */
+#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
+
+/* ID_ISAR0: Instruction Set Attributes Register 0 */
+#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
+
+/* ID_ISAR1: Instruction Set Attributes Register 1 */
+#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
+
+/* ID_ISAR2: Instruction Set Attributes Register 2 */
+#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
+
+/* ID_ISAR3: Instruction Set Attributes Register 3 */
+#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
+
+/* ID_ISAR4: Instruction Set Attributes Register 4 */
+#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
+
+/* CPACR: Coprocessor Access Control Register */
+#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
+
+/* FPCCR: Floating-Point Context Control Register */
+#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
+
+/* FPCAR: Floating-Point Context Address Register */
+#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
+
+/* FPDSCR: Floating-Point Default Status Control Register */
+#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
+
+/* MVFR0: Media and Floating-Point Feature Register 0 */
+#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
+
+/* MVFR1: Media and Floating-Point Feature Register 1 */
+#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
+
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
@@ -292,11 +349,28 @@
/* BFAR [31:0]: Bus fault address */
+/* --- SCB_CPACR values ---------------------------------------------------- */
+
+/* CPACR CPn: Access privileges values */
+#define SCB_CPACR_NONE 0 /* Access denied */
+#define SCB_CPACR_PRIV 1 /* Privileged access only */
+#define SCB_CPACR_FULL 3 /* Full access */
+
+/* CPACR [20:21]: Access privileges for coprocessor 10 */
+#define SCB_CPACR_CP10 (1 << 20)
+/* CPACR [22:23]: Access privileges for coprocessor 11 */
+#define SCB_CPACR_CP11 (1 << 22)
+
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/timer.h b/include/libopencm3/stm32/f4/timer.h
index 6d19990..988d02c 100644
--- a/include/libopencm3/stm32/f4/timer.h
+++ b/include/libopencm3/stm32/f4/timer.h
@@ -52,6 +52,10 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void timer_set_option(u32 timer_peripheral, u32 option);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index 1606b64..13257eb 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -316,6 +316,8 @@
/* --- I2C funtion prototypes----------------------------------------------- */
+BEGIN_DECLS
+
void i2c_reset(u32 i2c);
void i2c_peripheral_enable(u32 i2c);
void i2c_peripheral_disable(u32 i2c);
@@ -331,4 +333,6 @@ void i2c_set_trise(u32 i2c, u16 trise);
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
void i2c_send_data(u32 i2c, u8 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h
index a5f1ac1..4e44907 100644
--- a/include/libopencm3/stm32/iwdg.h
+++ b/include/libopencm3/stm32/iwdg.h
@@ -106,12 +106,16 @@ LGPL License Terms @ref lgpl_license
/* --- IWDG function prototypes---------------------------------------------- */
+BEGIN_DECLS
+
void iwdg_start(void);
void iwdg_set_period_ms(u32 period);
bool iwdg_reload_busy(void);
bool iwdg_prescaler_busy(void);
void iwdg_reset(void);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h
index 6a98737..694fab8 100644
--- a/include/libopencm3/stm32/nvic.h
+++ b/include/libopencm3/stm32/nvic.h
@@ -1,4 +1,4 @@
-/** @defgroup STM32F_nvic_defines STM32F NVIC Defines
+/** @defgroup STM32F_nvic_defines NVIC Defines
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
@@ -96,7 +96,7 @@ IRQ numbers -3 and -6 to -9 are reserved
/* irq number -3 reserved */
#define NVIC_PENDSV_IRQ -2
#define NVIC_SYSTICK_IRQ -1
-/*@}*/
+/**@}*/
/* Note: User interrupts are family specific and are defined in a family
@@ -116,6 +116,8 @@ IRQ numbers -3 and -6 to -9 are reserved
/* --- NVIC functions ------------------------------------------------------ */
+BEGIN_DECLS
+
void nvic_enable_irq(u8 irqn);
void nvic_disable_irq(u8 irqn);
u8 nvic_get_pending_irq(u8 irqn);
@@ -126,6 +128,8 @@ u8 nvic_get_irq_enabled(u8 irqn);
void nvic_set_priority(u8 irqn, u8 priority);
void nvic_generate_software_interrupt(u16 irqn);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
index 7084382..e709f3d 100644
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -106,6 +106,8 @@ LGPL License Terms @ref lgpl_license
/* --- PWR function prototypes ------------------------------------------- */
+BEGIN_DECLS
+
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_power_voltage_detect(u32 pvd_level);
@@ -122,6 +124,8 @@ bool pwr_voltage_high(void);
bool pwr_get_standby_flag(void);
bool pwr_get_wakeup_flag(void);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/sdio.h b/include/libopencm3/stm32/sdio.h
index cf9b056..16244ed 100644
--- a/include/libopencm3/stm32/sdio.h
+++ b/include/libopencm3/stm32/sdio.h
@@ -142,7 +142,7 @@
#define SDIO_CMD_WAITRESP_SHIFT 6
/* 00: No response, expect CMDSENT flag */
#define SDIO_CMD_WAITRESP_NO_0 (0x0 << SDIO_CMD_WAITRESP_SHIFT)
-/* 01: Short response, expect CMDREND or CCRCFAIL flag
+/* 01: Short response, expect CMDREND or CCRCFAIL flag */
#define SDIO_CMD_WAITRESP_SHORT (0x1 << SDIO_CMD_WAITRESP_SHIFT)
/* 10: No response, expect CMDSENT flag */
#define SDIO_CMD_WAITRESP_NO_2 (0x2 << SDIO_CMD_WAITRESP_SHIFT)
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index e64dd0f..11ba820 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -297,6 +297,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void spi_reset(u32 spi_peripheral);
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
void spi_enable(u32 spi);
@@ -343,4 +345,6 @@ void spi_disable_tx_dma(u32 spi);
void spi_enable_rx_dma(u32 spi);
void spi_disable_rx_dma(u32 spi);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h
index aa6c287..e42c4e6 100644
--- a/include/libopencm3/stm32/systick.h
+++ b/include/libopencm3/stm32/systick.h
@@ -93,6 +93,8 @@ LGPL License Terms @ref lgpl_license
/* --- Function Prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void systick_set_reload(u32 value);
u32 systick_get_value(void);
void systick_set_clocksource(u8 clocksource);
@@ -102,6 +104,8 @@ void systick_counter_enable(void);
void systick_counter_disable(void);
u8 systick_get_countflag(void);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index b1e1064..b6f8949 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -1022,6 +1022,9 @@ enum tim_ic_pol {
};
/* --- TIM function prototypes ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
@@ -1101,6 +1104,8 @@ void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
void timer_slave_set_mode(u32 timer, u8 mode);
void timer_slave_set_trigger(u32 timer, u8 trigger);
+END_DECLS
+
#endif
/**@}*/
diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h
index 5c7f285..9ec6c3d 100644
--- a/include/libopencm3/stm32/usart.h
+++ b/include/libopencm3/stm32/usart.h
@@ -294,6 +294,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void usart_set_baudrate(u32 usart, u32 baud);
void usart_set_databits(u32 usart, u32 bits);
void usart_set_stopbits(u32 usart, u32 stopbits);
@@ -313,4 +315,6 @@ void usart_disable_rx_dma(u32 usart);
void usart_enable_tx_dma(u32 usart);
void usart_disable_tx_dma(u32 usart);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h
index f453bc2..e4b3578 100644
--- a/include/libopencm3/usb/usbd.h
+++ b/include/libopencm3/usb/usbd.h
@@ -22,6 +22,8 @@
#include <libopencm3/usb/usbstd.h>
+BEGIN_DECLS
+
typedef struct _usbd_driver usbd_driver;
extern const usbd_driver stm32f103_usb_driver;
extern const usbd_driver stm32f107_usb_driver;
@@ -73,4 +75,6 @@ extern void usbd_ep_nak_set(u8 addr, u8 nak);
/* Optional */
extern void usbd_cable_connect(u8 on);
+END_DECLS
+
#endif