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-rw-r--r--include/libopencm3/stm32/can.h30
-rw-r--r--include/libopencm3/stm32/common/gpio_common_all.h73
-rw-r--r--include/libopencm3/stm32/common/gpio_common_f24.h285
-rw-r--r--include/libopencm3/stm32/desig.h (renamed from include/libopencm3/stm32/f1/desig.h)9
-rw-r--r--include/libopencm3/stm32/f1/dma.h1
-rw-r--r--include/libopencm3/stm32/f1/gpio.h88
-rw-r--r--include/libopencm3/stm32/f1/rcc.h25
-rw-r--r--include/libopencm3/stm32/f2/gpio.h280
-rw-r--r--include/libopencm3/stm32/f4/gpio.h280
-rw-r--r--include/libopencm3/stm32/f4/syscfg.h46
-rw-r--r--include/libopencm3/stm32/gpio.h31
-rw-r--r--include/libopencm3/stm32/i2c.h20
-rw-r--r--include/libopencm3/stm32/l1/doc-stm32l1.h32
-rw-r--r--include/libopencm3/stm32/l1/gpio.h266
-rw-r--r--include/libopencm3/stm32/l1/irq.yaml49
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h108
-rw-r--r--include/libopencm3/stm32/l1/rcc.h404
-rw-r--r--include/libopencm3/stm32/memorymap.h2
-rw-r--r--include/libopencm3/stm32/pwr.h2
-rw-r--r--include/libopencm3/stm32/syscfg.h (renamed from include/libopencm3/stm32/f2/syscfg.h)0
20 files changed, 1400 insertions, 631 deletions
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
index cdb5df1..65aca5c 100644
--- a/include/libopencm3/stm32/can.h
+++ b/include/libopencm3/stm32/can.h
@@ -1,3 +1,17 @@
+/** @defgroup can_defines CAN defines
+
+@ingroup STM32F_defines
+
+@brief <b>libopencm3 Defined Constants and Types for STM32 CAN </b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 12 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,11 +37,19 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+/**@{*/
+
/* --- Convenience macros -------------------------------------------------- */
/* CAN register base adresses (for convenience) */
+/*****************************************************************************/
+/** @defgroup can_reg_base CAN register base address
+@ingroup can_defines
+
+@{*/
#define CAN1 BX_CAN1_BASE
#define CAN2 BX_CAN2_BASE
+/**@}*/
/* --- CAN registers ------------------------------------------------------- */
@@ -417,6 +439,7 @@
#define CAN_BTR_SJW_3TQ (0x2 << 24)
#define CAN_BTR_SJW_4TQ (0x3 << 24)
#define CAN_BTR_SJW_MASK (0x3 << 24)
+#define CAN_BTR_SJW_SHIFT 24
/* 23 Reserved, forced by hardware to 0 */
@@ -430,6 +453,7 @@
#define CAN_BTR_TS2_7TQ (0x6 << 20)
#define CAN_BTR_TS2_8TQ (0x7 << 20)
#define CAN_BTR_TS2_MASK (0x7 << 20)
+#define CAN_BTR_TS2_SHIFT 20
/* TS1[3:0]: Time segment 1 */
#define CAN_BTR_TS1_1TQ (0x0 << 16)
@@ -449,6 +473,7 @@
#define CAN_BTR_TS1_15TQ (0xE << 16)
#define CAN_BTR_TS1_16TQ (0xF << 16)
#define CAN_BTR_TS1_MASK (0xF << 16)
+#define CAN_BTR_TS1_SHIFT 16
/* 15:10 Reserved, forced by hardware to 0 */
@@ -619,7 +644,8 @@ BEGIN_DECLS
void can_reset(u32 canport);
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
- bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp);
+ bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
+ bool loopback, bool silent);
void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
u32 fr1, u32 fr2, u32 fifo, bool enable);
@@ -640,7 +666,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
bool *rtr, u32 *fmi, u8 *length, u8 *data);
void can_fifo_release(u32 canport, u8 fifo);
-
+bool can_available_mailbox(u32 canport);
END_DECLS
#endif
diff --git a/include/libopencm3/stm32/common/gpio_common_all.h b/include/libopencm3/stm32/common/gpio_common_all.h
new file mode 100644
index 0000000..b2327e5
--- /dev/null
+++ b/include/libopencm3/stm32/common/gpio_common_all.h
@@ -0,0 +1,73 @@
+/** @addtogroup gpio_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H */
+
+#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H
+#define LIBOPENCM3_GPIO_COMMON_ALL_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* --- GPIO_LCKR values ---------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup gpio_defines
+
+@{*/
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+#define GPIO8 (1 << 8)
+#define GPIO9 (1 << 9)
+#define GPIO10 (1 << 10)
+#define GPIO11 (1 << 11)
+#define GPIO12 (1 << 12)
+#define GPIO13 (1 << 13)
+#define GPIO14 (1 << 14)
+#define GPIO15 (1 << 15)
+#define GPIO_ALL 0xffff
+/**@}*/
+
+void gpio_set(u32 gpioport, u16 gpios);
+void gpio_clear(u32 gpioport, u16 gpios);
+u16 gpio_get(u32 gpioport, u16 gpios);
+void gpio_toggle(u32 gpioport, u16 gpios);
+u16 gpio_port_read(u32 gpioport);
+void gpio_port_write(u32 gpioport, u16 data);
+void gpio_port_config_lock(u32 gpioport, u16 gpios);
+
+/**@}*/
+#endif
+
diff --git a/include/libopencm3/stm32/common/gpio_common_f24.h b/include/libopencm3/stm32/common/gpio_common_f24.h
new file mode 100644
index 0000000..f8bd4fb
--- /dev/null
+++ b/include/libopencm3/stm32/common/gpio_common_f24.h
@@ -0,0 +1,285 @@
+/** @addtogroup gpio_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H */
+
+#ifndef LIBOPENCM3_GPIO_COMMON_F24_H
+#define LIBOPENCM3_GPIO_COMMON_F24_H
+
+/**@{*/
+
+#include <libopencm3/stm32/common/gpio_common_all.h>
+
+/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup gpio_defines
+
+@{*/
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOF GPIO_PORT_F_BASE
+#define GPIOG GPIO_PORT_G_BASE
+#define GPIOH GPIO_PORT_H_BASE
+#define GPIOI GPIO_PORT_I_BASE
+/**@}*/
+
+/* --- GPIO registers for STM32F2 and STM32F4 --------------------------- */
+
+/* Port mode register (GPIOx_MODER) */
+#define GPIO_MODER(port) MMIO32(port + 0x00)
+#define GPIOA_MODER GPIO_MODER(GPIOA)
+#define GPIOB_MODER GPIO_MODER(GPIOB)
+#define GPIOC_MODER GPIO_MODER(GPIOC)
+#define GPIOD_MODER GPIO_MODER(GPIOD)
+#define GPIOE_MODER GPIO_MODER(GPIOE)
+#define GPIOF_MODER GPIO_MODER(GPIOF)
+#define GPIOG_MODER GPIO_MODER(GPIOG)
+#define GPIOH_MODER GPIO_MODER(GPIOH)
+#define GPIOI_MODER GPIO_MODER(GPIOI)
+
+/* Port output type register (GPIOx_OTYPER) */
+#define GPIO_OTYPER(port) MMIO32(port + 0x04)
+#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
+#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
+#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
+#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
+#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
+#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
+#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
+#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
+#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
+
+/* Port output speed register (GPIOx_OSPEEDR) */
+#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
+#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
+#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
+#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
+#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
+#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
+#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
+#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
+#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
+#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
+
+/* Port pull-up/pull-down register (GPIOx_PUPDR) */
+#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
+#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
+#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
+#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
+#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
+#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
+#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
+#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
+#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
+#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x10)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOF_IDR GPIO_IDR(GPIOF)
+#define GPIOG_IDR GPIO_IDR(GPIOG)
+#define GPIOH_IDR GPIO_IDR(GPIOH)
+#define GPIOI_IDR GPIO_IDR(GPIOI)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x14)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOF_ODR GPIO_ODR(GPIOF)
+#define GPIOG_ODR GPIO_ODR(GPIOG)
+#define GPIOH_ODR GPIO_ODR(GPIOH)
+#define GPIOI_ODR GPIO_ODR(GPIOI)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x18)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOF_BSRR GPIO_BSRR(GPIOF)
+#define GPIOG_BSRR GPIO_BSRR(GPIOG)
+#define GPIOH_BSRR GPIO_BSRR(GPIOH)
+#define GPIOI_BSRR GPIO_BSRR(GPIOI)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x1c)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOF_LCKR GPIO_LCKR(GPIOF)
+#define GPIOG_LCKR GPIO_LCKR(GPIOG)
+#define GPIOH_LCKR GPIO_LCKR(GPIOH)
+#define GPIOI_LCKR GPIO_LCKR(GPIOI)
+
+/* Alternate function low register (GPIOx_AFRL) */
+#define GPIO_AFRL(port) MMIO32(port + 0x20)
+#define GPIOA_AFRL GPIO_AFRL(GPIOA)
+#define GPIOB_AFRL GPIO_AFRL(GPIOB)
+#define GPIOC_AFRL GPIO_AFRL(GPIOC)
+#define GPIOD_AFRL GPIO_AFRL(GPIOD)
+#define GPIOE_AFRL GPIO_AFRL(GPIOE)
+#define GPIOF_AFRL GPIO_AFRL(GPIOF)
+#define GPIOG_AFRL GPIO_AFRL(GPIOG)
+#define GPIOH_AFRL GPIO_AFRL(GPIOH)
+#define GPIOI_AFRL GPIO_AFRL(GPIOI)
+
+/* Alternate function high register (GPIOx_AFRH) */
+#define GPIO_AFRH(port) MMIO32(port + 0x24)
+#define GPIOA_AFRH GPIO_AFRH(GPIOA)
+#define GPIOB_AFRH GPIO_AFRH(GPIOB)
+#define GPIOC_AFRH GPIO_AFRH(GPIOC)
+#define GPIOD_AFRH GPIO_AFRH(GPIOD)
+#define GPIOE_AFRH GPIO_AFRH(GPIOE)
+#define GPIOF_AFRH GPIO_AFRH(GPIOF)
+#define GPIOG_AFRH GPIO_AFRH(GPIOG)
+#define GPIOH_AFRH GPIO_AFRH(GPIOH)
+#define GPIOI_AFRH GPIO_AFRH(GPIOI)
+
+/* --- GPIOx_MODER values -------------------------------------------------- */
+
+#define GPIO_MODE(n, mode) (mode << (2 * (n)))
+#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode
+@ingroup gpio_defines
+@{*/
+#define GPIO_MODE_INPUT 0x0
+#define GPIO_MODE_OUTPUT 0x1
+#define GPIO_MODE_AF 0x2
+#define GPIO_MODE_ANALOG 0x3
+/**@}*/
+
+/* --- GPIOx_OTYPER values ------------------------------------------------- */
+
+/** @defgroup gpio_output_type GPIO Output Pin Driver Type
+@ingroup gpio_defines
+@list Push Pull
+@list Open Drain
+@{*/
+#define GPIO_OTYPE_PP 0x0
+#define GPIO_OTYPE_OD 0x1
+/**@}*/
+
+/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
+
+#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
+#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_speed GPIO Output Pin Speed
+@ingroup gpio_defines
+@{*/
+#define GPIO_OSPEED_2MHZ 0x0
+#define GPIO_OSPEED_25MHZ 0x1
+#define GPIO_OSPEED_50MHZ 0x2
+#define GPIO_OSPEED_100MHZ 0x3
+/**@}*/
+
+/* --- GPIOx_PUPDR values -------------------------------------------------- */
+
+#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
+#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_pup GPIO Output Pin Pullup
+@ingroup gpio_defines
+@{*/
+#define GPIO_PUPD_NONE 0x0
+#define GPIO_PUPD_PULLUP 0x1
+#define GPIO_PUPD_PULLDOWN 0x2
+/**@}*/
+
+/* --- GPIOx_IDR values ---------------------------------------------------- */
+
+/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIOx_ODR values ---------------------------------------------------- */
+
+/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIOx_BSRR values --------------------------------------------------- */
+
+/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIOx_LCKR values --------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- GPIOx_AFRL/H values ------------------------------------------------- */
+
+/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
+/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
+
+#define GPIO_AFR(n, af) (af << ((n) * 4))
+#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
+/** @defgroup gpio_af_num Alternate Function Pin Selection
+@ingroup gpio_defines
+@{*/
+#define GPIO_AF0 0x0
+#define GPIO_AF1 0x1
+#define GPIO_AF2 0x2
+#define GPIO_AF3 0x3
+#define GPIO_AF4 0x4
+#define GPIO_AF5 0x5
+#define GPIO_AF6 0x6
+#define GPIO_AF7 0x7
+#define GPIO_AF8 0x8
+#define GPIO_AF9 0x9
+#define GPIO_AF10 0xa
+#define GPIO_AF11 0xb
+#define GPIO_AF12 0xc
+#define GPIO_AF13 0xd
+#define GPIO_AF14 0xe
+#define GPIO_AF15 0xf
+/**@}*/
+
+/* Note: EXTI source selection is now in the SYSCFG peripheral. */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+/*
+ * Note: The F2 and F4 series have a completely new GPIO peripheral with different
+ * configuration options. Here we implement a different API partly to more
+ * closely match the peripheral capabilities and also to deliberately break
+ * compatibility with old F1 code so there is no confusion with similar
+ * sounding functions that have very different functionality.
+ */
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
+
+END_DECLS
+/**@}*/
+#endif
+
diff --git a/include/libopencm3/stm32/f1/desig.h b/include/libopencm3/stm32/desig.h
index 74cfb35..6ceb665 100644
--- a/include/libopencm3/stm32/f1/desig.h
+++ b/include/libopencm3/stm32/desig.h
@@ -51,6 +51,15 @@ u16 desig_get_flash_size(void);
*/
void desig_get_unique_id(u32 result[]);
+/**
+ * Read the full 96 bit unique identifier and return it as a
+ * zero-terminated string
+ * @param string memory region to write the result to
+ 8 @param string_len the size of string in bytes
+ */
+void desig_get_unique_id_as_string(char *string,
+ unsigned int string_len);
+
END_DECLS
#endif
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 6e5cc20..6257394 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -394,6 +394,7 @@ void dma_disable_channel(u32 dma, u8 channel);
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
+void dma_clear_flag(u32 dma, u32 flag);
END_DECLS
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index a1e74cc..7fb93c1 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -1,4 +1,4 @@
-/** @defgroup STM32F1xx_gpio_defines GPIO Defines
+/** @defgroup gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
@@ -8,6 +8,7 @@
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 1 July 2012
@@ -18,6 +19,7 @@ LGPL License Terms @ref lgpl_license
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -32,21 +34,23 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+
/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/f1/memorymap.h>
+#include <libopencm3/stm32/common/gpio_common_all.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
/** @defgroup gpio_port_id GPIO Port IDs
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
+/* GPIO port base addresses (for convenience) */
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
@@ -56,30 +60,6 @@ LGPL License Terms @ref lgpl_license
#define GPIOG GPIO_PORT_G_BASE
/**@}*/
-/* GPIO number definitions (for convenience) */
-/** @defgroup gpio_pin_id GPIO Pin Identifiers
-@ingroup STM32F1xx_gpio_defines
-
-@{*/
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-/**@}*/
-
/* --- Alternate function GPIOs -------------------------------------------- */
/* Default alternate functions of some pins (with and without remapping) */
@@ -103,18 +83,18 @@ LGPL License Terms @ref lgpl_license
/* CAN1 / CAN BANK */
#define GPIO_BANK_CAN1_RX GPIOA /* PA11 */
#define GPIO_BANK_CAN1_TX GPIOA /* PA12 */
-#define GPIO_BANK_CAN_RX GPIO_CAN1_RX /* Alias */
-#define GPIO_BANK_CAN_TX GPIO_CAN1_TX /* Alias */
+#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */
+#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */
#define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */
#define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */
-#define GPIO_BANK_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
-#define GPIO_BANK_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
+#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */
+#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */
#define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */
#define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */
-#define GPIO_BANK_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
-#define GPIO_BANK_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
+#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */
+#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */
/* CAN2 GPIO */
#define GPIO_CAN2_RX GPIO12 /* PB12 */
@@ -620,7 +600,7 @@ LGPL License Terms @ref lgpl_license
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
/** @defgroup gpio_cnf GPIO Pin Configuration
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
If mode specifies input, configuration can be
@li Analog input
@li Floating input
@@ -652,7 +632,7 @@ If mode specifies output, configuration can be
/* Pin mode (MODE[1:0]) values */
/** @defgroup gpio_mode GPIO Pin Mode
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@li Input (default after reset)
@li Output mode at 10 MHz maximum speed
@li Output mode at 2 MHz maximum speed
@@ -681,11 +661,6 @@ If mode specifies output, configuration can be
/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
-/* --- GPIO_LCKR values ---------------------------------------------------- */
-
-#define GPIO_LCKK (1 << 16)
-/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
-
/* --- AFIO registers ------------------------------------------------------ */
/* Event control register (AFIO_EVCR) */
@@ -716,7 +691,7 @@ If mode specifies output, configuration can be
/* PORT[2:0]: Port selection */
/** @defgroup afio_evcr_port EVENTOUT Port selection
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
@@ -728,7 +703,7 @@ If mode specifies output, configuration can be
/* PIN[3:0]: Pin selection */
/** @defgroup afio_evcr_pin EVENTOUT Pin selection
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
@@ -755,7 +730,7 @@ If mode specifies output, configuration can be
/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
Line Devices only
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
@@ -788,7 +763,7 @@ Line Devices only
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
/** @defgroup afio_swj_disable Serial Wire JTAG disables
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
@@ -803,7 +778,7 @@ Line Devices only
/**@}*/
/** @defgroup afio_remap Alternate Function Remap Controls
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
@@ -846,7 +821,7 @@ Line Devices only
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
@@ -856,7 +831,7 @@ Line Devices only
/* TIM3_REMAP[1:0]: TIM3 remapping */
/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
@@ -866,7 +841,7 @@ Line Devices only
/* TIM2_REMAP[1:0]: TIM2 remapping */
/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
@@ -877,7 +852,7 @@ Line Devices only
/* TIM1_REMAP[1:0]: TIM1 remapping */
/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
@@ -887,7 +862,7 @@ Line Devices only
/* USART3_REMAP[1:0]: USART3 remapping */
/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
@@ -896,7 +871,7 @@ Line Devices only
/**@}*/
/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
@@ -925,7 +900,7 @@ Line Devices only
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
/** @defgroup afio_exti Alternate Function EXTI pin number
-@ingroup STM32F1xx_gpio_defines
+@ingroup gpio_defines
@{*/
@@ -953,13 +928,6 @@ Line Devices only
BEGIN_DECLS
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
-void gpio_set(u32 gpioport, u16 gpios);
-void gpio_clear(u32 gpioport, u16 gpios);
-u16 gpio_get(u32 gpioport, u16 gpios);
-void gpio_toggle(u32 gpioport, u16 gpios);
-u16 gpio_port_read(u32 gpioport);
-void gpio_port_write(u32 gpioport, u16 data);
-void gpio_port_config_lock(u32 gpioport, u16 gpios);
void gpio_set_eventout(u8 evoutport, u8 evoutpin);
void gpio_primary_remap(u8 swjenable, u32 maps);
void gpio_secondary_remap(u32 maps);
diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h
index 855e43b..868ad9c 100644
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -86,7 +86,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
#define RCC_CFGR_MCO_HSECLK 0x6
-#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x7
#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
@@ -448,6 +448,24 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
+/* PREDIV: PREDIV division factor */
+#define RCC_CFGR2_PREDIV_NODIV 0x0
+#define RCC_CFGR2_PREDIV_DIV2 0x1
+#define RCC_CFGR2_PREDIV_DIV3 0x2
+#define RCC_CFGR2_PREDIV_DIV4 0x3
+#define RCC_CFGR2_PREDIV_DIV5 0x4
+#define RCC_CFGR2_PREDIV_DIV6 0x5
+#define RCC_CFGR2_PREDIV_DIV7 0x6
+#define RCC_CFGR2_PREDIV_DIV8 0x7
+#define RCC_CFGR2_PREDIV_DIV9 0x8
+#define RCC_CFGR2_PREDIV_DIV10 0x9
+#define RCC_CFGR2_PREDIV_DIV11 0xa
+#define RCC_CFGR2_PREDIV_DIV12 0xb
+#define RCC_CFGR2_PREDIV_DIV13 0xc
+#define RCC_CFGR2_PREDIV_DIV14 0xd
+#define RCC_CFGR2_PREDIV_DIV15 0xe
+#define RCC_CFGR2_PREDIV_DIV16 0xf
+
/* PREDIV2: PREDIV2 division factor */
#define RCC_CFGR2_PREDIV2_NODIV 0x0
#define RCC_CFGR2_PREDIV2_DIV2 0x1
@@ -473,7 +491,7 @@ extern u32 rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
typedef enum {
- PLL, HSE, HSI, LSE, LSI
+ PLL, PLL2, PLL3, HSE, HSI, LSE, LSI
} osc_t;
BEGIN_DECLS
@@ -489,6 +507,7 @@ void rcc_osc_on(osc_t osc);
void rcc_osc_off(osc_t osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
+void rcc_set_mco(u32 mcosrc);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
@@ -497,6 +516,7 @@ void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll2_multiplication_factor(u32 mul);
void rcc_set_pll_source(u32 pllsrc);
void rcc_set_pllxtpre(u32 pllxtpre);
void rcc_set_adcpre(u32 adcpre);
@@ -512,6 +532,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_25mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
END_DECLS
diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h
index 6616769..3ff2ba6 100644
--- a/include/libopencm3/stm32/f2/gpio.h
+++ b/include/libopencm3/stm32/f2/gpio.h
@@ -1,8 +1,23 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx General Purpose I/O</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -20,263 +35,8 @@
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* GPIO port base addresses (for convenience) */
-#define GPIOA GPIO_PORT_A_BASE
-#define GPIOB GPIO_PORT_B_BASE
-#define GPIOC GPIO_PORT_C_BASE
-#define GPIOD GPIO_PORT_D_BASE
-#define GPIOE GPIO_PORT_E_BASE
-#define GPIOF GPIO_PORT_F_BASE
-#define GPIOG GPIO_PORT_G_BASE
-#define GPIOH GPIO_PORT_H_BASE
-#define GPIOI GPIO_PORT_I_BASE
-
-/* GPIO number definitions (for convenience) */
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-
-/* --- GPIO registers ------------------------------------------------------ */
-
-/* Port mode register (GPIOx_MODER) */
-#define GPIO_MODER(port) MMIO32(port + 0x00)
-#define GPIOA_MODER GPIO_MODER(GPIOA)
-#define GPIOB_MODER GPIO_MODER(GPIOB)
-#define GPIOC_MODER GPIO_MODER(GPIOC)
-#define GPIOD_MODER GPIO_MODER(GPIOD)
-#define GPIOE_MODER GPIO_MODER(GPIOE)
-#define GPIOF_MODER GPIO_MODER(GPIOF)
-#define GPIOG_MODER GPIO_MODER(GPIOG)
-#define GPIOH_MODER GPIO_MODER(GPIOH)
-#define GPIOI_MODER GPIO_MODER(GPIOI)
-
-/* Port output type register (GPIOx_OTYPER) */
-#define GPIO_OTYPER(port) MMIO32(port + 0x04)
-#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
-#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
-#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
-#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
-#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
-#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
-#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
-#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
-#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
-
-/* Port output speed register (GPIOx_OSPEEDR) */
-#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
-#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
-#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
-#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
-#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
-#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
-#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
-#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
-#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
-#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
-
-/* Port pull-up/pull-down register (GPIOx_PUPDR) */
-#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
-#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
-#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
-#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
-#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
-#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
-#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
-#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
-#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
-#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
-
-/* Port input data register (GPIOx_IDR) */
-#define GPIO_IDR(port) MMIO32(port + 0x10)
-#define GPIOA_IDR GPIO_IDR(GPIOA)
-#define GPIOB_IDR GPIO_IDR(GPIOB)
-#define GPIOC_IDR GPIO_IDR(GPIOC)
-#define GPIOD_IDR GPIO_IDR(GPIOD)
-#define GPIOE_IDR GPIO_IDR(GPIOE)
-#define GPIOF_IDR GPIO_IDR(GPIOF)
-#define GPIOG_IDR GPIO_IDR(GPIOG)
-#define GPIOH_IDR GPIO_IDR(GPIOH)
-#define GPIOI_IDR GPIO_IDR(GPIOI)
-
-/* Port output data register (GPIOx_ODR) */
-#define GPIO_ODR(port) MMIO32(port + 0x14)
-#define GPIOA_ODR GPIO_ODR(GPIOA)
-#define GPIOB_ODR GPIO_ODR(GPIOB)
-#define GPIOC_ODR GPIO_ODR(GPIOC)
-#define GPIOD_ODR GPIO_ODR(GPIOD)
-#define GPIOE_ODR GPIO_ODR(GPIOE)
-#define GPIOF_ODR GPIO_ODR(GPIOF)
-#define GPIOG_ODR GPIO_ODR(GPIOG)
-#define GPIOH_ODR GPIO_ODR(GPIOH)
-#define GPIOI_ODR GPIO_ODR(GPIOI)
-
-/* Port bit set/reset register (GPIOx_BSRR) */
-#define GPIO_BSRR(port) MMIO32(port + 0x18)
-#define GPIOA_BSRR GPIO_BSRR(GPIOA)
-#define GPIOB_BSRR GPIO_BSRR(GPIOB)
-#define GPIOC_BSRR GPIO_BSRR(GPIOC)
-#define GPIOD_BSRR GPIO_BSRR(GPIOD)
-#define GPIOE_BSRR GPIO_BSRR(GPIOE)
-#define GPIOF_BSRR GPIO_BSRR(GPIOF)
-#define GPIOG_BSRR GPIO_BSRR(GPIOG)
-#define GPIOH_BSRR GPIO_BSRR(GPIOH)
-#define GPIOI_BSRR GPIO_BSRR(GPIOI)
-
-/* Port configuration lock register (GPIOx_LCKR) */
-#define GPIO_LCKR(port) MMIO32(port + 0x1c)
-#define GPIOA_LCKR GPIO_LCKR(GPIOA)
-#define GPIOB_LCKR GPIO_LCKR(GPIOB)
-#define GPIOC_LCKR GPIO_LCKR(GPIOC)
-#define GPIOD_LCKR GPIO_LCKR(GPIOD)
-#define GPIOE_LCKR GPIO_LCKR(GPIOE)
-#define GPIOF_LCKR GPIO_LCKR(GPIOF)
-#define GPIOG_LCKR GPIO_LCKR(GPIOG)
-#define GPIOH_LCKR GPIO_LCKR(GPIOH)
-#define GPIOI_LCKR GPIO_LCKR(GPIOI)
-
-/* Alternate function low register (GPIOx_AFRL) */
-#define GPIO_AFRL(port) MMIO32(port + 0x20)
-#define GPIOA_AFRL GPIO_AFRL(GPIOA)
-#define GPIOB_AFRL GPIO_AFRL(GPIOB)
-#define GPIOC_AFRL GPIO_AFRL(GPIOC)
-#define GPIOD_AFRL GPIO_AFRL(GPIOD)
-#define GPIOE_AFRL GPIO_AFRL(GPIOE)
-#define GPIOF_AFRL GPIO_AFRL(GPIOF)
-#define GPIOG_AFRL GPIO_AFRL(GPIOG)
-#define GPIOH_AFRL GPIO_AFRL(GPIOH)
-#define GPIOI_AFRL GPIO_AFRL(GPIOI)
-
-/* Alternate function high register (GPIOx_AFRH) */
-#define GPIO_AFRH(port) MMIO32(port + 0x24)
-#define GPIOA_AFRH GPIO_AFRH(GPIOA)
-#define GPIOB_AFRH GPIO_AFRH(GPIOB)
-#define GPIOC_AFRH GPIO_AFRH(GPIOC)
-#define GPIOD_AFRH GPIO_AFRH(GPIOD)
-#define GPIOE_AFRH GPIO_AFRH(GPIOE)
-#define GPIOF_AFRH GPIO_AFRH(GPIOF)
-#define GPIOG_AFRH GPIO_AFRH(GPIOG)
-#define GPIOH_AFRH GPIO_AFRH(GPIOH)
-#define GPIOI_AFRH GPIO_AFRH(GPIOI)
-
-/* --- GPIOx_MODER values -------------------------------------------------- */
-
-#define GPIO_MODE(n, mode) (mode << (2 * (n)))
-#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_MODE_INPUT 0x0
-#define GPIO_MODE_OUTPUT 0x1
-#define GPIO_MODE_AF 0x2
-#define GPIO_MODE_ANALOG 0x3
-
-/* --- GPIOx_OTYPER values ------------------------------------------------- */
-
-#define GPIO_OTYPE_PP 0x0
-#define GPIO_OTYPE_OD 0x1
-
-/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
-
-#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
-#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_OSPEED_2MHZ 0x0
-#define GPIO_OSPEED_25MHZ 0x1
-#define GPIO_OSPEED_50MHZ 0x2
-#define GPIO_OSPEED_100MHZ 0x3
-
-/* --- GPIOx_PUPDR values -------------------------------------------------- */
-
-#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
-#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_PUPD_NONE 0x0
-#define GPIO_PUPD_PULLUP 0x1
-#define GPIO_PUPD_PULLDOWN 0x2
-
-/* --- GPIOx_IDR values ---------------------------------------------------- */
-
-/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
-
-/* --- GPIOx_ODR values ---------------------------------------------------- */
-
-/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
-
-/* --- GPIOx_BSRR values --------------------------------------------------- */
-
-/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
-/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
-
-/* --- GPIOx_LCKR values --------------------------------------------------- */
-
-#define GPIO_LCKK (1 << 16)
-/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
-
-/* --- GPIOx_AFRL/H values ------------------------------------------------- */
-
-/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
-/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
-
-#define GPIO_AFR(n, af) (af << ((n) * 4))
-#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
-#define GPIO_AF0 0x0
-#define GPIO_AF1 0x1
-#define GPIO_AF2 0x2
-#define GPIO_AF3 0x3
-#define GPIO_AF4 0x4
-#define GPIO_AF5 0x5
-#define GPIO_AF6 0x6
-#define GPIO_AF7 0x7
-#define GPIO_AF8 0x8
-#define GPIO_AF9 0x9
-#define GPIO_AF10 0xa
-#define GPIO_AF11 0xb
-#define GPIO_AF12 0xc
-#define GPIO_AF13 0xd
-#define GPIO_AF14 0xe
-#define GPIO_AF15 0xf
-
-/* Note: EXTI source selection is now in the SYSCFG peripheral. */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-/*
- * Note: The F2 series has a completely new GPIO peripheral with different
- * configuration options. Here we implement a different API partly to more
- * closely match the peripheral capabilities and also to deliberately break
- * compatibility with old F1 code so there is no confusion with similar
- * sounding functions that have very different functionality.
- */
-
-void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
-void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
-void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
-
-/* This part of the API is compatible with the F1 series ------------------- */
-void gpio_set(u32 gpioport, u16 gpios);
-void gpio_clear(u32 gpioport, u16 gpios);
-u16 gpio_get(u32 gpioport, u16 gpios);
-void gpio_toggle(u32 gpioport, u16 gpios);
-u16 gpio_port_read(u32 gpioport);
-void gpio_port_write(u32 gpioport, u16 data);
-void gpio_port_config_lock(u32 gpioport, u16 gpios);
-
-END_DECLS
+#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
index b7da9c6..9e0685f 100644
--- a/include/libopencm3/stm32/f4/gpio.h
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -1,8 +1,23 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx General Purpose I/O</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -20,263 +35,8 @@
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* GPIO port base addresses (for convenience) */
-#define GPIOA GPIO_PORT_A_BASE
-#define GPIOB GPIO_PORT_B_BASE
-#define GPIOC GPIO_PORT_C_BASE
-#define GPIOD GPIO_PORT_D_BASE
-#define GPIOE GPIO_PORT_E_BASE
-#define GPIOF GPIO_PORT_F_BASE
-#define GPIOG GPIO_PORT_G_BASE
-#define GPIOH GPIO_PORT_H_BASE
-#define GPIOI GPIO_PORT_I_BASE
-
-/* GPIO number definitions (for convenience) */
-#define GPIO0 (1 << 0)
-#define GPIO1 (1 << 1)
-#define GPIO2 (1 << 2)
-#define GPIO3 (1 << 3)
-#define GPIO4 (1 << 4)
-#define GPIO5 (1 << 5)
-#define GPIO6 (1 << 6)
-#define GPIO7 (1 << 7)
-#define GPIO8 (1 << 8)
-#define GPIO9 (1 << 9)
-#define GPIO10 (1 << 10)
-#define GPIO11 (1 << 11)
-#define GPIO12 (1 << 12)
-#define GPIO13 (1 << 13)
-#define GPIO14 (1 << 14)
-#define GPIO15 (1 << 15)
-#define GPIO_ALL 0xffff
-
-/* --- GPIO registers ------------------------------------------------------ */
-
-/* Port mode register (GPIOx_MODER) */
-#define GPIO_MODER(port) MMIO32(port + 0x00)
-#define GPIOA_MODER GPIO_MODER(GPIOA)
-#define GPIOB_MODER GPIO_MODER(GPIOB)
-#define GPIOC_MODER GPIO_MODER(GPIOC)
-#define GPIOD_MODER GPIO_MODER(GPIOD)
-#define GPIOE_MODER GPIO_MODER(GPIOE)
-#define GPIOF_MODER GPIO_MODER(GPIOF)
-#define GPIOG_MODER GPIO_MODER(GPIOG)
-#define GPIOH_MODER GPIO_MODER(GPIOH)
-#define GPIOI_MODER GPIO_MODER(GPIOI)
-
-/* Port output type register (GPIOx_OTYPER) */
-#define GPIO_OTYPER(port) MMIO32(port + 0x04)
-#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
-#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
-#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
-#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
-#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
-#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
-#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
-#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
-#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
-
-/* Port output speed register (GPIOx_OSPEEDR) */
-#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
-#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
-#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
-#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
-#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
-#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
-#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
-#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
-#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
-#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
-
-/* Port pull-up/pull-down register (GPIOx_PUPDR) */
-#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
-#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
-#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
-#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
-#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
-#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
-#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
-#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
-#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
-#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
-
-/* Port input data register (GPIOx_IDR) */
-#define GPIO_IDR(port) MMIO32(port + 0x10)
-#define GPIOA_IDR GPIO_IDR(GPIOA)
-#define GPIOB_IDR GPIO_IDR(GPIOB)
-#define GPIOC_IDR GPIO_IDR(GPIOC)
-#define GPIOD_IDR GPIO_IDR(GPIOD)
-#define GPIOE_IDR GPIO_IDR(GPIOE)
-#define GPIOF_IDR GPIO_IDR(GPIOF)
-#define GPIOG_IDR GPIO_IDR(GPIOG)
-#define GPIOH_IDR GPIO_IDR(GPIOH)
-#define GPIOI_IDR GPIO_IDR(GPIOI)
-
-/* Port output data register (GPIOx_ODR) */
-#define GPIO_ODR(port) MMIO32(port + 0x14)
-#define GPIOA_ODR GPIO_ODR(GPIOA)
-#define GPIOB_ODR GPIO_ODR(GPIOB)
-#define GPIOC_ODR GPIO_ODR(GPIOC)
-#define GPIOD_ODR GPIO_ODR(GPIOD)
-#define GPIOE_ODR GPIO_ODR(GPIOE)
-#define GPIOF_ODR GPIO_ODR(GPIOF)
-#define GPIOG_ODR GPIO_ODR(GPIOG)
-#define GPIOH_ODR GPIO_ODR(GPIOH)
-#define GPIOI_ODR GPIO_ODR(GPIOI)
-
-/* Port bit set/reset register (GPIOx_BSRR) */
-#define GPIO_BSRR(port) MMIO32(port + 0x18)
-#define GPIOA_BSRR GPIO_BSRR(GPIOA)
-#define GPIOB_BSRR GPIO_BSRR(GPIOB)
-#define GPIOC_BSRR GPIO_BSRR(GPIOC)
-#define GPIOD_BSRR GPIO_BSRR(GPIOD)
-#define GPIOE_BSRR GPIO_BSRR(GPIOE)
-#define GPIOF_BSRR GPIO_BSRR(GPIOF)
-#define GPIOG_BSRR GPIO_BSRR(GPIOG)
-#define GPIOH_BSRR GPIO_BSRR(GPIOH)
-#define GPIOI_BSRR GPIO_BSRR(GPIOI)
-
-/* Port configuration lock register (GPIOx_LCKR) */
-#define GPIO_LCKR(port) MMIO32(port + 0x1c)
-#define GPIOA_LCKR GPIO_LCKR(GPIOA)
-#define GPIOB_LCKR GPIO_LCKR(GPIOB)
-#define GPIOC_LCKR GPIO_LCKR(GPIOC)
-#define GPIOD_LCKR GPIO_LCKR(GPIOD)
-#define GPIOE_LCKR GPIO_LCKR(GPIOE)
-#define GPIOF_LCKR GPIO_LCKR(GPIOF)
-#define GPIOG_LCKR GPIO_LCKR(GPIOG)
-#define GPIOH_LCKR GPIO_LCKR(GPIOH)
-#define GPIOI_LCKR GPIO_LCKR(GPIOI)
-
-/* Alternate function low register (GPIOx_AFRL) */
-#define GPIO_AFRL(port) MMIO32(port + 0x20)
-#define GPIOA_AFRL GPIO_AFRL(GPIOA)
-#define GPIOB_AFRL GPIO_AFRL(GPIOB)
-#define GPIOC_AFRL GPIO_AFRL(GPIOC)
-#define GPIOD_AFRL GPIO_AFRL(GPIOD)
-#define GPIOE_AFRL GPIO_AFRL(GPIOE)
-#define GPIOF_AFRL GPIO_AFRL(GPIOF)
-#define GPIOG_AFRL GPIO_AFRL(GPIOG)
-#define GPIOH_AFRL GPIO_AFRL(GPIOH)
-#define GPIOI_AFRL GPIO_AFRL(GPIOI)
-
-/* Alternate function high register (GPIOx_AFRH) */
-#define GPIO_AFRH(port) MMIO32(port + 0x24)
-#define GPIOA_AFRH GPIO_AFRH(GPIOA)
-#define GPIOB_AFRH GPIO_AFRH(GPIOB)
-#define GPIOC_AFRH GPIO_AFRH(GPIOC)
-#define GPIOD_AFRH GPIO_AFRH(GPIOD)
-#define GPIOE_AFRH GPIO_AFRH(GPIOE)
-#define GPIOF_AFRH GPIO_AFRH(GPIOF)
-#define GPIOG_AFRH GPIO_AFRH(GPIOG)
-#define GPIOH_AFRH GPIO_AFRH(GPIOH)
-#define GPIOI_AFRH GPIO_AFRH(GPIOI)
-
-/* --- GPIOx_MODER values -------------------------------------------------- */
-
-#define GPIO_MODE(n, mode) (mode << (2 * (n)))
-#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_MODE_INPUT 0x0
-#define GPIO_MODE_OUTPUT 0x1
-#define GPIO_MODE_AF 0x2
-#define GPIO_MODE_ANALOG 0x3
-
-/* --- GPIOx_OTYPER values ------------------------------------------------- */
-
-#define GPIO_OTYPE_PP 0x0
-#define GPIO_OTYPE_OD 0x1
-
-/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
-
-#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
-#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_OSPEED_2MHZ 0x0
-#define GPIO_OSPEED_25MHZ 0x1
-#define GPIO_OSPEED_50MHZ 0x2
-#define GPIO_OSPEED_100MHZ 0x3
-
-/* --- GPIOx_PUPDR values -------------------------------------------------- */
-
-#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
-#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
-#define GPIO_PUPD_NONE 0x0
-#define GPIO_PUPD_PULLUP 0x1
-#define GPIO_PUPD_PULLDOWN 0x2
-
-/* --- GPIOx_IDR values ---------------------------------------------------- */
-
-/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
-
-/* --- GPIOx_ODR values ---------------------------------------------------- */
-
-/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
-
-/* --- GPIOx_BSRR values --------------------------------------------------- */
-
-/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
-/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
-
-/* --- GPIOx_LCKR values --------------------------------------------------- */
-
-#define GPIO_LCKK (1 << 16)
-/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
-
-/* --- GPIOx_AFRL/H values ------------------------------------------------- */
-
-/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
-/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
-
-#define GPIO_AFR(n, af) (af << ((n) * 4))
-#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
-#define GPIO_AF0 0x0
-#define GPIO_AF1 0x1
-#define GPIO_AF2 0x2
-#define GPIO_AF3 0x3
-#define GPIO_AF4 0x4
-#define GPIO_AF5 0x5
-#define GPIO_AF6 0x6
-#define GPIO_AF7 0x7
-#define GPIO_AF8 0x8
-#define GPIO_AF9 0x9
-#define GPIO_AF10 0xa
-#define GPIO_AF11 0xb
-#define GPIO_AF12 0xc
-#define GPIO_AF13 0xd
-#define GPIO_AF14 0xe
-#define GPIO_AF15 0xf
-
-/* Note: EXTI source selection is now in the SYSCFG peripheral. */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-/*
- * Note: The F4 series has a completely new GPIO peripheral with different
- * configuration options. Here we implement a different API partly to more
- * closely match the peripheral capabilities and also to deliberately break
- * compatibility with old F1 code so there is no confusion with similar
- * sounding functions that have very different functionality.
- */
-
-void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
-void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
-void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
-
-/* This part of the API is compatible with the F1 series ------------------- */
-void gpio_set(u32 gpioport, u16 gpios);
-void gpio_clear(u32 gpioport, u16 gpios);
-u16 gpio_get(u32 gpioport, u16 gpios);
-void gpio_toggle(u32 gpioport, u16 gpios);
-u16 gpio_port_read(u32 gpioport);
-void gpio_port_write(u32 gpioport, u16 data);
-void gpio_port_config_lock(u32 gpioport, u16 gpios);
-
-END_DECLS
+#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/syscfg.h b/include/libopencm3/stm32/f4/syscfg.h
deleted file mode 100644
index 7426f16..0000000
--- a/include/libopencm3/stm32/f4/syscfg.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_SYSCFG_H
-#define LIBOPENCM3_SYSCFG_H
-
-#include <libopencm3/stm32/memorymap.h>
-
-/* --- SYSCFG registers ------------------------------------------------------ */
-
-#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)
-
-#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
-
-/* External interrupt configuration register 1 (SYSCFG_EXTICR1) */
-#define SYSCFG_EXTICR1 MMIO32(SYSCFG_BASE + 0x08)
-
-/* External interrupt configuration register 2 (SYSCFG_EXTICR2) */
-#define SYSCFG_EXTICR2 MMIO32(SYSCFG_BASE + 0x0c)
-
-/* External interrupt configuration register 3 (SYSCFG_EXTICR3) */
-#define SYSCFG_EXTICR3 MMIO32(SYSCFG_BASE + 0x10)
-
-/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
-#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
-
-#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
-
-#endif
-
diff --git a/include/libopencm3/stm32/gpio.h b/include/libopencm3/stm32/gpio.h
new file mode 100644
index 0000000..c106a09
--- /dev/null
+++ b/include/libopencm3/stm32/gpio.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32F subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/gpio.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/gpio.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/gpio.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/gpio.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index a59c420..1b2dc0e 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -321,7 +321,14 @@ LGPL License Terms @ref lgpl_license
#define I2C_CCR_FS (1 << 15)
/* DUTY: Fast Mode Duty Cycle */
+/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
+@ingroup i2c_defines
+
+@{*/
#define I2C_CCR_DUTY (1 << 14)
+#define I2C_CCR_DUTY_DIV2 0
+#define I2C_CCR_DUTY_16_DIV_9 1
+/**@}*/
/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
@@ -359,6 +366,7 @@ void i2c_peripheral_enable(u32 i2c);
void i2c_peripheral_disable(u32 i2c);
void i2c_send_start(u32 i2c);
void i2c_send_stop(u32 i2c);
+void i2c_clear_stop(u32 i2c);
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
void i2c_set_fast_mode(u32 i2c);
@@ -368,6 +376,18 @@ void i2c_set_ccr(u32 i2c, u16 freq);
void i2c_set_trise(u32 i2c, u16 trise);
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
void i2c_send_data(u32 i2c, u8 data);
+uint8_t i2c_get_data(u32 i2c);
+void i2c_enable_interrupt(u32 i2c, u32 interrupt);
+void i2c_disable_interrupt(u32 i2c, u32 interrupt);
+void i2c_enable_ack(u32 i2c);
+void i2c_disable_ack(u32 i2c);
+void i2c_nack_next(u32 i2c);
+void i2c_nack_current(u32 i2c);
+void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
+void i2c_enable_dma(u32 i2c);
+void i2c_disable_dma(u32 i2c);
+void i2c_set_dma_last_transfer(u32 i2c);
+void i2c_clear_dma_last_transfer(u32 i2c);
END_DECLS
diff --git a/include/libopencm3/stm32/l1/doc-stm32l1.h b/include/libopencm3/stm32/l1/doc-stm32l1.h
new file mode 100644
index 0000000..96bea00
--- /dev/null
+++ b/include/libopencm3/stm32/l1/doc-stm32l1.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 STM32L1
+
+@version 1.0.0
+
+@date 12 November 2012
+
+API documentation for ST Microelectronics STM32L1 Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32L1xx STM32L1xx
+Libraries for ST Microelectronics STM32L1xx series.
+
+@version 1.0.0
+
+@date 12 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32L1xx_defines STM32L1xx Defines
+
+@brief Defined Constants and Types for the STM32L1xx series
+
+@version 1.0.0
+
+@date 12 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h
new file mode 100644
index 0000000..93850a2
--- /dev/null
+++ b/include/libopencm3/stm32/l1/gpio.h
@@ -0,0 +1,266 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx General Purpose I/O</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/gpio_common_all.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+/* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup gpio_defines
+
+@{*/
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOH GPIO_PORT_H_BASE
+/**@}*/
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* Port mode register (GPIOx_MODER) */
+#define GPIO_MODER(port) MMIO32(port + 0x00)
+#define GPIOA_MODER GPIO_MODER(GPIOA)
+#define GPIOB_MODER GPIO_MODER(GPIOB)
+#define GPIOC_MODER GPIO_MODER(GPIOC)
+#define GPIOD_MODER GPIO_MODER(GPIOD)
+#define GPIOE_MODER GPIO_MODER(GPIOE)
+#define GPIOH_MODER GPIO_MODER(GPIOH)
+
+/* Port output type register (GPIOx_OTYPER) */
+#define GPIO_OTYPER(port) MMIO32(port + 0x04)
+#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
+#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
+#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
+#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
+#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
+#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
+
+/* Port output speed register (GPIOx_OSPEEDR) */
+#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
+#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
+#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
+#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
+#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
+#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
+#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
+
+/* Port pull-up/pull-down register (GPIOx_PUPDR) */
+#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
+#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
+#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
+#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
+#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
+#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
+#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x10)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOH_IDR GPIO_IDR(GPIOH)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x14)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOH_ODR GPIO_ODR(GPIOH)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x18)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOH_BSRR GPIO_BSRR(GPIOH)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x1C)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOH_LCKR GPIO_LCKR(GPIOH)
+
+/* Alternate function low register (GPIOx_AFRL) */
+#define GPIO_AFRL(port) MMIO32(port + 0x20)
+#define GPIOA_AFRL GPIO_AFRL(GPIOA)
+#define GPIOB_AFRL GPIO_AFRL(GPIOB)
+#define GPIOC_AFRL GPIO_AFRL(GPIOC)
+#define GPIOD_AFRL GPIO_AFRL(GPIOD)
+#define GPIOE_AFRL GPIO_AFRL(GPIOE)
+#define GPIOH_AFRL GPIO_AFRL(GPIOH)
+
+/* Alternate function high register (GPIOx_AFRH) */
+#define GPIO_AFRH(port) MMIO32(port + 0x24)
+#define GPIOA_AFRH GPIO_AFRH(GPIOA)
+#define GPIOB_AFRH GPIO_AFRH(GPIOB)
+#define GPIOC_AFRH GPIO_AFRH(GPIOC)
+#define GPIOD_AFRH GPIO_AFRH(GPIOD)
+#define GPIOE_AFRH GPIO_AFRH(GPIOE)
+#define GPIOH_AFRH GPIO_AFRH(GPIOH)
+
+/* --- GPIOx_MODER values-------------------------------------------- */
+
+#define GPIO_MODE(n, mode) (mode << (2 * (n)))
+#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode
+@ingroup gpio_defines
+@{*/
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT 0x01
+#define GPIO_MODE_AF 0x02
+#define GPIO_MODE_ANALOG 0x03
+/**@}*/
+
+/* --- GPIOx_OTYPER values -------------------------------------------- */
+/* Output type (OTx values) */
+/** @defgroup gpio_output_type GPIO Output Pin Driver Type
+@ingroup gpio_defines
+@list Push Pull
+@list Open Drain
+@{*/
+#define GPIO_OTYPE_PP 0x0
+#define GPIO_OTYPE_OD 0x1
+/**@}*/
+
+/* Output speed values */
+#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
+#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_speed GPIO Output Pin Speed
+@ingroup gpio_defines
+@{*/
+#define GPIO_OSPEED_400KHZ 0x0
+#define GPIO_OSPEED_2MHZ 0x1
+#define GPIO_OSPEED_10MHZ 0x2
+#define GPIO_OSPEED_40MHZ 0x3
+/**@}*/
+
+/* --- GPIOx_PUPDR values ------------------------------------------- */
+
+#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
+#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
+/** @defgroup gpio_pup GPIO Output Pin Pullup
+@ingroup gpio_defines
+@{*/
+#define GPIO_PUPD_NONE 0x0
+#define GPIO_PUPD_PULLUP 0x1
+#define GPIO_PUPD_PULLDOWN 0x2
+/**@}*/
+
+/* --- GPIO_IDR values ----------------------------------------------------- */
+
+/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIO_ODR values ----------------------------------------------------- */
+
+/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIO_BSRR values ---------------------------------------------------- */
+
+/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIO_LCKR values ---------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- GPIOx_AFRL/H values ------------------------------------------------- */
+
+/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
+/* See datasheet table 5, page 35 for the definitions */
+
+#define GPIO_AFR(n, af) (af << ((n) * 4))
+#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
+/** @defgroup gpio_af_num Alternate Function Pin Selection
+@ingroup gpio_defines
+@{*/
+#define GPIO_AF0 0x0
+#define GPIO_AF1 0x1
+#define GPIO_AF2 0x2
+#define GPIO_AF3 0x3
+#define GPIO_AF4 0x4
+#define GPIO_AF5 0x5
+#define GPIO_AF6 0x6
+#define GPIO_AF7 0x7
+#define GPIO_AF8 0x8
+#define GPIO_AF9 0x9
+#define GPIO_AF10 0xa
+#define GPIO_AF11 0xb
+#define GPIO_AF12 0xc
+#define GPIO_AF13 0xd
+#define GPIO_AF14 0xe
+#define GPIO_AF15 0xf
+/**@}*/
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+/*
+ * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style
+ * however the number of ports is reduced and H port naming is different.
+ * TODO: this should all really be moved to a "common" gpio header
+ */
+
+void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
+void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
+void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/l1/irq.yaml b/include/libopencm3/stm32/l1/irq.yaml
new file mode 100644
index 0000000..c2f118f
--- /dev/null
+++ b/include/libopencm3/stm32/l1/irq.yaml
@@ -0,0 +1,49 @@
+includeguard: LIBOPENCM3_STM32_L1_NVIC_H
+partname_humanreadable: STM32 L1 series
+partname_doxygen: STM32L1
+irqs:
+ - wwdg
+ - pvd
+ - tamper
+ - rtc
+ - flash
+ - rcc
+ - exti0
+ - exti1
+ - exti2
+ - exti3
+ - exti4
+ - dma1_channel1
+ - dma1_channel2
+ - dma1_channel3
+ - dma1_channel4
+ - dma1_channel5
+ - dma1_channel6
+ - dma1_channel7
+ - adc1
+ - usb_hp
+ - usb_lp
+ - dac
+ - comp
+ - exti9_5
+ - lcd
+ - tim9
+ - tim10
+ - tim11
+ - tim2
+ - tim3
+ - tim4
+ - i2c1_ev
+ - i2c1_er
+ - i2c2_ev
+ - i2c2_er
+ - spi1
+ - spi2
+ - usart1
+ - usart2
+ - usart3
+ - exti15_10
+ - rtc_alarm
+ - usb_wakeup
+ - tim6
+ - tim7
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
new file mode 100644
index 0000000..950dd18
--- /dev/null
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE ((u32)0x40000000)
+#define INFO_BASE ((u32)0x1ff00000)
+#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
+#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
+#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
+#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
+#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
+#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
+#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)
+#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
+/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
+#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
+// datasheet has an error? here
+#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
+/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
+#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
+#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
+#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
+#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000)
+#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
+#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
+#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
+/* gap */
+#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
+#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
+
+/* APB2 */
+#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
+#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
+#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800)
+#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00)
+#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000)
+/* gap */
+#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400)
+/* gap */
+#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00)
+#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
+/* gap */
+#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
+
+/* AHB */
+#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000)
+#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400)
+#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800)
+#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
+#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
+#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
+/* gap */
+#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
+/* gap */
+#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
+#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
+/* gap */
+#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
+
+/* PPIB */
+#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
+
+/* FSMC */
+#define FSMC_BASE (PERIPH_BASE + 0x60000000)
+/* AES */
+#define AES_BASE (PERIPH_BASE + 0x10000000)
+
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
+#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
+
+#endif
diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h
new file mode 100644
index 0000000..d888d7c
--- /dev/null
+++ b/include/libopencm3/stm32/l1/rcc.h
@@ -0,0 +1,404 @@
+/** @defgroup STM32L1xx_rcc_defines RCC Defines
+
+@ingroup STM32L1xx_defines
+
+@brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 11 November 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Originally based on the F1 code, as it seemed most similar to the L1
+ * TODO: very incomplete still!
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_RCC_H
+#define LIBOPENCM3_RCC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- RCC registers ------------------------------------------------------- */
+
+#define RCC_CR MMIO32(RCC_BASE + 0x00)
+#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
+#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
+#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
+#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)
+#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)
+#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)
+#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)
+#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)
+#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)
+#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)
+#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)
+#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)
+#define RCC_CSR MMIO32(RCC_BASE + 0x34)
+
+/* --- RCC_CR values ------------------------------------------------------- */
+
+/* RTCPRE[1:0] at 30:29 */
+#define RCC_CR_CSSON (1 << 28)
+#define RCC_CR_PLLRDY (1 << 25)
+#define RCC_CR_PLLON (1 << 24)
+#define RCC_CR_HSEBYP (1 << 18)
+#define RCC_CR_HSERDY (1 << 17)
+#define RCC_CR_HSEON (1 << 16)
+#define RCC_CR_MSIRDY (1 << 9)
+#define RCC_CR_MSION (1 << 8)
+#define RCC_CR_HSIRDY (1 << 1)
+#define RCC_CR_HSION (1 << 0)
+
+#define RCC_CR_RTCPRE_DIV2 0
+#define RCC_CR_RTCPRE_DIV4 1
+#define RCC_CR_RTCPRE_DIV8 2
+#define RCC_CR_RTCPRE_DIV18 3
+
+/* --- RCC_ICSCR values ---------------------------------------------------- */
+
+// TODO
+
+/* --- RCC_CFGR values ----------------------------------------------------- */
+
+/* MCOPRE */
+#define RCC_CFGR_MCOPRE_DIV1 0
+#define RCC_CFGR_MCOPRE_DIV2 1
+#define RCC_CFGR_MCOPRE_DIV4 2
+#define RCC_CFGR_MCOPRE_DIV8 3
+#define RCC_CFGR_MCOPRE_DIV16 4
+
+/* MCO: Microcontroller clock output */
+#define RCC_CFGR_MCO_NOCLK 0x0
+#define RCC_CFGR_MCO_SYSCLK 0x1
+#define RCC_CFGR_MCO_HSICLK 0x2
+#define RCC_CFGR_MCO_MSICLK 0x3
+#define RCC_CFGR_MCO_HSECLK 0x4
+#define RCC_CFGR_MCO_PLLCLK 0x5
+#define RCC_CFGR_MCO_LSICLK 0x6
+#define RCC_CFGR_MCO_LSECLK 0x7
+
+/* PLL Output division selection */
+#define RCC_CFGR_PLLDIV_DIV2 0x1
+#define RCC_CFGR_PLLDIV_DIV3 0x2
+#define RCC_CFGR_PLLDIV_DIV4 0x3
+
+/* PLLMUL: PLL multiplication factor */
+#define RCC_CFGR_PLLMUL_MUL3 0x0
+#define RCC_CFGR_PLLMUL_MUL4 0x1
+#define RCC_CFGR_PLLMUL_MUL6 0x2
+#define RCC_CFGR_PLLMUL_MUL8 0x3
+#define RCC_CFGR_PLLMUL_MUL12 0x4
+#define RCC_CFGR_PLLMUL_MUL16 0x5
+#define RCC_CFGR_PLLMUL_MUL24 0x6
+#define RCC_CFGR_PLLMUL_MUL32 0x7
+#define RCC_CFGR_PLLMUL_MUL48 0x8
+
+/* PLLSRC: PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
+#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
+
+/* PPRE2: APB high-speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+
+/* PPRE1: APB low-speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+
+/* HPRE: AHB prescaler */
+#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
+#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
+#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
+#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
+#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
+#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
+#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
+#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
+#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+
+/* SWS: System clock switch status */
+#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
+#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
+#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
+#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
+
+/* SW: System clock switch */
+#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0
+#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
+#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
+#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
+
+/* --- RCC_CIR values ------------------------------------------------------ */
+
+/* Clock security system interrupt clear bit */
+#define RCC_CIR_CSSC (1 << 23)
+
+/* OSC ready interrupt clear bits */
+#define RCC_CIR_MSIRDYC (1 << 21)
+#define RCC_CIR_PLLRDYC (1 << 20)
+#define RCC_CIR_HSERDYC (1 << 19)
+#define RCC_CIR_HSIRDYC (1 << 18)
+#define RCC_CIR_LSERDYC (1 << 17)
+#define RCC_CIR_LSIRDYC (1 << 16)
+
+/* OSC ready interrupt enable bits */
+#define RCC_CIR_MSIRDYIE (1 << 13)
+#define RCC_CIR_PLLRDYIE (1 << 12)
+#define RCC_CIR_HSERDYIE (1 << 11)
+#define RCC_CIR_HSIRDYIE (1 << 10)
+#define RCC_CIR_LSERDYIE (1 << 9)
+#define RCC_CIR_LSIRDYIE (1 << 8)
+
+/* Clock security system interrupt flag bit */
+#define RCC_CIR_CSSF (1 << 7)
+
+/* OSC ready interrupt flag bits */
+#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */
+#define RCC_CIR_PLLRDYF (1 << 4)
+#define RCC_CIR_HSERDYF (1 << 3)
+#define RCC_CIR_HSIRDYF (1 << 2)
+#define RCC_CIR_LSERDYF (1 << 1)
+#define RCC_CIR_LSIRDYF (1 << 0)
+
+/* --- RCC_AHBRSTR values ------------------------------------------------- */
+#define RCC_AHBRSTR_DMA1RST (1 << 24)
+#define RCC_AHBRSTR_FLITFRST (1 << 15)
+#define RCC_AHBRSTR_CRCRST (1 << 12)
+#define RCC_AHBRSTR_GPIOHRST (1 << 5)
+#define RCC_AHBRSTR_GPIOERST (1 << 4)
+#define RCC_AHBRSTR_GPIODRST (1 << 3)
+#define RCC_AHBRSTR_GPIOCRST (1 << 2)
+#define RCC_AHBRSTR_GPIOBRST (1 << 1)
+#define RCC_AHBRSTR_GPIOARST (1 << 0)
+
+/* --- RCC_APB2RSTR values ------------------------------------------------- */
+
+#define RCC_APB2RSTR_USART1RST (1 << 14)
+#define RCC_APB2RSTR_SPI1RST (1 << 12)
+#define RCC_APB2RSTR_ADC1RST (1 << 9)
+#define RCC_APB2RSTR_TIM11RST (1 << 4)
+#define RCC_APB2RSTR_TIM10RST (1 << 3)
+#define RCC_APB2RSTR_TIM9RST (1 << 2)
+#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
+
+/* --- RCC_APB1RSTR values ------------------------------------------------- */
+
+#define RCC_APB1RSTR_COMPRST (1 << 31)
+#define RCC_APB1RSTR_DACRST (1 << 29)
+#define RCC_APB1RSTR_PWRRST (1 << 28)
+#define RCC_APB1RSTR_USBRST (1 << 23)
+#define RCC_APB1RSTR_I2C2RST (1 << 22)
+#define RCC_APB1RSTR_I2C1RST (1 << 21)
+#define RCC_APB1RSTR_USART3RST (1 << 18)
+#define RCC_APB1RSTR_USART2RST (1 << 17)
+#define RCC_APB1RSTR_SPI2RST (1 << 14)
+#define RCC_APB1RSTR_WWDGRST (1 << 11)
+#define RCC_APB1RSTR_LCDRST (1 << 9)
+#define RCC_APB1RSTR_TIM7RST (1 << 5)
+#define RCC_APB1RSTR_TIM6RST (1 << 4)
+#define RCC_APB1RSTR_TIM4RST (1 << 2)
+#define RCC_APB1RSTR_TIM3RST (1 << 1)
+#define RCC_APB1RSTR_TIM2RST (1 << 0)
+
+/* --- RCC_AHBENR values --------------------------------------------------- */
+
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_AHBENR_DMA1EN (1 << 24)
+#define RCC_AHBENR_FLITFEN (1 << 15)
+#define RCC_AHBENR_CRCEN (1 << 12)
+#define RCC_AHBENR_GPIOHEN (1 << 5)
+#define RCC_AHBENR_GPIOEEN (1 << 4)
+#define RCC_AHBENR_GPIODEN (1 << 3)
+#define RCC_AHBENR_GPIOCEN (1 << 2)
+#define RCC_AHBENR_GPIOBEN (1 << 1)
+#define RCC_AHBENR_GPIOAEN (1 << 0)
+/*@}*/
+
+/* --- RCC_APB2ENR values -------------------------------------------------- */
+
+/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_APB2ENR_USART1EN (1 << 14)
+#define RCC_APB2ENR_SPI1EN (1 << 12)
+#define RCC_APB2ENR_ADC1EN (1 << 9)
+#define RCC_APB2ENR_TIM11EN (1 << 4)
+#define RCC_APB2ENR_TIM10EN (1 << 3)
+#define RCC_APB2ENR_TIM9EN (1 << 2)
+#define RCC_APB2ENR_SYSCFGEN (1 << 0)
+/*@}*/
+
+/* --- RCC_APB1ENR values -------------------------------------------------- */
+
+/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
+@ingroup STM32L1xx_rcc_defines
+
+@{*/
+#define RCC_APB1ENR_COMPEN (1 << 31)
+#define RCC_APB1ENR_DACEN (1 << 29)
+#define RCC_APB1ENR_PWREN (1 << 28)
+#define RCC_APB1ENR_USBEN (1 << 23)
+#define RCC_APB1ENR_I2C2EN (1 << 22)
+#define RCC_APB1ENR_I2C1EN (1 << 21)
+#define RCC_APB1ENR_USART3EN (1 << 18)
+#define RCC_APB1ENR_USART2EN (1 << 17)
+#define RCC_APB1ENR_SPI2EN (1 << 14)
+#define RCC_APB1ENR_WWDGEN (1 << 11)
+#define RCC_APB1ENR_LCDEN (1 << 9)
+#define RCC_APB1ENR_TIM7EN (1 << 5)
+#define RCC_APB1ENR_TIM6EN (1 << 4)
+#define RCC_APB1ENR_TIM4EN (1 << 2)
+#define RCC_APB1ENR_TIM3EN (1 << 1)
+#define RCC_APB1ENR_TIM2EN (1 << 0)
+/*@}*/
+
+/* --- RCC_AHBLPENR -------------------------------------------------------- */
+#define RCC_AHBLPENR_DMA1LPEN (1 << 24)
+#define RCC_AHBLPENR_SRAMLPEN (1 << 16)
+#define RCC_AHBLPENR_FLITFLPEN (1 << 15)
+#define RCC_AHBLPENR_CRCLPEN (1 << 12)
+#define RCC_AHBLPENR_GPIOHLPEN (1 << 5)
+#define RCC_AHBLPENR_GPIOELPEN (1 << 4)
+#define RCC_AHBLPENR_GPIODLPEN (1 << 3)
+#define RCC_AHBLPENR_GPIOCLPEN (1 << 2)
+#define RCC_AHBLPENR_GPIOBLPEN (1 << 1)
+#define RCC_AHBLPENR_GPIOALPEN (1 << 0)
+
+#define RCC_APB2LPENR_USART1LPEN (1 << 14)
+#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
+#define RCC_APB2LPENR_ADC1LPEN (1 << 9)
+#define RCC_APB2LPENR_TIM11LPEN (1 << 4)
+#define RCC_APB2LPENR_TIM10LPEN (1 << 3)
+#define RCC_APB2LPENR_TIM9LPEN (1 << 2)
+#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0)
+
+#define RCC_APB1LPENR_COMPLPEN (1 << 31)
+#define RCC_APB1LPENR_DACLPEN (1 << 29)
+#define RCC_APB1LPENR_PWRLPEN (1 << 28)
+#define RCC_APB1LPENR_USBLPEN (1 << 23)
+#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
+#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
+#define RCC_APB1LPENR_USART3LPEN (1 << 18)
+#define RCC_APB1LPENR_USART2LPEN (1 << 17)
+#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
+#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
+#define RCC_APB1LPENR_LCDLPEN (1 << 9)
+#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
+#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
+#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
+#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
+#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
+
+
+/* --- RCC_CSR values ------------------------------------------------------ */
+
+#define RCC_CSR_LPWRRSTF (1 << 31)
+#define RCC_CSR_WWDGRSTF (1 << 30)
+#define RCC_CSR_IWDGRSTF (1 << 29)
+#define RCC_CSR_SFTRSTF (1 << 28)
+#define RCC_CSR_PORRSTF (1 << 27)
+#define RCC_CSR_PINRSTF (1 << 26)
+#define RCC_CSR_OBLRSTF (1 << 25)
+#define RCC_CSR_RMVF (1 << 24)
+#define RCC_CSR_RTCRST (1 << 23)
+#define RCC_CSR_RTCEN (1 << 22)
+/* RTCSEL[1:0] */
+#define RCC_CSR_LSEBYP (1 << 10)
+#define RCC_CSR_LSERDY (1 << 9)
+#define RCC_CSR_LSEON (1 << 8)
+#define RCC_CSR_LSIRDY (1 << 1)
+#define RCC_CSR_LSION (1 << 0)
+
+
+/* --- Variable definitions ------------------------------------------------ */
+extern u32 rcc_ppre1_frequency;
+extern u32 rcc_ppre2_frequency;
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ PLL, HSE, HSI, MSI, LSE, LSI
+} osc_t;
+
+void rcc_osc_ready_int_clear(osc_t osc);
+void rcc_osc_ready_int_enable(osc_t osc);
+void rcc_osc_ready_int_disable(osc_t osc);
+int rcc_osc_ready_int_flag(osc_t osc);
+void rcc_css_int_clear(void);
+int rcc_css_int_flag(void);
+void rcc_wait_for_osc_ready(osc_t osc);
+void rcc_osc_on(osc_t osc);
+void rcc_osc_off(osc_t osc);
+void rcc_css_enable(void);
+void rcc_css_disable(void);
+void rcc_osc_bypass_enable(osc_t osc);
+void rcc_osc_bypass_disable(osc_t osc);
+void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
+void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
+void rcc_set_sysclk_source(u32 clk);
+void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll_source(u32 pllsrc);
+void rcc_set_pllxtpre(u32 pllxtpre);
+void rcc_set_adcpre(u32 adcpre);
+void rcc_set_ppre2(u32 ppre2);
+void rcc_set_ppre1(u32 ppre1);
+void rcc_set_hpre(u32 hpre);
+void rcc_set_usbpre(u32 usbpre);
+u32 rcc_get_system_clock_source(int i);
+void rcc_clock_setup_in_hsi_out_64mhz(void);
+void rcc_clock_setup_in_hsi_out_48mhz(void);
+
+/**
+ * Maximum speed possible for F100 (Value Line) on HSI
+ */
+void rcc_clock_setup_in_hsi_out_24mhz(void);
+void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
+void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_backupdomain_reset(void);
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h
index 6f213da..9b757ce 100644
--- a/include/libopencm3/stm32/memorymap.h
+++ b/include/libopencm3/stm32/memorymap.h
@@ -26,6 +26,8 @@
# include <libopencm3/stm32/f2/memorymap.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/memorymap.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/memorymap.h>
#else
# error "stm32 family not defined."
#endif
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
index e709f3d..34b2407 100644
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -1,4 +1,4 @@
-/** @defgroup STM32F1xx_pwr_defines PWR Defines
+/** @defgroup STM32F_pwr_defines PWR Defines
@ingroup STM32F_defines
diff --git a/include/libopencm3/stm32/f2/syscfg.h b/include/libopencm3/stm32/syscfg.h
index 7426f16..7426f16 100644
--- a/include/libopencm3/stm32/f2/syscfg.h
+++ b/include/libopencm3/stm32/syscfg.h