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-rw-r--r--include/libopencm3/stm32/f4/doc-stm32f4.h32
-rw-r--r--include/libopencm3/stm32/f4/flash.h4
-rw-r--r--include/libopencm3/stm32/f4/gpio.h4
-rw-r--r--include/libopencm3/stm32/f4/pwr.h4
-rw-r--r--include/libopencm3/stm32/f4/rcc.h4
-rw-r--r--include/libopencm3/stm32/f4/scb.h74
-rw-r--r--include/libopencm3/stm32/f4/timer.h4
7 files changed, 126 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/f4/doc-stm32f4.h b/include/libopencm3/stm32/f4/doc-stm32f4.h
new file mode 100644
index 0000000..39d7091
--- /dev/null
+++ b/include/libopencm3/stm32/f4/doc-stm32f4.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 STM32F4
+
+@version 1.0.0
+
+@date 7 September 2012
+
+API documentation for ST Microelectronics STM32F4 Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F4xx STM32F4xx
+Libraries for ST Microelectronics STM32F4xx series.
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32F4xx_defines STM32F4xx Defines
+
+@brief Defined Constants and Types for the STM32F4xx series
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
index f85d56f..2221333 100644
--- a/include/libopencm3/stm32/f4/flash.h
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -115,6 +115,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void flash_dcache_enable(void);
void flash_dcache_disable(void);
void flash_icache_enable(void);
@@ -144,4 +146,6 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
index a5b4361..b7da9c6 100644
--- a/include/libopencm3/stm32/f4/gpio.h
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -254,6 +254,8 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
/*
* Note: The F4 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
@@ -275,4 +277,6 @@ u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
index ede1ae7..25fb163 100644
--- a/include/libopencm3/stm32/f4/pwr.h
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -63,6 +63,10 @@ typedef enum {
SCALE2,
} vos_scale_t;
+BEGIN_DECLS
+
void pwr_set_vos_scale(vos_scale_t scale);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 648ccb0..1688584 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -482,6 +482,8 @@ typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
+BEGIN_DECLS
+
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
@@ -512,4 +514,6 @@ u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h
index 12a74a2..7187ca9 100644
--- a/include/libopencm3/stm32/f4/scb.h
+++ b/include/libopencm3/stm32/f4/scb.h
@@ -72,6 +72,63 @@
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+/* ID_PFR0: Processor Feature Register 0 */
+#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
+
+/* ID_PFR1: Processor Feature Register 1 */
+#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
+
+/* ID_DFR0: Debug Features Register 0 */
+#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
+
+/* ID_AFR0: Auxiliary Features Register 0 */
+#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
+
+/* ID_MMFR0: Memory Model Feature Register 0 */
+#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
+
+/* ID_MMFR1: Memory Model Feature Register 1 */
+#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
+
+/* ID_MMFR2: Memory Model Feature Register 2 */
+#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
+
+/* ID_MMFR3: Memory Model Feature Register 3 */
+#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
+
+/* ID_ISAR0: Instruction Set Attributes Register 0 */
+#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
+
+/* ID_ISAR1: Instruction Set Attributes Register 1 */
+#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
+
+/* ID_ISAR2: Instruction Set Attributes Register 2 */
+#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
+
+/* ID_ISAR3: Instruction Set Attributes Register 3 */
+#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
+
+/* ID_ISAR4: Instruction Set Attributes Register 4 */
+#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
+
+/* CPACR: Coprocessor Access Control Register */
+#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
+
+/* FPCCR: Floating-Point Context Control Register */
+#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
+
+/* FPCAR: Floating-Point Context Address Register */
+#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
+
+/* FPDSCR: Floating-Point Default Status Control Register */
+#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
+
+/* MVFR0: Media and Floating-Point Feature Register 0 */
+#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
+
+/* MVFR1: Media and Floating-Point Feature Register 1 */
+#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
+
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
@@ -292,11 +349,28 @@
/* BFAR [31:0]: Bus fault address */
+/* --- SCB_CPACR values ---------------------------------------------------- */
+
+/* CPACR CPn: Access privileges values */
+#define SCB_CPACR_NONE 0 /* Access denied */
+#define SCB_CPACR_PRIV 1 /* Privileged access only */
+#define SCB_CPACR_FULL 3 /* Full access */
+
+/* CPACR [20:21]: Access privileges for coprocessor 10 */
+#define SCB_CPACR_CP10 (1 << 20)
+/* CPACR [22:23]: Access privileges for coprocessor 11 */
+#define SCB_CPACR_CP11 (1 << 22)
+
/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
+END_DECLS
+
#endif
diff --git a/include/libopencm3/stm32/f4/timer.h b/include/libopencm3/stm32/f4/timer.h
index 6d19990..988d02c 100644
--- a/include/libopencm3/stm32/f4/timer.h
+++ b/include/libopencm3/stm32/f4/timer.h
@@ -52,6 +52,10 @@
/* --- Function prototypes ------------------------------------------------- */
+BEGIN_DECLS
+
void timer_set_option(u32 timer_peripheral, u32 option);
+END_DECLS
+
#endif