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Diffstat (limited to 'include/libopencm3/lpc17xx')
-rw-r--r--include/libopencm3/lpc17xx/gpio.h22
-rw-r--r--include/libopencm3/lpc17xx/memorymap.h2
2 files changed, 12 insertions, 12 deletions
diff --git a/include/libopencm3/lpc17xx/gpio.h b/include/libopencm3/lpc17xx/gpio.h
index 15afd87..f35516d 100644
--- a/include/libopencm3/lpc17xx/gpio.h
+++ b/include/libopencm3/lpc17xx/gpio.h
@@ -110,27 +110,27 @@
/* GPIO interrupt register map */
/* Interrupt enable rising edge */
-#define GPIO0_IER MMIO32(GPIOINTERRPUT_BASE + 0x90)
-#define GPIO2_IER MMIO32(GPIOINTERRPUT_BASE + 0xB0)
+#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90)
+#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0)
/* Interrupt enable falling edge */
-#define GPIO0_IEF MMIO32(GPIOINTERRPUT_BASE + 0x94)
-#define GPIO2_IEF MMIO32(GPIOINTERRPUT_BASE + 0xB4)
+#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94)
+#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4)
/* Interrupt status rising edge */
-#define GPIO0_ISR MMIO32(GPIOINTERRPUT_BASE + 0x84)
-#define GPIO2_ISR MMIO32(GPIOINTERRPUT_BASE + 0xA4)
+#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84)
+#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4)
/* Interrupt status falling edge */
-#define GPIO0_ISF MMIO32(GPIOINTERRPUT_BASE + 0x88)
-#define GPIO2_ISF MMIO32(GPIOINTERRPUT_BASE + 0xA8)
+#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88)
+#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8)
/* Interrupt clear */
-#define GPIO0_IC MMIO32(GPIOINTERRPUT_BASE + 0x8C)
-#define GPIO1_IC MMIO32(GPIOINTERRPUT_BASE + 0xAC)
+#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C)
+#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC)
/* Overall interrupt status */
-#define GPIO_IS MMIO32(GPIOINTERRPUT_BASE + 0x80)
+#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80)
BEGIN_DECLS
diff --git a/include/libopencm3/lpc17xx/memorymap.h b/include/libopencm3/lpc17xx/memorymap.h
index 1114442..cbb2acb 100644
--- a/include/libopencm3/lpc17xx/memorymap.h
+++ b/include/libopencm3/lpc17xx/memorymap.h
@@ -42,7 +42,7 @@
#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
-#define GPIOINTERRPUT_BASE (PERIPH_BASE_APB0 + 0x28000)
+#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)