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-rw-r--r--README10
-rw-r--r--examples/lm4f/stellaris-ek-lm4f120xl/miniblink/README21
-rw-r--r--examples/lm4f/stellaris-ek-lm4f120xl/miniblink/miniblink.c193
-rw-r--r--examples/stm32/f1/other/rtc/rtc.c2
-rw-r--r--examples/stm32/f1/stm32vl-discovery/adc-dac-printf/Makefile24
-rw-r--r--examples/stm32/f1/stm32vl-discovery/adc-dac-printf/README17
-rw-r--r--examples/stm32/f1/stm32vl-discovery/adc-dac-printf/adc-dac-printf.c162
-rw-r--r--examples/stm32/f1/stm32vl-discovery/rtc/rtc.c2
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/Makefile24
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/README18
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/main.c300
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/syscfg.h61
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf/README32
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c224
-rw-r--r--examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h29
-rw-r--r--examples/stm32/l1/stm32l-discovery/usart/usart.c88
-rw-r--r--include/libopencm3/lm4f/rcc.h126
-rw-r--r--include/libopencm3/lm4f/systemcontrol.h272
-rw-r--r--include/libopencm3/stm32/common/pwr_common_all.h119
-rw-r--r--include/libopencm3/stm32/common/rtc_common_bcd.h302
-rw-r--r--include/libopencm3/stm32/f1/dma.h2
-rw-r--r--include/libopencm3/stm32/f1/flash.h56
-rw-r--r--include/libopencm3/stm32/f1/pwr.h40
-rw-r--r--include/libopencm3/stm32/f1/rtc.h5
-rw-r--r--include/libopencm3/stm32/f2/dma.h2
-rw-r--r--include/libopencm3/stm32/f2/flash.h112
-rw-r--r--include/libopencm3/stm32/f2/rcc.h2
-rw-r--r--include/libopencm3/stm32/f2/rng.h2
-rw-r--r--include/libopencm3/stm32/f2/rtc.h39
-rw-r--r--include/libopencm3/stm32/f4/adc.h2
-rw-r--r--include/libopencm3/stm32/f4/dma.h2
-rw-r--r--include/libopencm3/stm32/f4/flash.h112
-rw-r--r--include/libopencm3/stm32/f4/pwr.h19
-rw-r--r--include/libopencm3/stm32/f4/rcc.h2
-rw-r--r--include/libopencm3/stm32/f4/rng.h2
-rw-r--r--include/libopencm3/stm32/f4/rtc.h39
-rw-r--r--include/libopencm3/stm32/l1/flash.h106
-rw-r--r--include/libopencm3/stm32/l1/irq.yaml19
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h7
-rw-r--r--include/libopencm3/stm32/l1/pwr.h25
-rw-r--r--include/libopencm3/stm32/l1/rcc.h47
-rw-r--r--include/libopencm3/stm32/l1/rtc.h39
-rw-r--r--include/libopencm3/stm32/pwr.h122
-rw-r--r--include/libopencm3/stm32/rtc.h31
-rw-r--r--lib/cm3/vector.c2
-rw-r--r--lib/lm4f/Makefile2
-rw-r--r--lib/lm4f/rcc.c493
-rw-r--r--lib/lm4f/systemcontrol.c40
-rw-r--r--lib/stm32/common/dma_common_f13.c4
-rw-r--r--lib/stm32/common/pwr_common_all.c217
-rw-r--r--lib/stm32/common/rtc_common_bcd.c78
-rw-r--r--lib/stm32/f1/Makefile2
-rw-r--r--lib/stm32/f1/flash.c63
-rw-r--r--lib/stm32/f1/rcc.c16
-rw-r--r--lib/stm32/f2/Makefile3
-rw-r--r--lib/stm32/f2/flash.c72
-rw-r--r--lib/stm32/f2/rcc.c2
-rw-r--r--lib/stm32/f2/rtc.c27
-rw-r--r--lib/stm32/f4/Makefile4
-rw-r--r--lib/stm32/f4/flash.c74
-rw-r--r--lib/stm32/f4/rcc.c4
-rw-r--r--lib/stm32/f4/rtc.c27
-rw-r--r--lib/stm32/l1/Makefile3
-rw-r--r--lib/stm32/l1/flash.c8
-rw-r--r--lib/stm32/l1/pwr.c (renamed from lib/stm32/l1/pwr_chipset.c)2
-rw-r--r--lib/stm32/l1/rcc.c81
-rw-r--r--lib/stm32/l1/rtc.c27
67 files changed, 3479 insertions, 632 deletions
diff --git a/README b/README
index 5d3e064..44cbeab 100644
--- a/README
+++ b/README
@@ -28,6 +28,16 @@ IMPORTANT: The API of the library is NOT yet considered stable! Please do
not rely on it, yet! Changes to function names, macro names etc.
can happen at any time without prior notice!
+Prerequisites
+-------------
+
+Building requires python, and a python YAML module. (Some code is generated)
+
+For Ubuntu
+ $ [sudo] apt-get install python-yaml
+
+For Fedora
+ $ [sudo] yum install PyYAML
Building
--------
diff --git a/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/README b/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/README
index f6441be..a19550d 100644
--- a/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/README
+++ b/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/README
@@ -2,8 +2,21 @@
README
------------------------------------------------------------------------------
-Flashes the Red, Green and Blue diodes on the board, in order.
-RED controlled by PF1
-Green controlled by PF3
-Blue controlled by PF2
+This example demonstrates the following:
+ * Configuriong GPIO pins
+ * Toggling GPIO pins
+ * Setting up and using GPIO interrupts
+ * Unlocking protected GPIO pins
+ * Controlling the system clock
+ * Changing the system clock on the fly
+
+Flashes the Red, Green and Blue diodes on the board, in order. The system clock
+starts at 80MHz.
+Pressing SW2 toggles the system clock between 80MHz, 57MHz, 40MHz ,20MHz, and
+16MHz by changing the PLL divisor.
+Pressing SW1 bypasses the PLL completely, and runs off the raw 16MHz clock
+provided by the external crystal oscillator.
+The LEDs will toggle at different speeds, depending on the system clock. The
+system clock changes are handled within the interrupt service routine.
+
diff --git a/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/miniblink.c b/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/miniblink.c
index 0231a90..d03be0c 100644
--- a/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/miniblink.c
+++ b/examples/lm4f/stellaris-ek-lm4f120xl/miniblink/miniblink.c
@@ -2,7 +2,7 @@
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
- * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Copyright (C) 2012-2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -27,66 +27,193 @@
* Green controlled by PF3
* Blue controlled by PF2
*/
+#include <libopencm3/cm3/nvic.h>
#include <libopencm3/lm4f/systemcontrol.h>
+#include <libopencm3/lm4f/rcc.h>
#include <libopencm3/lm4f/gpio.h>
+#include <libopencm3/lm4f/nvic.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+
+/* This is how the RGB LED is connected on the stellaris launchpad */
+#define RGB_PORT GPIOF
+enum {
+ LED_R = GPIO1,
+ LED_G = GPIO3,
+ LED_B = GPIO2,
+};
+
+/* This is how the user switches are connected to GPIOF */
+enum {
+ USR_SW1 = GPIO4,
+ USR_SW2 = GPIO0,
+};
+
+/* The divisors we loop through when the user presses SW2 */
+enum {
+ PLL_DIV_80MHZ = 5,
+ PLL_DIV_57MHZ = 7,
+ PLL_DIV_40MHZ = 10,
+ PLL_DIV_20MHZ = 20,
+ PLL_DIV_16MHZ = 25,
+};
+
+static const u8 plldiv[] = {
+ PLL_DIV_80MHZ,
+ PLL_DIV_57MHZ,
+ PLL_DIV_40MHZ,
+ PLL_DIV_20MHZ,
+ PLL_DIV_16MHZ,
+ 0
+};
+/* The PLL divisor we are currently on */
+static size_t ipll = 0;
+/* Are we bypassing the PLL, or not? */
+static bool bypass = false;
-void gpio_setup(void)
+/*
+ * Clock setup:
+ * Take the main crystal oscillator at 16MHz, run it through the PLL, and divide
+ * the 400MHz PLL clock to get a system clock of 80MHz.
+ */
+static void clock_setup(void)
+{
+ rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLL_DIV_80MHZ);
+}
+
+/*
+ * GPIO setup:
+ * Enable the pins driving the RGB LED as outputs.
+ */
+static void gpio_setup(void)
{
- SYSCTL_RCGCGPIO |= 0x20; /* Enable GPIOF in run mode. */
- const u32 outpins = ((1<<3) | (1<<2) | (1<<1));
+ /*
+ * Configure GPIOF
+ * This port is used to control the RGB LED
+ */
+ periph_clock_enable(RCC_GPIOF);
+ const u32 outpins = (LED_R | LED_G | LED_B);
+
+ GPIO_DIR(RGB_PORT) |= outpins; /* Configure outputs. */
+ GPIO_DEN(RGB_PORT) |= outpins; /* Enable digital function on outputs. */
+
+ /*
+ * Now take care of our buttons
+ */
+ const u32 btnpins = USR_SW1 | USR_SW2;
+
+ /*
+ * PF0 is locked by default. We need to unlock the GPIO_CR register,
+ * then enable PF0 commit. After we do this, we can setup PF0. If we
+ * don't do this, any configuration done to PF0 is lost, and we will not
+ * have a PF0 interrupt.
+ */
+ GPIO_LOCK(GPIOF) = 0x4C4F434B;
+ GPIO_CR(GPIOF) |= USR_SW2;
+
+ /* Configure pins as inputs. */
+ GPIO_DIR(GPIOF) &= ~btnpins;
+ /* Enable digital function on the pins. */
+ GPIO_DEN(GPIOF) |= btnpins;
+ /* Pull-up the pins. We don't have an external pull-up */
+ GPIO_PUR(GPIOF) |= btnpins;
+}
- GPIO_DIR(GPIOF) |= outpins; /* Configure outputs. */
- GPIO_DEN(GPIOF) |= outpins; /* Enable digital function on outputs. */
+/*
+ * IRQ setup:
+ * Trigger an interrupt whenever a button is depressed.
+ */
+static void irq_setup(void)
+{
+ const u32 btnpins = USR_SW1 | USR_SW2;
+ /* Configure interrupt as edge-sensitive */
+ GPIO_IS(GPIOF) &= ~btnpins;
+ /* Interrupt only respond to rising or falling edge (single-edge) */
+ GPIO_IBE(GPIOF) &= ~btnpins;
+ /* Trigger interrupt on rising-edge (when button is depressed) */
+ GPIO_IEV(GPIOF) |= btnpins;
+ /* Finally, Enable interrupt */
+ GPIO_IM(GPIOF) |= btnpins;
+ /* Enable the interrupt in the NVIC as well */
+ nvic_enable_irq(NVIC_GPIOF_IRQ);
}
#define FLASH_DELAY 800000
+static void delay(void)
+{
+ int i;
+ for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
+ __asm__("nop");
+}
+
int main(void)
{
int i;
+ clock_setup();
gpio_setup();
+ irq_setup();
- /* Blink STATUS LED (PF0) on the board. */
+ /* Blink each color of the RGB LED in order. */
while (1) {
/*
* Flash the Red diode
*/
- gpio_set(GPIOF, GPIO1);
-
- for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
- __asm__("nop");
-
- gpio_clear(GPIOF, GPIO1);
-
- for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
- __asm__("nop");
+ gpio_set(RGB_PORT, LED_R);
+ delay(); /* Wait a bit. */
+ gpio_clear(RGB_PORT, LED_R);
+ delay(); /* Wait a bit. */
/*
* Flash the Green diode
*/
- gpio_set(GPIOF, GPIO3);
-
- for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
- __asm__("nop");
-
- gpio_clear(GPIOF, GPIO3);
-
- for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
- __asm__("nop");
+ gpio_set(RGB_PORT, LED_G);
+ delay(); /* Wait a bit. */
+ gpio_clear(RGB_PORT, LED_G);
+ delay(); /* Wait a bit. */
/*
* Flash the Blue diode
*/
- gpio_set(GPIOF, GPIO2);
-
- for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
- __asm__("nop");
+ gpio_set(RGB_PORT, LED_B);
+ delay(); /* Wait a bit. */
+ gpio_clear(RGB_PORT, LED_B);
+ delay(); /* Wait a bit. */
+ }
- gpio_clear(GPIOF, GPIO2);
+ return 0;
+}
- for (i = 0; i < FLASH_DELAY; i++) /* Wait a bit. */
- __asm__("nop");
+void gpiof_isr(void)
+{
+ if (GPIO_RIS(GPIOF) & USR_SW1) {
+ /* SW1 was just depressed */
+ bypass = !bypass;
+ if (bypass) {
+ rcc_pll_bypass_enable();
+ /*
+ * The divisor is still applied to the raw clock.
+ * Disable the divisor, or we'll divide the raw clock.
+ */
+ SYSCTL_RCC &= ~SYSCTL_RCC_USESYSDIV;
+ }
+ else
+ {
+ rcc_change_pll_divisor(plldiv[ipll]);
+ }
+ /* Clear interrupt source */
+ GPIO_ICR(GPIOF) = USR_SW1;
}
- return 0;
+ if (GPIO_RIS(GPIOF) & USR_SW2) {
+ /* SW2 was just depressed */
+ if (!bypass) {
+ if (plldiv[++ipll] == 0)
+ ipll = 0;
+ rcc_change_pll_divisor(plldiv[ipll]);
+ }
+ /* Clear interrupt source */
+ GPIO_ICR(GPIOF) = USR_SW2;
+ }
}
diff --git a/examples/stm32/f1/other/rtc/rtc.c b/examples/stm32/f1/other/rtc/rtc.c
index 41c5d89..9db114c 100644
--- a/examples/stm32/f1/other/rtc/rtc.c
+++ b/examples/stm32/f1/other/rtc/rtc.c
@@ -19,7 +19,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
-#include <libopencm3/stm32/f1/rtc.h>
+#include <libopencm3/stm32/rtc.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/cm3/nvic.h>
diff --git a/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/Makefile b/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/Makefile
new file mode 100644
index 0000000..979317c
--- /dev/null
+++ b/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/Makefile
@@ -0,0 +1,24 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library. If not, see <http://www.gnu.org/licenses/>.
+##
+
+BINARY = adc-dac-printf
+LDSCRIPT = ../../../../../lib/stm32/f1/stm32f100xb.ld
+
+include ../../Makefile.include
+
diff --git a/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/README b/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/README
new file mode 100644
index 0000000..796cba2
--- /dev/null
+++ b/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/README
@@ -0,0 +1,17 @@
+Console on PA2 (tx only) 115200@8n1
+
+* Prints the ADC value on PA0 (adc channel 0) on the console
+* Echos half that ADC value out to DAC channel 2 on PA5
+* Prints the ADC value of PA1 (adc channel 1) to the console.
+
+Recommended wiring:
+* pot or any resistor ladder to PA0
+* jumper from PA5 to PA1
+
+example output:
+...
+tick: 228: adc0= 3950, target adc1=1975, adc1=1979
+tick: 229: adc0= 3949, target adc1=1974, adc1=1978
+tick: 230: adc0= 3950, target adc1=1975, adc1=1979
+tick: 231: adc0= 3949, target adc1=1974, adc1=1978
+...
diff --git a/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/adc-dac-printf.c b/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/adc-dac-printf.c
new file mode 100644
index 0000000..92e43c0
--- /dev/null
+++ b/examples/stm32/f1/stm32vl-discovery/adc-dac-printf/adc-dac-printf.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/stm32/dac.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/f1/rcc.h>
+#include <libopencm3/stm32/f1/adc.h>
+
+#define LED_DISCOVERY_USER_PORT GPIOC
+#define LED_DISCOVERY_USER_PIN GPIO8
+
+#define USART_CONSOLE USART2
+
+void clock_setup(void)
+{
+ rcc_clock_setup_in_hsi_out_24mhz();
+ /* Enable clocks for USART2 and DAC*/
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
+
+ /* and the ADC and IO ports */
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN);
+ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
+}
+
+void usart_setup(void)
+{
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
+ GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX);
+
+ usart_set_baudrate(USART_CONSOLE, 115200);
+ usart_set_databits(USART_CONSOLE, 8);
+ usart_set_stopbits(USART_CONSOLE, USART_STOPBITS_1);
+ usart_set_mode(USART_CONSOLE, USART_MODE_TX);
+ usart_set_parity(USART_CONSOLE, USART_PARITY_NONE);
+ usart_set_flow_control(USART_CONSOLE, USART_FLOWCONTROL_NONE);
+
+ /* Finally enable the USART. */
+ usart_enable(USART_CONSOLE);
+}
+
+/**
+ * Use USART_CONSOLE as a console.
+ * This is a syscall for newlib
+ * @param file
+ * @param ptr
+ * @param len
+ * @return
+ */
+int _write(int file, char *ptr, int len)
+{
+ int i;
+
+ if (file == STDOUT_FILENO || file == STDERR_FILENO) {
+ for (i = 0; i < len; i++) {
+ if (ptr[i] == '\n') {
+ usart_send_blocking(USART_CONSOLE, '\r');
+ }
+ usart_send_blocking(USART_CONSOLE, ptr[i]);
+ }
+ return i;
+ }
+ errno = EIO;
+ return -1;
+}
+
+void adc_setup(void)
+{
+ gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0);
+ gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO1);
+
+ /* Make sure the ADC doesn't run during config. */
+ adc_off(ADC1);
+
+ /* We configure everything for one single conversion. */
+ adc_disable_scan_mode(ADC1);
+ adc_set_single_conversion_mode(ADC1);
+ adc_disable_external_trigger_regular(ADC1);
+ adc_set_right_aligned(ADC1);
+ adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC);
+
+ adc_power_on(ADC1);
+
+ /* Wait for ADC starting up. */
+ int i;
+ for (i = 0; i < 800000; i++) /* Wait a bit. */
+ __asm__("nop");
+
+ adc_reset_calibration(ADC1);
+ adc_calibration(ADC1);
+}
+
+void dac_setup(void)
+{
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5);
+ dac_disable(CHANNEL_2);
+ dac_disable_waveform_generation(CHANNEL_2);
+ dac_enable(CHANNEL_2);
+ dac_set_trigger_source(DAC_CR_TSEL2_SW);
+}
+
+u16 read_adc_naiive(u8 channel)
+{
+ u8 channel_array[16];
+ channel_array[0] = channel;
+ adc_set_regular_sequence(ADC1, 1, channel_array);
+ adc_start_conversion_direct(ADC1);
+ while (!adc_eoc(ADC1));
+ u16 reg16 = adc_read_regular(ADC1);
+ return reg16;
+}
+
+int main(void)
+{
+ int i;
+ int j = 0;
+ clock_setup();
+ usart_setup();
+ printf("hi guys!\n");
+ adc_setup();
+ dac_setup();
+ gpio_set_mode(LED_DISCOVERY_USER_PORT, GPIO_MODE_OUTPUT_2_MHZ,
+ GPIO_CNF_OUTPUT_PUSHPULL, LED_DISCOVERY_USER_PIN);
+
+ while (1) {
+ u16 input_adc0 = read_adc_naiive(0);
+ u16 target = input_adc0 / 2;
+ dac_load_data_buffer_single(target, RIGHT12, CHANNEL_2);
+ dac_software_trigger(CHANNEL_2);
+ u16 input_adc1 = read_adc_naiive(1);
+ printf("tick: %d: adc0= %u, target adc1=%d, adc1=%d\n",
+ j++, input_adc0, target, input_adc1);
+ gpio_toggle(LED_DISCOVERY_USER_PORT, LED_DISCOVERY_USER_PIN); /* LED on/off */
+ for (i = 0; i < 1000000; i++) /* Wait a bit. */
+ __asm__("NOP");
+ }
+
+ return 0;
+}
diff --git a/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c b/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c
index b3c698b..be40dfd 100644
--- a/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c
+++ b/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c
@@ -20,7 +20,7 @@
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h>
-#include <libopencm3/stm32/f1/rtc.h>
+#include <libopencm3/stm32/rtc.h>
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/cm3/nvic.h>
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/Makefile b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/Makefile
new file mode 100644
index 0000000..d57ea7a
--- /dev/null
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/Makefile
@@ -0,0 +1,24 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library. If not, see <http://www.gnu.org/licenses/>.
+##
+
+BINARY = main
+LDSCRIPT = ../../../../../lib/stm32/l1/stm32l15xxb.ld
+
+include ../../Makefile.include
+
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/README b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/README
new file mode 100644
index 0000000..83cccfc
--- /dev/null
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/README
@@ -0,0 +1,18 @@
+This is _functionally_ identical to the "button-irq-printf"
+example, but has been modified to use some low power features.
+
+There is a 115200@8n1 console on PA2, which prints a tick count every second,
+and when the user push button is pressed, the time it is held down for is
+timed (in milliseconds)
+
+Instead of free running timers and busy loops, this version uses the RTC
+module and attempts to sleep as much as possible, including while the button
+is pressed.
+
+Status
+~~~~~~
+Only very basic power savings are done!
+
+Current consumption, led off/on, 16Mhz HSI: 2.7mA/5.4mA
+Current consumption, led off/on, 4Mhz HSI: 1.4mA/?.?mA
+Current consumption, led off/on, 4Mhz MSI: 0.9mA/?.?mA
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/main.c b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/main.c
new file mode 100644
index 0000000..6e4bb23
--- /dev/null
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/main.c
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/cm3/scb.h>
+#include <libopencm3/stm32/dbgmcu.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/exti.h>
+#include <libopencm3/stm32/timer.h>
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/l1/rcc.h>
+#include <libopencm3/stm32/l1/flash.h>
+
+#include "syscfg.h"
+
+static volatile struct state_t state;
+
+__attribute__((always_inline)) static inline void __WFI(void)
+{
+ __asm volatile ("wfi");
+}
+
+void gpio_setup(void)
+{
+ /* green led for ticking, blue for button feedback */
+ gpio_mode_setup(LED_DISCO_GREEN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_GREEN_PIN);
+ gpio_mode_setup(LED_DISCO_BLUE_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_BLUE_PIN);
+
+ /* Setup GPIO pins for USART2 transmit. */
+ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2);
+
+ /* Setup USART2 TX pin as alternate function. */
+ gpio_set_af(GPIOA, GPIO_AF7, GPIO2);
+}
+
+void BUTTON_DISCO_USER_isr(void)
+{
+ exti_reset_request(BUTTON_DISCO_USER_EXTI);
+ state.pressed = true;
+ if (state.falling) {
+ state.falling = false;
+ exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING);
+ state.hold_time = TIM_CNT(TIMER_BUTTON_PRESS);
+ } else {
+ state.falling = true;
+ exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_FALLING);
+ state.hold_time = TIM_CNT(TIMER_BUTTON_PRESS) = 0;
+ }
+}
+
+void setup_buttons(void)
+{
+ /* Enable EXTI0 interrupt. */
+ nvic_enable_irq(BUTTON_DISCO_USER_NVIC);
+
+ gpio_mode_setup(BUTTON_DISCO_USER_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BUTTON_DISCO_USER_PIN);
+
+ /* Configure the EXTI subsystem. */
+ exti_select_source(BUTTON_DISCO_USER_EXTI, BUTTON_DISCO_USER_PORT);
+ state.falling = false;
+ exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING);
+ exti_enable_request(BUTTON_DISCO_USER_EXTI);
+}
+
+void usart_setup(void)
+{
+ usart_set_baudrate(USART_CONSOLE, 115200);
+ usart_set_databits(USART_CONSOLE, 8);
+ usart_set_stopbits(USART_CONSOLE, USART_STOPBITS_1);
+ usart_set_mode(USART_CONSOLE, USART_MODE_TX);
+ usart_set_parity(USART_CONSOLE, USART_PARITY_NONE);
+ usart_set_flow_control(USART_CONSOLE, USART_FLOWCONTROL_NONE);
+
+ /* Finally enable the USART. */
+ usart_enable(USART_CONSOLE);
+}
+
+/**
+ * Use USART_CONSOLE as a console.
+ * @param file
+ * @param ptr
+ * @param len
+ * @return
+ */
+int _write(int file, char *ptr, int len)
+{
+ int i;
+
+ if (file == STDOUT_FILENO || file == STDERR_FILENO) {
+ for (i = 0; i < len; i++) {
+ if (ptr[i] == '\n') {
+ usart_send_blocking(USART_CONSOLE, '\r');
+ }
+ usart_send_blocking(USART_CONSOLE, ptr[i]);
+ }
+ return i;
+ }
+ errno = EIO;
+ return -1;
+}
+
+/*
+ * Free running ms timer.
+ */
+void setup_button_press_timer(void)
+{
+ timer_reset(TIMER_BUTTON_PRESS);
+ timer_set_prescaler(TIMER_BUTTON_PRESS, 3999); // 4Mhz/1000hz - 1
+ timer_set_period(TIMER_BUTTON_PRESS, 0xffff);
+ timer_enable_counter(TIMER_BUTTON_PRESS);
+}
+
+int setup_rtc(void)
+{
+ /* turn on power block to enable unlocking */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
+ pwr_disable_backup_domain_write_protect();
+
+ /* reset rtc */
+ RCC_CSR |= RCC_CSR_RTCRST;
+ RCC_CSR &= ~RCC_CSR_RTCRST;
+
+ /* We want to use the LSE fitted on the discovery board */
+ rcc_osc_on(LSE);
+ rcc_wait_for_osc_ready(LSE);
+
+ /* Select the LSE as rtc clock */
+ rcc_rtc_select_clock(RCC_CSR_RTCSEL_LSE);
+
+ /* ?! Stdperiph examples don't turn this on until _afterwards_ which
+ * simply doesn't work. It must be on at least to be able to configure it */
+ RCC_CSR |= RCC_CSR_RTCEN;
+
+ rtc_unlock();
+
+ /* enter init mode */
+ RTC_ISR |= RTC_ISR_INIT;
+ while ((RTC_ISR & RTC_ISR_INITF) == 0)
+ ;
+
+ /* set synch prescaler, using defaults for 1Hz out */
+ u32 sync = 255;
+ u32 async = 127;
+ rtc_set_prescaler(sync, async);
+
+ /* load time and date here if desired, and hour format */
+
+ /* exit init mode */
+ RTC_ISR &= ~(RTC_ISR_INIT);
+
+ /* and write protect again */
+ rtc_lock();
+
+ /* and finally enable the clock */
+ RCC_CSR |= RCC_CSR_RTCEN;
+
+ /* And wait for synchro.. */
+ rtc_wait_for_synchro();
+ return 0;
+}
+
+int setup_rtc_wakeup(int period)
+{
+ rtc_unlock();
+
+ /* ensure wakeup timer is off */
+ RTC_CR &= ~RTC_CR_WUTE;
+
+ /* Wait until we can write */
+ while ((RTC_ISR & RTC_ISR_WUTWF) == 0)
+ ;
+
+ RTC_WUTR = period - 1;
+
+ /* Use the 1Hz clock as source */
+ RTC_CR &= ~(RTC_CR_WUCLKSEL_MASK << RTC_CR_WUCLKSEL_SHIFT);
+ RTC_CR |= (RTC_CR_WUCLKSEL_SPRE << RTC_CR_WUCLKSEL_SHIFT);
+
+ /* Restart WakeUp unit */
+ RTC_CR |= RTC_CR_WUTE;
+
+ /* interrupt configuration */
+
+ /* also, let's have an interrupt */
+ RTC_CR |= RTC_CR_WUTIE;
+
+ /* done with rtc registers, lock them again */
+ rtc_lock();
+
+
+ nvic_enable_irq(NVIC_RTC_WKUP_IRQ);
+
+ // EXTI configuration
+ /* Configure the EXTI subsystem. */
+ // not needed, this chooses ports exti_select_source(EXTI20, BUTTON_DISCO_USER_PORT);
+ exti_set_trigger(EXTI20, EXTI_TRIGGER_RISING);
+ exti_enable_request(EXTI20);
+ return 0;
+}
+
+void rtc_wkup_isr(void)
+{
+ /* clear flag, not write protected */
+ RTC_ISR &= ~(RTC_ISR_WUTF);
+ exti_reset_request(EXTI20);
+ state.rtc_ticked = true;
+}
+
+int process_state(volatile struct state_t *st)
+{
+ if (st->rtc_ticked) {
+ st->rtc_ticked = 0;
+ printf("Tick: %x\n", (unsigned int) RTC_TR);
+#if FULL_USER_EXPERIENCE
+ gpio_toggle(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN);
+#else
+ gpio_clear(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN);
+#endif
+ }
+ if (st->pressed) {
+ st->pressed = false;
+ if (st->falling) {
+ gpio_set(LED_DISCO_BLUE_PORT, LED_DISCO_BLUE_PIN);
+ printf("Pushed down!\n");
+ } else {
+ gpio_clear(LED_DISCO_BLUE_PORT, LED_DISCO_BLUE_PIN);
+ printf("held: %u ms\n", st->hold_time);
+ }
+ }
+ return 0;
+}
+
+void reset_clocks(void)
+{
+ /* 4MHz MSI raw range 2*/
+ clock_scale_t myclock_config = {
+ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE2,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
+ .apb1_frequency = 4194000,
+ .apb2_frequency = 4194000,
+ .msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
+ };
+ rcc_clock_setup_msi(&myclock_config);
+
+ /* buttons and uarts */
+ rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN);
+ /* user feedback leds */
+ rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN);
+ /* Enable clocks for USART2. */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
+ /* And a timers for button presses */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM7EN);
+}
+
+int main(void)
+{
+ reset_clocks();
+ gpio_setup();
+ usart_setup();
+ setup_buttons();
+ setup_button_press_timer();
+ printf("we're awake!\n");
+
+ setup_rtc();
+ setup_rtc_wakeup(1);
+
+ while (1) {
+ PWR_CR |= PWR_CR_LPSDSR;
+ pwr_set_stop_mode();
+ __WFI();
+ reset_clocks();
+ process_state(&state);
+ }
+
+ return 0;
+}
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/syscfg.h b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/syscfg.h
new file mode 100644
index 0000000..8ca634b
--- /dev/null
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/syscfg.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SYSCFG_H
+#define SYSCFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/exti.h>
+#include <libopencm3/stm32/usart.h>
+
+
+#define USART_CONSOLE USART2
+#define USE_NASTYLOG 1
+
+#define LED_DISCO_GREEN_PORT GPIOB
+#define LED_DISCO_GREEN_PIN GPIO7
+#define LED_DISCO_BLUE_PORT GPIOB
+#define LED_DISCO_BLUE_PIN GPIO6
+
+#define BUTTON_DISCO_USER_PORT GPIOA
+#define BUTTON_DISCO_USER_PIN GPIO0
+#define BUTTON_DISCO_USER_EXTI EXTI0
+#define BUTTON_DISCO_USER_isr exti0_isr
+#define BUTTON_DISCO_USER_NVIC NVIC_EXTI0_IRQ
+#define TIMER_BUTTON_PRESS TIM7
+
+ struct state_t {
+ bool falling;
+ bool pressed;
+ int rtc_ticked;
+ int hold_time;
+ };
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSCFG_H */
+
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/README b/examples/stm32/l1/stm32l-discovery/button-irq-printf/README
index 63232ef..5de96a2 100644
--- a/examples/stm32/l1/stm32l-discovery/button-irq-printf/README
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/README
@@ -1,3 +1,35 @@
* Prints to the screen when the button is pushed/released (irq driven)
115200@8n1 console on PA2 (tx only)
+* uses basic timer 6 with overflows to generate a 1ms counter (not an ideal
+ use, but shows some api methods and can be demoed on the disco board)
+* uses basic timer 7 with the exti interrupts to do ghetto input capture.
+ Not as fast or precise as the real input capture modes, but can be used
+ on any gpio pin.
+
+No effort at saving power is made here. Current consumption on the Disco board
+is ~7.5mA when the green tick led is off, and about 10.5mA when it is on.
+
+example output:
+
+hi guys!
+TICK 0
+TICK 1
+TICK 2
+Pushed down!
+held: 443 ms
+Pushed down!
+TICK 3
+held: 217 ms
+Pushed down!
+held: 99 ms
+Pushed down!
+TICK 4
+held: 73 ms
+Pushed down!
+held: 60 ms
+TICK 5
+Pushed down!
+held: 98 ms
+Pushed down!
+
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c b/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c
index 1830c4d..82a3434 100644
--- a/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c
@@ -1,5 +1,20 @@
/*
- * Karl Palsson, 2012 <karlp@tweak.net.au
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <errno.h>
@@ -7,43 +22,55 @@
#include <unistd.h>
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/l1/rcc.h>
-#include <libopencm3/stm32/l1/gpio.h>
+#include <libopencm3/stm32/gpio.h>
#include <libopencm3/stm32/exti.h>
+#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/usart.h>
#include "syscfg.h"
static struct state_t state;
-void clock_setup(void) {
- /* Lots of things on all ports... */
- rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN);
- rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN);
+void clock_setup(void)
+{
+ rcc_clock_setup_pll(&clock_config[CLOCK_VRANGE1_HSI_PLL_24MHZ]);
+ /* Lots of things on all ports... */
+ rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN);
+ rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN);
+
+ /* Enable clocks for USART2. */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
+
+ /* And timers. */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM6EN);
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM7EN);
- /* Enable clocks for USART2. */
- rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
}
-void gpio_setup(void) {
- gpio_mode_setup(LED_DISCO_GREEN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_GREEN_PIN);
+void gpio_setup(void)
+{
+ /* green led for ticking, blue for button feedback */
+ gpio_mode_setup(LED_DISCO_GREEN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_GREEN_PIN);
+ gpio_mode_setup(LED_DISCO_BLUE_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_DISCO_BLUE_PIN);
- /* Setup GPIO pins for USART2 transmit. */
- gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2);
+ /* Setup GPIO pins for USART2 transmit. */
+ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2);
- /* Setup USART2 TX pin as alternate function. */
- gpio_set_af(GPIOA, GPIO_AF7, GPIO2);
+ /* Setup USART2 TX pin as alternate function. */
+ gpio_set_af(GPIOA, GPIO_AF7, GPIO2);
}
-void usart_setup(void) {
- usart_set_baudrate(USART_CONSOLE, 115200);
- usart_set_databits(USART_CONSOLE, 8);
- usart_set_stopbits(USART_CONSOLE, USART_STOPBITS_1);
- usart_set_mode(USART_CONSOLE, USART_MODE_TX);
- usart_set_parity(USART_CONSOLE, USART_PARITY_NONE);
- usart_set_flow_control(USART_CONSOLE, USART_FLOWCONTROL_NONE);
-
- /* Finally enable the USART. */
- usart_enable(USART_CONSOLE);
+void usart_setup(void)
+{
+ usart_set_baudrate(USART_CONSOLE, 115200);
+ usart_set_databits(USART_CONSOLE, 8);
+ usart_set_stopbits(USART_CONSOLE, USART_STOPBITS_1);
+ usart_set_mode(USART_CONSOLE, USART_MODE_TX);
+ usart_set_parity(USART_CONSOLE, USART_PARITY_NONE);
+ usart_set_flow_control(USART_CONSOLE, USART_FLOWCONTROL_NONE);
+
+ /* Finally enable the USART. */
+ usart_enable(USART_CONSOLE);
}
/**
@@ -53,65 +80,108 @@ void usart_setup(void) {
* @param len
* @return
*/
-int _write(int file, char *ptr, int len) {
- int i;
-
- if (file == STDOUT_FILENO || file == STDERR_FILENO) {
- for (i = 0; i < len; i++) {
- if (ptr[i] == '\n') {
- usart_send_blocking(USART_CONSOLE, '\r');
- }
- usart_send_blocking(USART_CONSOLE, ptr[i]);
- }
- return i;
- }
- errno = EIO;
- return -1;
+int _write(int file, char *ptr, int len)
+{
+ int i;
+
+ if (file == STDOUT_FILENO || file == STDERR_FILENO) {
+ for (i = 0; i < len; i++) {
+ if (ptr[i] == '\n') {
+ usart_send_blocking(USART_CONSOLE, '\r');
+ }
+ usart_send_blocking(USART_CONSOLE, ptr[i]);
+ }
+ return i;
+ }
+ errno = EIO;
+ return -1;
+}
+
+void BUTTON_DISCO_USER_isr(void)
+{
+ exti_reset_request(BUTTON_DISCO_USER_EXTI);
+ if (state.falling) {
+ gpio_clear(LED_DISCO_BLUE_PORT, LED_DISCO_BLUE_PIN);
+ state.falling = false;
+ exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING);
+ unsigned int x = TIM_CNT(TIM7);
+ printf("held: %u ms\n", x);
+ } else {
+ gpio_set(LED_DISCO_BLUE_PORT, LED_DISCO_BLUE_PIN);
+ printf("Pushed down!\n");
+ TIM_CNT(TIM7) = 0;
+ state.falling = true;
+ exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_FALLING);
+ }
+}
+
+static volatile int t6ovf = 0;
+
+void tim6_isr(void)
+{
+ TIM_SR(TIM6) &= ~TIM_SR_UIF;
+ if (t6ovf++ > 1000) {
+ printf("TICK %d\n", state.tickcount++);
+ t6ovf = 0;
+ gpio_toggle(LED_DISCO_GREEN_PORT, LED_DISCO_GREEN_PIN);
+ }
+}
+
+/*
+ * Another ms timer, this one used to generate an overflow interrupt at 1ms
+ * It is used to toggle leds and write tick counts
+ */
+void setup_tim6(void)
+{
+ timer_reset(TIM6);
+ // 24Mhz / 10khz -1.
+ timer_set_prescaler(TIM6, 2399); // 24Mhz/10000hz - 1
+ // 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts
+ timer_set_period(TIM6, 10);
+
+ nvic_enable_irq(NVIC_TIM6_IRQ);
+ timer_enable_update_event(TIM6); // default at reset!
+ timer_enable_irq(TIM6, TIM_DIER_UIE);
+ timer_enable_counter(TIM6);
}
-void BUTTON_DISCO_USER_isr(void) {
- exti_reset_request(BUTTON_DISCO_USER_EXTI);
- if (state.falling) {
- state.falling = false;
- exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING);
- // ILOG("fell: %d\n", TIM_CNT(TIM7));
- puts("fell!\n");
- } else {
- puts("Rose!\n");
- // TIM_CNT(TIM7) = 0;
- state.falling = true;
- exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_FALLING);
- }
+/*
+ * Free running ms timer.
+ */
+void setup_tim7(void)
+{
+ timer_reset(TIM7);
+ timer_set_prescaler(TIM7, 23999); // 24Mhz/1000hz - 1
+ timer_set_period(TIM7, 0xffff);
+ timer_enable_counter(TIM7);
}
-void setup_buttons(void) {
- /* Enable EXTI0 interrupt. */
- nvic_enable_irq(BUTTON_DISCO_USER_NVIC);
+void setup_buttons(void)
+{
+ /* Enable EXTI0 interrupt. */
+ nvic_enable_irq(BUTTON_DISCO_USER_NVIC);
- gpio_mode_setup(BUTTON_DISCO_USER_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BUTTON_DISCO_USER_PIN);
+ gpio_mode_setup(BUTTON_DISCO_USER_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BUTTON_DISCO_USER_PIN);
- /* Configure the EXTI subsystem. */
- exti_select_source(BUTTON_DISCO_USER_EXTI, BUTTON_DISCO_USER_PORT);
- state.falling = false;
- exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING);
- exti_enable_request(BUTTON_DISCO_USER_EXTI);
+ /* Configure the EXTI subsystem. */
+ exti_select_source(BUTTON_DISCO_USER_EXTI, BUTTON_DISCO_USER_PORT);
+ state.falling = false;
+ exti_set_trigger(BUTTON_DISCO_USER_EXTI, EXTI_TRIGGER_RISING);
+ exti_enable_request(BUTTON_DISCO_USER_EXTI);
}
-int main(void) {
- int i;
- int j = 0;
- clock_setup();
- gpio_setup();
- usart_setup();
- puts("hi guys!\n");
- setup_buttons();
- while (1) {
- puts("tick:");
- putchar('a' + (j++ % 26));
- gpio_toggle(GPIOB, GPIO7); /* LED on/off */
- for (i = 0; i < 100000; i++) /* Wait a bit. */
- __asm__("NOP");
- }
-
- return 0;
+int main(void)
+{
+ clock_setup();
+ gpio_setup();
+ usart_setup();
+ printf("hi guys!\n");
+ setup_buttons();
+ setup_tim6();
+ setup_tim7();
+ while (1) {
+ ;
+ }
+
+ return 0;
}
diff --git a/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h b/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h
index 32cf465..d278ac4 100644
--- a/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h
+++ b/examples/stm32/l1/stm32l-discovery/button-irq-printf/syscfg.h
@@ -1,7 +1,20 @@
/*
- * General configuration of the device
+ * This file is part of the libopencm3 project.
*
- * Karl Palsson <karlp@tweak.net.au> 2012
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SYSCFG_H
@@ -11,8 +24,8 @@
extern "C" {
#endif
-#include <libopencm3/stm32/l1/gpio.h>
-#include <libopencm3/stm32/l1/nvic.h>
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/stm32/gpio.h>
#include <libopencm3/stm32/exti.h>
#include <libopencm3/stm32/usart.h>
@@ -31,10 +44,10 @@ extern "C" {
#define BUTTON_DISCO_USER_isr exti0_isr
#define BUTTON_DISCO_USER_NVIC NVIC_EXTI0_IRQ
-
- struct state_t {
- bool falling;
- };
+ struct state_t {
+ bool falling;
+ int tickcount;
+ };
#ifdef __cplusplus
diff --git a/examples/stm32/l1/stm32l-discovery/usart/usart.c b/examples/stm32/l1/stm32l-discovery/usart/usart.c
index 3335ca8..cc766dd 100644
--- a/examples/stm32/l1/stm32l-discovery/usart/usart.c
+++ b/examples/stm32/l1/stm32l-discovery/usart/usart.c
@@ -22,59 +22,63 @@
#include <libopencm3/stm32/l1/gpio.h>
#include <libopencm3/stm32/usart.h>
-void clock_setup(void) {
- /* We are running on MSI after boot. */
- /* Enable GPIOD clock for LED & USARTs. */
- rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN);
- rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN);
+void clock_setup(void)
+{
+ /* We are running on MSI after boot. */
+ /* Enable GPIOD clock for LED & USARTs. */
+ rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOAEN);
+ rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_GPIOBEN);
- /* Enable clocks for USART2. */
- rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
+ /* Enable clocks for USART2. */
+ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
}
-void usart_setup(void) {
- /* Setup USART2 parameters. */
- usart_set_baudrate(USART2, 38400);
- usart_set_databits(USART2, 8);
- usart_set_stopbits(USART2, USART_STOPBITS_1);
- usart_set_mode(USART2, USART_MODE_TX);
- usart_set_parity(USART2, USART_PARITY_NONE);
- usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
+void usart_setup(void)
+{
+ /* Setup USART2 parameters. */
+ usart_set_baudrate(USART2, 38400);
+ usart_set_databits(USART2, 8);
+ usart_set_stopbits(USART2, USART_STOPBITS_1);
+ usart_set_mode(USART2, USART_MODE_TX);
+ usart_set_parity(USART2, USART_PARITY_NONE);
+ usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
- /* Finally enable the USART. */
- usart_enable(USART2);
+ /* Finally enable the USART. */
+ usart_enable(USART2);
}
-void gpio_setup(void) {
- /* Setup GPIO pin GPIO7 on GPIO port B for Green LED. */
- gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7);
+void gpio_setup(void)
+{
+ /* Setup GPIO pin GPIO7 on GPIO port B for Green LED. */
+ gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7);
- /* Setup GPIO pins for USART2 transmit. */
- gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2);
+ /* Setup GPIO pins for USART2 transmit. */
+ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2);
- /* Setup USART2 TX pin as alternate function. */
- gpio_set_af(GPIOA, GPIO_AF7, GPIO2);
+ /* Setup USART2 TX pin as alternate function. */
+ gpio_set_af(GPIOA, GPIO_AF7, GPIO2);
}
-int main(void) {
- int i, j = 0, c = 0;
+int main(void)
+{
+ int i, j = 0, c = 0;
- clock_setup();
- gpio_setup();
- usart_setup();
+ clock_setup();
+ gpio_setup();
+ usart_setup();
- /* Blink the LED (PD12) on the board with every transmitted byte. */
- while (1) {
- gpio_toggle(GPIOB, GPIO7); /* LED on/off */
- usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */
- c = (c == 9) ? 0 : c + 1; /* Increment c. */
- if ((j++ % 80) == 0) { /* Newline after line full. */
- usart_send_blocking(USART2, '\r');
- usart_send_blocking(USART2, '\n');
- }
- for (i = 0; i < 100000; i++) /* Wait a bit. */
- __asm__("NOP");
- }
+ /* Blink the LED (PD12) on the board with every transmitted byte. */
+ while (1) {
+ gpio_toggle(GPIOB, GPIO7); /* LED on/off */
+ usart_send_blocking(USART2, c + '0'); /* USART2: Send byte. */
+ c = (c == 9) ? 0 : c + 1; /* Increment c. */
+ if ((j++ % 80) == 0) { /* Newline after line full. */
+ usart_send_blocking(USART2, '\r');
+ usart_send_blocking(USART2, '\n');
+ }
+ for (i = 0; i < 100000; i++) /* Wait a bit. */
+ __asm__("NOP");
+ }
- return 0;
+ return 0;
}
diff --git a/include/libopencm3/lm4f/rcc.h b/include/libopencm3/lm4f/rcc.h
new file mode 100644
index 0000000..1c15f4b
--- /dev/null
+++ b/include/libopencm3/lm4f/rcc.h
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @defgroup rcc_defines RCC Defines
+ *
+ * @ingroup LM4F_defines
+ *
+ * \brief <b>Defined Constants and Types for the LM4F Clock control API</b>
+ * @{
+ */
+
+#ifndef LM4F_RCC_H
+#define LM4F_RCC_H
+
+#include <libopencm3/lm4f/systemcontrol.h>
+
+/**
+ * \brief Oscillator source values
+ *
+ * Possible values of the oscillator source.
+ */
+typedef enum {
+ OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
+ OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
+ OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
+ OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
+ OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
+} osc_src_t;
+
+/**
+ * \brief PWM clock divisor values
+ *
+ * Possible values of the binary divisor used to predivide the system clock down
+ * for use as the timing reference for the PWM module.
+ */
+typedef enum {
+ PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
+ PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
+ PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
+ PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
+ PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
+ PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
+} pwm_clkdiv_t;
+
+/**
+ * \brief Predefined crystal values
+ *
+ * Predefined crystal values for the XTAL field in SYSCTL_RCC.
+ * Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and
+ * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
+ * of 400MHz.
+ */
+typedef enum {
+ XTAL_4M = SYSCTL_RCC_XTAL_4M,
+ XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
+ XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
+ XTAL_5M = SYSCTL_RCC_XTAL_5M,
+ XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12,
+ XTAL_6M = SYSCTL_RCC_XTAL_6M,
+ XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144,
+ XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728,
+ XTAL_8M = SYSCTL_RCC_XTAL_8M,
+ XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192,
+ XTAL_10M = SYSCTL_RCC_XTAL_10M,
+ XTAL_12M = SYSCTL_RCC_XTAL_12M,
+ XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288,
+ XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56,
+ XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818,
+ XTAL_16M = SYSCTL_RCC_XTAL_16M,
+ XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384,
+ XTAL_18M = SYSCTL_RCC_XTAL_18M,
+ XTAL_20M = SYSCTL_RCC_XTAL_20M,
+ XTAL_24M = SYSCTL_RCC_XTAL_24M,
+ XTAL_25M = SYSCTL_RCC_XTAL_25M,
+} xtal_t;
+
+/**
+ * @}
+ */
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+/* Low-level clock API */
+void rcc_configure_xtal(xtal_t xtal);
+void rcc_disable_main_osc(void);
+void rcc_disable_interal_osc(void);
+void rcc_enable_main_osc(void);
+void rcc_enable_interal_osc(void);
+void rcc_enable_rcc2(void);
+void rcc_pll_off(void);
+void rcc_pll_on(void);
+void rcc_set_osc_source(osc_src_t src);
+void rcc_pll_bypass_disable(void);
+void rcc_pll_bypass_enable(void);
+void rcc_set_pll_divisor(u8 div400);
+void rcc_set_pwm_divisor(pwm_clkdiv_t div);
+void rcc_usb_pll_off(void);
+void rcc_usb_pll_on(void);
+void rcc_wait_for_pll_ready(void);
+/* High-level clock API */
+void rcc_change_pll_divisor(u8 plldiv400);
+u32 rcc_get_system_clock_frequency(void);
+void rcc_sysclk_config(osc_src_t src, xtal_t xtal, u8 pll_div400);
+
+END_DECLS
+
+
+#endif /* LM4F_RCC_H */
diff --git a/include/libopencm3/lm4f/systemcontrol.h b/include/libopencm3/lm4f/systemcontrol.h
index af4b71f..30fa1c9 100644
--- a/include/libopencm3/lm4f/systemcontrol.h
+++ b/include/libopencm3/lm4f/systemcontrol.h
@@ -21,6 +21,7 @@
#define LM4F_SYSTEMCONTROL_H
#include <libopencm3/cm3/common.h>
+#include <libopencm3/lm4f/memorymap.h>
#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
@@ -369,9 +370,11 @@
/** Auto Clock Gating */
#define SYSCTL_RCC2_ACG (1 << 27)
/** System Clock Divisor 2 */
-#define SYSCTL_RCC2_SYSDIV2_MASK (0xF << 23)
+#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23)
/** Additional LSB for SYSDIV2 */
#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22)
+/** System clock divisor mask when RCC2_DIV400 is set */
+#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22)
/** Power-Down USB PLL */
#define SYSCTL_RCC2_USBPWRDN (1 << 14)
/** PLL Power Down 2 */
@@ -450,6 +453,273 @@
/** PLL lock */
#define SYSCTL_PLLSTAT_LOCK (1 << 0)
+/* =============================================================================
+ * Convenience definitions for a readable API
+ * ---------------------------------------------------------------------------*/
+/**
+ * \brief Clock enable definitions
+ *
+ * The definitions are specified in the form
+ * 31:5 register offset from SYSCTL_BASE for the clock register
+ * 4:0 bit offset for the given peripheral
+ *
+ * The names have the form [clock_type]_[periph_type]_[periph_number]
+ * Where clock_type is
+ * RCC for run clock
+ * SCC for sleep clock
+ * DCC for deep-sleep clock
+ */
+typedef enum {
+ /*
+ * Run clock control
+ */
+ RCC_WD0 = ((u32)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
+ RCC_WD1,
+
+ RCC_TIMER0 = ((u32)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
+ RCC_TIMER1,
+ RCC_TIMER2,
+ RCC_TIMER3,
+ RCC_TIMER4,
+ RCC_TIMER5,
+
+ RCC_GPIOA = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+ RCC_GPIOB,
+ RCC_GPIOC,
+ RCC_GPIOD,
+ RCC_GPIOE,
+ RCC_GPIOF,
+ RCC_GPIOG,
+ RCC_GPIOH,
+ RCC_GPIOJ,
+ RCC_GPIOK,
+ RCC_GPIOL,
+ RCC_GPIOM,
+ RCC_GPION,
+ RCC_GPIOP,
+ RCC_GPIOQ,
+
+ RCC_DMA = ((u32)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
+
+ RCC_HIB = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+
+ RCC_UART0 = ((u32)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
+ RCC_UART1,
+ RCC_UART2,
+ RCC_UART3,
+ RCC_UART4,
+ RCC_UART5,
+ RCC_UART6,
+ RCC_UART7,
+
+ RCC_SSI0 = ((u32)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
+ RCC_SSI1,
+ RCC_SSI2,
+ RCC_SSI3,
+
+ RCC_I2C0 = ((u32)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
+ RCC_I2C1,
+ RCC_I2C2,
+ RCC_I2C3,
+ RCC_I2C4,
+ RCC_I2C5,
+
+ RCC_USB0 = ((u32)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
+
+ RCC_CAN0 = ((u32)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
+ RCC_CAN1,
+
+ RCC_ADC0 = ((u32)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
+ RCC_ADC1,
+
+ RCC_ACMP0 = ((u32)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
+
+ RCC_PWM0 = ((u32)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
+ RCC_PWM1,
+
+ RCC_QEI0 = ((u32)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
+ RCC_QEI1,
+
+ RCC_EEPROM0 = ((u32)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
+
+ RCC_WTIMER0 = ((u32)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
+ RCC_WTIMER1,
+ RCC_WTIMER2,
+ RCC_WTIMER3,
+ RCC_WTIMER4,
+ RCC_WTIMER5,
+
+
+ /*
+ * Sleep clock control
+ */
+ SCC_WD0 = ((u32)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
+ SCC_WD1,
+
+ SCC_TIMER0 = ((u32)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
+ SCC_TIMER1,
+ SCC_TIMER2,
+ SCC_TIMER3,
+ SCC_TIMER4,
+ SCC_TIMER5,
+
+ SCC_GPIOA = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+ SCC_GPIOB,
+ SCC_GPIOC,
+ SCC_GPIOD,
+ SCC_GPIOE,
+ SCC_GPIOF,
+ SCC_GPIOG,
+ SCC_GPIOH,
+ SCC_GPIOJ,
+ SCC_GPIOK,
+ SCC_GPIOL,
+ SCC_GPIOM,
+ SCC_GPION,
+ SCC_GPIOP,
+ SCC_GPIOQ,
+
+ SCC_DMA = ((u32)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
+
+ SCC_HIB = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+
+ SCC_UART0 = ((u32)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
+ SCC_UART1,
+ SCC_UART2,
+ SCC_UART3,
+ SCC_UART4,
+ SCC_UART5,
+ SCC_UART6,
+ SCC_UART7,
+
+ SCC_SSI0 = ((u32)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
+ SCC_SSI1,
+ SCC_SSI2,
+ SCC_SSI3,
+
+ SCC_I2C0 = ((u32)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
+ SCC_I2C1,
+ SCC_I2C2,
+ SCC_I2C3,
+ SCC_I2C4,
+ SCC_I2C5,
+
+ SCC_USB0 = ((u32)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
+
+ SCC_CAN0 = ((u32)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
+ SCC_CAN1,
+
+ SCC_ADC0 = ((u32)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
+ SCC_ADC1,
+
+ SCC_ACMP0 = ((u32)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
+
+ SCC_PWM0 = ((u32)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
+ SCC_PWM1,
+
+ SCC_QEI0 = ((u32)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
+ SCC_QEI1,
+
+ SCC_EEPROM0 = ((u32)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
+
+ SCC_WTIMER0 = ((u32)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
+ SCC_WTIMER1,
+ SCC_WTIMER2,
+ SCC_WTIMER3,
+ SCC_WTIMER4,
+ SCC_WTIMER5,
+
+ /*
+ * Deep-sleep clock control
+ */
+ DCC_WD0 = ((u32)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
+ DCC_WD1,
+
+ DCC_TIMER0 = ((u32)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
+ DCC_TIMER1,
+ DCC_TIMER2,
+ DCC_TIMER3,
+ DCC_TIMER4,
+ DCC_TIMER5,
+
+ DCC_GPIOA = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+ DCC_GPIOB,
+ DCC_GPIOC,
+ DCC_GPIOD,
+ DCC_GPIOE,
+ DCC_GPIOF,
+ DCC_GPIOG,
+ DCC_GPIOH,
+ DCC_GPIOJ,
+ DCC_GPIOK,
+ DCC_GPIOL,
+ DCC_GPIOM,
+ DCC_GPION,
+ DCC_GPIOP,
+ DCC_GPIOQ,
+
+ DCC_DMA = ((u32)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
+
+ DCC_HIB = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+
+ DCC_UART0 = ((u32)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
+ DCC_UART1,
+ DCC_UART2,
+ DCC_UART3,
+ DCC_UART4,
+ DCC_UART5,
+ DCC_UART6,
+ DCC_UART7,
+
+ DCC_SSI0 = ((u32)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
+ DCC_SSI1,
+ DCC_SSI2,
+ DCC_SSI3,
+
+ DCC_I2C0 = ((u32)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
+ DCC_I2C1,
+ DCC_I2C2,
+ DCC_I2C3,
+ DCC_I2C4,
+ DCC_I2C5,
+
+ DCC_USB0 = ((u32)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
+
+ DCC_CAN0 = ((u32)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
+ DCC_CAN1,
+
+ DCC_ADC0 = ((u32)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
+ DCC_ADC1,
+
+ DCC_ACMP0 = ((u32)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
+
+ DCC_PWM0 = ((u32)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
+ DCC_PWM1,
+
+ DCC_QEI0 = ((u32)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
+ DCC_QEI1,
+
+ DCC_EEPROM0 = ((u32)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
+
+ DCC_WTIMER0 = ((u32)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
+ DCC_WTIMER1,
+ DCC_WTIMER2,
+ DCC_WTIMER3,
+ DCC_WTIMER4,
+ DCC_WTIMER5,
+
+} clken_t;
+
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+void periph_clock_enable(clken_t periph);
+void periph_clock_disable(clken_t periph);
+
+END_DECLS
+
#endif /* LM4F_SYSTEMCONTROL_H */
diff --git a/include/libopencm3/stm32/common/pwr_common_all.h b/include/libopencm3/stm32/common/pwr_common_all.h
new file mode 100644
index 0000000..cc9fd22
--- /dev/null
+++ b/include/libopencm3/stm32/common/pwr_common_all.h
@@ -0,0 +1,119 @@
+/** @addtogroup pwr_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
+
+#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
+#define LIBOPENCM3_PWR_COMMON_ALL_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+
+/* --- PWR registers ------------------------------------------------------- */
+
+/* Power control register (PWR_CR) */
+#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
+
+/* Power control/status register (PWR_CSR) */
+#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* Bits [31:9]: Reserved, must be kept at reset value. */
+
+/* DBP: Disable backup domain write protection */
+#define PWR_CR_DBP (1 << 8)
+
+/* PLS[7:5]: PVD level selection */
+#define PWR_CR_PLS_LSB 5
+/** @defgroup pwr_pls PVD level selection
+@ingroup STM32F_pwr_defines
+
+@{*/
+#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
+/**@}*/
+#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
+
+/* PVDE: Power voltage detector enable */
+#define PWR_CR_PVDE (1 << 4)
+
+/* CSBF: Clear standby flag */
+#define PWR_CR_CSBF (1 << 3)
+
+/* CWUF: Clear wakeup flag */
+#define PWR_CR_CWUF (1 << 2)
+
+/* PDDS: Power down deepsleep */
+#define PWR_CR_PDDS (1 << 1)
+
+/* LPDS: Low-power deepsleep */
+#define PWR_CR_LPDS (1 << 0)
+
+/* --- PWR_CSR values ------------------------------------------------------ */
+
+/* Bits [31:9]: Reserved, must be kept at reset value. */
+
+/* EWUP: Enable WKUP pin */
+#define PWR_CSR_EWUP (1 << 8)
+
+/* Bits [7:3]: Reserved, must be kept at reset value. */
+
+/* PVDO: PVD output */
+#define PWR_CSR_PVDO (1 << 2)
+
+/* SBF: Standby flag */
+#define PWR_CSR_SBF (1 << 1)
+
+/* WUF: Wakeup flag */
+#define PWR_CSR_WUF (1 << 0)
+
+/* --- PWR function prototypes ------------------------------------------- */
+
+BEGIN_DECLS
+
+void pwr_disable_backup_domain_write_protect(void);
+void pwr_enable_backup_domain_write_protect(void);
+void pwr_enable_power_voltage_detect(u32 pvd_level);
+void pwr_disable_power_voltage_detect(void);
+void pwr_clear_standby_flag(void);
+void pwr_clear_wakeup_flag(void);
+void pwr_set_standby_mode(void);
+void pwr_set_stop_mode(void);
+void pwr_voltage_regulator_on_in_stop(void);
+void pwr_voltage_regulator_low_power_in_stop(void);
+void pwr_enable_wakeup_pin(void);
+void pwr_disable_wakeup_pin(void);
+bool pwr_voltage_high(void);
+bool pwr_get_standby_flag(void);
+bool pwr_get_wakeup_flag(void);
+
+END_DECLS
+
+/**@}*/
+#endif
diff --git a/include/libopencm3/stm32/common/rtc_common_bcd.h b/include/libopencm3/stm32/common/rtc_common_bcd.h
new file mode 100644
index 0000000..130020e
--- /dev/null
+++ b/include/libopencm3/stm32/common/rtc_common_bcd.h
@@ -0,0 +1,302 @@
+/** @addtogroup rtc_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H */
+
+/*
+ * This covers the "version 2" RTC peripheral. This is completely different
+ * to the v1 RTC periph on the F1 series devices. It has BCD counters, with
+ * automatic leapyear corrections and daylight savings support.
+ * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some
+ * only support a subset.
+ */
+
+#ifndef LIBOPENCM3_RTC2_H
+#define LIBOPENCM3_RTC2_H
+
+/**@{*/
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/memorymap.h>
+
+/* RTC time register (RTC_TR) */
+#define RTC_TR MMIO32(RTC_BASE + 0x00)
+
+/* RTC date register (RTC_DR) */
+#define RTC_DR MMIO32(RTC_BASE + 0x04)
+
+/* RTC control register (RTC_CR) */
+#define RTC_CR MMIO32(RTC_BASE + 0x08)
+
+/* RTC initialization and status register (RTC_ISR) */
+#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
+
+/* RTC prescaler register (RTC_PRER) */
+#define RTC_PRER MMIO32(RTC_BASE + 0x10)
+
+/* RTC wakeup timer register (RTC_WUTR) */
+#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
+
+/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
+#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
+
+/* RTC alarm X register (RTC_ALRMxR) */
+#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
+#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
+
+/* RTC write protection register (RTC_WPR)*/
+#define RTC_WPR MMIO32(RTC_BASE + 0x24)
+
+/* RTC sub second register (RTC_SSR) (high and med+ only) */
+#define RTC_SSR MMIO32(RTC_BASE + 0x28)
+
+/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
+#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
+
+/* RTC time stamp time register (RTC_TSTR) */
+#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
+/* RTC time stamp date register (RTC_TSDR) */
+#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
+/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
+#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
+
+/* RTC calibration register (RTC_CALR) (high and med+ only) */
+#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
+
+/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
+#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
+
+/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
+#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
+#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
+
+/* RTC backup registers (RTC_BKPxR) */
+#define RTC_BKP_BASE (RTC_BASE + 0x50)
+#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg))
+
+
+/* RTC time register (RTC_TR) bits */
+#define RTC_TR_TR_PM (1 << 22)
+#define RTC_TR_HT_SHIFT (20)
+#define RTC_TR_HT_MASK (0x3)
+#define RTC_TR_HU_SHIFT (16)
+#define RTC_TR_HU_MASK (0xf)
+#define RTC_TR_MNT_SHIFT (12)
+#define RTC_TR_MNT_MASK (0x7)
+#define RTC_TR_MNU_SHIFT (8)
+#define RTC_TR_MNU_MASK (0xf)
+#define RTC_TR_ST_SHIFT (4)
+#define RTC_TR_ST_MASK (0x3)
+#define RTC_TR_SU_SHIFT (0)
+#define RTC_TR_SU_MASK (0xf)
+
+/* RTC date register (RTC_DR) bits */
+#define RTC_DR_YT_SHIFT (20)
+#define RTC_DR_YT_MASK (0xf)
+#define RTC_DR_YU_SHIFT (16)
+#define RTC_DR_YU_MASK (0xf)
+#define RTC_DR_WDU_SHIFT (13)
+#define RTC_DR_WDU_MASK (0x7)
+#define RTC_DR_MT (1<<12)
+#define RTC_DR_MU_SHIFT (8)
+#define RTC_DR_MU_MASK (0xf)
+#define RTC_DR_DT_SHIFT (4)
+#define RTC_DR_DT_MASK (0x3)
+#define RTC_DR_DU_SHIFT (0)
+#define RTC_DR_DU_MASK (0xf)
+
+/* RTC control register (RTC_CR) bits */
+#define RTC_CR_COE (1<<23)
+
+/* These bits are used to select the flag to be routed to AFO_ALARM RTC output */
+#define RTC_CR_OSEL_SHIFT 21
+#define RTC_CR_OSEL_MASK (0x3)
+#define RTC_CR_OSEL_DISABLED (0x0)
+#define RTC_CR_OSEL_ALARMA (0x1)
+#define RTC_CR_OSEL_ALARMB (0x2)
+#define RTC_CR_OSEL_WAKEUP (0x3)
+
+#define RTC_CR_POL (1<<20)
+#define RTC_CR_COSEL (1<<19)
+#define RTC_CR_BKP (1<<18)
+#define RTC_CR_SUB1H (1<<17)
+#define RTC_CR_ADD1H (1<<16)
+#define RTC_CR_TSIE (1<<15)
+#define RTC_CR_WUTIE (1<<14)
+#define RTC_CR_ALRBIE (1<<13)
+#define RTC_CR_ALRAIE (1<<12)
+#define RTC_CR_TSE (1<<11)
+#define RTC_CR_WUTE (1<<10)
+#define RTC_CR_ALRBE (1<<9)
+#define RTC_CR_ALRAE (1<<8)
+#define RTC_CR_DCE (1<<7)
+#define RTC_CR_FMT (1<<6)
+#define RTC_CR_BYPSHAD (1<<5)
+#define RTC_CR_REFCKON (1<<4)
+#define RTC_CR_TSEDGE (1<<3)
+#define RTC_CR_TSEDGE (1<<3)
+#define RTC_CR_WUCLKSEL_SHIFT (0)
+#define RTC_CR_WUCLKSEL_MASK (0x7)
+#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0)
+#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1)
+#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2)
+#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
+#define RTC_CR_WUCLKSEL_SPRE (0x4)
+#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
+
+/* RTC initialization and status register (RTC_ISR) bits */
+#define RTC_ISR_RECALPF (1<<16)
+#define RTC_ISR_TAMP3F (1<<15)
+#define RTC_ISR_TAMP2F (1<<14)
+#define RTC_ISR_TAMP1F (1<<13)
+#define RTC_ISR_TSOVF (1<<12)
+#define RTC_ISR_TSF (1<<11)
+#define RTC_ISR_WUTF (1<<10)
+#define RTC_ISR_ALRBF (1<<9)
+#define RTC_ISR_ALRAF (1<<8)
+#define RTC_ISR_INIT (1<<7)
+#define RTC_ISR_INITF (1<<6)
+#define RTC_ISR_RSF (1<<5)
+#define RTC_ISR_INITS (1<<4)
+#define RTC_ISR_SHPF (1<<3)
+#define RTC_ISR_WUTWF (1<<2)
+#define RTC_ISR_ALRBWF (1<<1)
+#define RTC_ISR_ALRAWF (1<<0)
+
+/* RTC prescaler register (RTC_PRER) bits */
+#define RTC_PRER_PREDIV_A_SHIFT (16)
+#define RTC_PRER_PREDIV_A_MASK (0x7f)
+#define RTC_PRER_PREDIV_S_SHIFT (0)
+#define RTC_PRER_PREDIV_S_MASK (0x7fff)
+
+/* RTC calibration register (RTC_CALIBR) bits */
+// FIXME - TODO
+
+/* RTC Alarm register bits Applies to RTC_ALRMAR and RTC_ALRMBR */
+#define RTC_ALRMXR_MSK4 (1<<31)
+#define RTC_ALRMXR_WDSEL (1<<30)
+#define RTC_ALRMXR_DT_SHIFT (28)
+#define RTC_ALRMXR_DT_MASK (0x3)
+#define RTC_ALRMXR_DU_SHIFT (24)
+#define RTC_ALRMXR_DU_MASK (0xf)
+#define RTC_ALRMXR_MSK3 (1<<23)
+#define RTC_ALRMXR_PM (1<<22)
+#define RTC_ALRMXR_HT_SHIFT (20)
+#define RTC_ALRMXR_HT_MASK (0x3)
+#define RTC_ALRMXR_HU_SHIFT (16)
+#define RTC_ALRMXR_HU_MASK (0xf)
+#define RTC_ALRMXR_MSK2 (1<<15)
+#define RTC_ALRMXR_MNT_SHIFT (12)
+#define RTC_ALRMXR_MNT_MASK (0x7)
+#define RTC_ALRMXR_MNU_SHIFT (8)
+#define RTC_ALRMXR_MNU_MASK (0xf)
+#define RTC_ALRMXR_MSK1 (1<<7)
+#define RTC_ALRMXR_ST_SHIFT (4)
+#define RTC_ALRMXR_ST_MASK (0x7)
+#define RTC_ALRMXR_SU_SHIFT (0)
+#define RTC_ALRMXR_SU_MASK (0xf)
+
+/* RTC shift control register (RTC_SHIFTR) */
+// FIXME - TODO
+
+/* RTC time stamp time register (RTC_TSTR) bits */
+#define RTC_TSTR_PM (1<<22)
+#define RTC_TSTR_HT_SHIFT (20)
+#define RTC_TSTR_HT_MASK (0x3)
+#define RTC_TSTR_HU_SHIFT (16)
+#define RTC_TSTR_HU_MASK (0xf)
+#define RTC_TSTR_MNT_SHIFT (12)
+#define RTC_TSTR_MNT_MASK (0x7)
+#define RTC_TSTR_MNU_SHIFT (8)
+#define RTC_TSTR_MNU_MASK (0xf)
+#define RTC_TSTR_ST_SHIFT (4)
+#define RTC_TSTR_ST_MASK (0x7)
+#define RTC_TSTR_SU_SHIFT (0)
+#define RTC_TSTR_SU_MASK (0xf)
+
+/* RTC time stamp date register (RTC_TSDR) bits */
+#define RTC_TSDR_WDU_SHIFT (13)
+#define RTC_TSDR_WDU_MASK (0x7)
+#define RTC_TSDR_MT (1<<12)
+#define RTC_TSDR_MU_SHIFT (8)
+#define RTC_TSDR_MU_MASK (0xf)
+#define RTC_TSDR_DT_SHIFT (4)
+#define RTC_TSDR_DT_MASK (0x3)
+#define RTC_TSDR_DU_SHIFT (0)
+#define RTC_TSDR_DU_MASK (0xf)
+
+/* RTC calibration register (RTC_CALR) bits */
+// FIXME - TODO
+
+/* RTC tamper and alternate function configuration register (RTC_TAFCR) bits */
+#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
+#define RTC_TAFCR_TAMPPUDIS (1<<15)
+
+#define RTC_TAFCR_TAMPPRCH_SHIFT (13)
+#define RTC_TAFCR_TAMPPRCH_MASK (0x3)
+#define RTC_TAFCR_TAMPPRCH_1RTC (0x0)
+#define RTC_TAFCR_TAMPPRCH_2RTC (0x1)
+#define RTC_TAFCR_TAMPPRCH_4RTC (0x2)
+#define RTC_TAFCR_TAMPPRCH_8RTC (0x3)
+
+#define RTC_TAFCR_TAMPFLT_SHIFT (11)
+#define RTC_TAFCR_TAMPFLT_MASK (0x3)
+#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0)
+#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1)
+#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2)
+#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3)
+
+#define RTC_TAFCR_TAMPFREQ_SHIFT (8)
+#define RTC_TAFCR_TAMPFREQ_MASK (0x7)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)
+#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7)
+
+#define RTC_TAFCR_TAMPTS (1<<7)
+#define RTC_TAFCR_TAMP3TRG (1<<6)
+#define RTC_TAFCR_TAMP3E (1<<5)
+#define RTC_TAFCR_TAMP2TRG (1<<4)
+#define RTC_TAFCR_TAMP2E (1<<3)
+#define RTC_TAFCR_TAMPIE (1<<2)
+#define RTC_TAFCR_TAMP1TRG (1<<1)
+#define RTC_TAFCR_TAMP1E (1<<0)
+
+/* RTC alarm X sub second register */
+// FIXME - TODO
+
+
+
+BEGIN_DECLS
+
+void rtc_set_prescaler(u32 sync, u32 async);
+void rtc_wait_for_synchro(void);
+void rtc_lock(void);
+void rtc_unlock(void);
+
+END_DECLS
+/**@}*/
+
+#endif /* RTC2_H */
+
diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 4af8f43..e0c55a6 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -34,7 +34,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
-#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dma_common_f13.h>
#endif
diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h
index 919b4d4..fef1257 100644
--- a/include/libopencm3/stm32/f1/flash.h
+++ b/include/libopencm3/stm32/f1/flash.h
@@ -44,48 +44,48 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_PRFTBS (1 << 5)
-#define FLASH_PRFTBE (1 << 4)
-#define FLASH_HLFCYA (1 << 3)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
+#define FLASH_ACR_PRFTBS (1 << 5)
+#define FLASH_ACR_PRFTBE (1 << 4)
+#define FLASH_ACR_HLFCYA (1 << 3)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_EOP (1 << 5)
-#define FLASH_WRPRTERR (1 << 4)
-#define FLASH_PGERR (1 << 2)
-#define FLASH_BSY (1 << 0)
+#define FLASH_SR_EOP (1 << 5)
+#define FLASH_SR_WRPRTERR (1 << 4)
+#define FLASH_SR_PGERR (1 << 2)
+#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_EOPIE (1 << 12)
-#define FLASH_ERRIE (1 << 10)
-#define FLASH_OPTWRE (1 << 9)
-#define FLASH_LOCK (1 << 7)
-#define FLASH_STRT (1 << 6)
-#define FLASH_OPTER (1 << 5)
-#define FLASH_OPTPG (1 << 4)
-#define FLASH_MER (1 << 2)
-#define FLASH_PER (1 << 1)
-#define FLASH_PG (1 << 0)
+#define FLASH_CR_EOPIE (1 << 12)
+#define FLASH_CR_ERRIE (1 << 10)
+#define FLASH_CR_OPTWRE (1 << 9)
+#define FLASH_CR_LOCK (1 << 7)
+#define FLASH_CR_STRT (1 << 6)
+#define FLASH_CR_OPTER (1 << 5)
+#define FLASH_CR_OPTPG (1 << 4)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_PER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
-#define FLASH_NRST_STDBY (1 << 4)
-#define FLASH_NRST_STOP (1 << 3)
-#define FLASH_WDG_SW (1 << 2)
-#define FLASH_RDPRT (1 << 1)
-#define FLASH_OPTERR (1 << 0)
+#define FLASH_OBR_NRST_STDBY (1 << 4)
+#define FLASH_OBR_NRST_STOP (1 << 3)
+#define FLASH_OBR_WDG_SW (1 << 2)
+#define FLASH_OBR_RDPRT (1 << 1)
+#define FLASH_OBR_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define RDP_KEY ((u16)0x00a5)
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
+#define FLASH_RDP_KEY ((u16)0x00a5)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/pwr.h b/include/libopencm3/stm32/f1/pwr.h
new file mode 100644
index 0000000..2875492
--- /dev/null
+++ b/include/libopencm3/stm32/f1/pwr.h
@@ -0,0 +1,40 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index 04aea01..a8a8966 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -17,6 +17,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ * The F1 RTC is a straight timestamp, a completely different peripheral to
+ * that found in the F2, F3, F4, L1 and F0.
+ */
+
#ifndef LIBOPENCM3_RTC_H
#define LIBOPENCM3_RTC_H
diff --git a/include/libopencm3/stm32/f2/dma.h b/include/libopencm3/stm32/f2/dma.h
index 8226f55..0eb952c 100644
--- a/include/libopencm3/stm32/f2/dma.h
+++ b/include/libopencm3/stm32/f2/dma.h
@@ -34,7 +34,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
-#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dma_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f2/flash.h b/include/libopencm3/stm32/f2/flash.h
index 2c78757..3e6816f 100644
--- a/include/libopencm3/stm32/f2/flash.h
+++ b/include/libopencm3/stm32/f2/flash.h
@@ -43,76 +43,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_DCRST (1 << 12)
-#define FLASH_ICRST (1 << 11)
-#define FLASH_DCE (1 << 10)
-#define FLASH_ICE (1 << 9)
-#define FLASH_PRFTEN (1 << 8)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
-#define FLASH_LATENCY_3WS 0x03
-#define FLASH_LATENCY_4WS 0x04
-#define FLASH_LATENCY_5WS 0x05
-#define FLASH_LATENCY_6WS 0x06
-#define FLASH_LATENCY_7WS 0x07
+#define FLASH_ACR_DCRST (1 << 12)
+#define FLASH_ACR_ICRST (1 << 11)
+#define FLASH_ACR_DCE (1 << 10)
+#define FLASH_ACR_ICE (1 << 9)
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
+#define FLASH_ACR_LATENCY_3WS 0x03
+#define FLASH_ACR_LATENCY_4WS 0x04
+#define FLASH_ACR_LATENCY_5WS 0x05
+#define FLASH_ACR_LATENCY_6WS 0x06
+#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7)
-#define FLASH_PGPERR (1 << 6)
-#define FLASH_PGAERR (1 << 5)
-#define FLASH_WRPERR (1 << 4)
-#define FLASH_OPERR (1 << 1)
-#define FLASH_EOP (1 << 0)
+#define FLASH_SR_BSY (1 << 16)
+#define FLASH_SR_PGSERR (1 << 7)
+#define FLASH_SR_PGPERR (1 << 6)
+#define FLASH_SR_PGAERR (1 << 5)
+#define FLASH_SR_WRPERR (1 << 4)
+#define FLASH_SR_OPERR (1 << 1)
+#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_LOCK (1 << 31)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_STRT (1 << 16)
-#define FLASH_MER (1 << 2)
-#define FLASH_SER (1 << 1)
-#define FLASH_PG (1 << 0)
-#define FLASH_SECTOR_0 (0x00 << 3)
-#define FLASH_SECTOR_1 (0x01 << 3)
-#define FLASH_SECTOR_2 (0x02 << 3)
-#define FLASH_SECTOR_3 (0x03 << 3)
-#define FLASH_SECTOR_4 (0x04 << 3)
-#define FLASH_SECTOR_5 (0x05 << 3)
-#define FLASH_SECTOR_6 (0x06 << 3)
-#define FLASH_SECTOR_7 (0x07 << 3)
-#define FLASH_SECTOR_8 (0x08 << 3)
-#define FLASH_SECTOR_9 (0x09 << 3)
-#define FLASH_SECTOR_10 (0x0a << 3)
-#define FLASH_SECTOR_11 (0x0b << 3)
-#define FLASH_PROGRAM_X8 (0x00 << 8)
-#define FLASH_PROGRAM_X16 (0x01 << 8)
-#define FLASH_PROGRAM_X32 (0x02 << 8)
-#define FLASH_PROGRAM_X64 (0x03 << 8)
+#define FLASH_CR_LOCK (1 << 31)
+#define FLASH_CR_ERRIE (1 << 25)
+#define FLASH_CR_EOPIE (1 << 24)
+#define FLASH_CR_STRT (1 << 16)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_SER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
+#define FLASH_CR_SECTOR_0 (0x00 << 3)
+#define FLASH_CR_SECTOR_1 (0x01 << 3)
+#define FLASH_CR_SECTOR_2 (0x02 << 3)
+#define FLASH_CR_SECTOR_3 (0x03 << 3)
+#define FLASH_CR_SECTOR_4 (0x04 << 3)
+#define FLASH_CR_SECTOR_5 (0x05 << 3)
+#define FLASH_CR_SECTOR_6 (0x06 << 3)
+#define FLASH_CR_SECTOR_7 (0x07 << 3)
+#define FLASH_CR_SECTOR_8 (0x08 << 3)
+#define FLASH_CR_SECTOR_9 (0x09 << 3)
+#define FLASH_CR_SECTOR_10 (0x0a << 3)
+#define FLASH_CR_SECTOR_11 (0x0b << 3)
+#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
+#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
+#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
+#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
-#define FLASH_NRST_STDBY (1 << 7)
-#define FLASH_NRST_STOP (1 << 6)
-#define FLASH_WDG_SW (1 << 5)
-#define FLASH_OPTSTRT (1 << 1)
-#define FLASH_OPTLOCK (1 << 0)
-#define FLASH_BOR_LEVEL_3 (0x00 << 2)
-#define FLASH_BOR_LEVEL_2 (0x01 << 2)
-#define FLASH_BOR_LEVEL_1 (0x02 << 2)
-#define FLASH_BOR_OFF (0x03 << 2)
+#define FLASH_OPTCR_NRST_STDBY (1 << 7)
+#define FLASH_OPTCR_NRST_STOP (1 << 6)
+#define FLASH_OPTCR_WDG_SW (1 << 5)
+#define FLASH_OPTCR_OPTSTRT (1 << 1)
+#define FLASH_OPTCR_OPTLOCK (1 << 0)
+#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
-#define FLASH_OPTKEY1 ((u32)0x08192a3b)
-#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h
index 4ffa242..1af6ccf 100644
--- a/include/libopencm3/stm32/f2/rcc.h
+++ b/include/libopencm3/stm32/f2/rcc.h
@@ -426,7 +426,7 @@
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
-#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
diff --git a/include/libopencm3/stm32/f2/rng.h b/include/libopencm3/stm32/f2/rng.h
index 63d03fe..403c7c7 100644
--- a/include/libopencm3/stm32/f2/rng.h
+++ b/include/libopencm3/stm32/f2/rng.h
@@ -18,7 +18,7 @@
#ifndef LIBOPENCM3_RNG_F2_H
#define LIBOPENCM3_RNG_F2_H
-#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/rng_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f2/rtc.h b/include/libopencm3/stm32/f2/rtc.h
new file mode 100644
index 0000000..ebc0936
--- /dev/null
+++ b/include/libopencm3/stm32/f2/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx RTC</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h
index 272c4c2..e400591 100644
--- a/include/libopencm3/stm32/f4/adc.h
+++ b/include/libopencm3/stm32/f4/adc.h
@@ -36,7 +36,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H
-#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f4/dma.h b/include/libopencm3/stm32/f4/dma.h
index cc97024..a3e9db1 100644
--- a/include/libopencm3/stm32/f4/dma.h
+++ b/include/libopencm3/stm32/f4/dma.h
@@ -34,7 +34,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
-#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dma_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f4/flash.h b/include/libopencm3/stm32/f4/flash.h
index 2221333..8e7ed30 100644
--- a/include/libopencm3/stm32/f4/flash.h
+++ b/include/libopencm3/stm32/f4/flash.h
@@ -42,76 +42,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_DCRST (1 << 12)
-#define FLASH_ICRST (1 << 11)
-#define FLASH_DCE (1 << 10)
-#define FLASH_ICE (1 << 9)
-#define FLASH_PRFTEN (1 << 8)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
-#define FLASH_LATENCY_2WS 0x02
-#define FLASH_LATENCY_3WS 0x03
-#define FLASH_LATENCY_4WS 0x04
-#define FLASH_LATENCY_5WS 0x05
-#define FLASH_LATENCY_6WS 0x06
-#define FLASH_LATENCY_7WS 0x07
+#define FLASH_ACR_DCRST (1 << 12)
+#define FLASH_ACR_ICRST (1 << 11)
+#define FLASH_ACR_DCE (1 << 10)
+#define FLASH_ACR_ICE (1 << 9)
+#define FLASH_ACR_PRFTEN (1 << 8)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
+#define FLASH_ACR_LATENCY_2WS 0x02
+#define FLASH_ACR_LATENCY_3WS 0x03
+#define FLASH_ACR_LATENCY_4WS 0x04
+#define FLASH_ACR_LATENCY_5WS 0x05
+#define FLASH_ACR_LATENCY_6WS 0x06
+#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7)
-#define FLASH_PGPERR (1 << 6)
-#define FLASH_PGAERR (1 << 5)
-#define FLASH_WRPERR (1 << 4)
-#define FLASH_OPERR (1 << 1)
-#define FLASH_EOP (1 << 0)
+#define FLASH_SR_BSY (1 << 16)
+#define FLASH_SR_PGSERR (1 << 7)
+#define FLASH_SR_PGPERR (1 << 6)
+#define FLASH_SR_PGAERR (1 << 5)
+#define FLASH_SR_WRPERR (1 << 4)
+#define FLASH_SR_OPERR (1 << 1)
+#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
-#define FLASH_LOCK (1 << 31)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_STRT (1 << 16)
-#define FLASH_MER (1 << 2)
-#define FLASH_SER (1 << 1)
-#define FLASH_PG (1 << 0)
-#define FLASH_SECTOR_0 (0x00 << 3)
-#define FLASH_SECTOR_1 (0x01 << 3)
-#define FLASH_SECTOR_2 (0x02 << 3)
-#define FLASH_SECTOR_3 (0x03 << 3)
-#define FLASH_SECTOR_4 (0x04 << 3)
-#define FLASH_SECTOR_5 (0x05 << 3)
-#define FLASH_SECTOR_6 (0x06 << 3)
-#define FLASH_SECTOR_7 (0x07 << 3)
-#define FLASH_SECTOR_8 (0x08 << 3)
-#define FLASH_SECTOR_9 (0x09 << 3)
-#define FLASH_SECTOR_10 (0x0a << 3)
-#define FLASH_SECTOR_11 (0x0b << 3)
-#define FLASH_PROGRAM_X8 (0x00 << 8)
-#define FLASH_PROGRAM_X16 (0x01 << 8)
-#define FLASH_PROGRAM_X32 (0x02 << 8)
-#define FLASH_PROGRAM_X64 (0x03 << 8)
+#define FLASH_CR_LOCK (1 << 31)
+#define FLASH_CR_ERRIE (1 << 25)
+#define FLASH_CR_EOPIE (1 << 24)
+#define FLASH_CR_STRT (1 << 16)
+#define FLASH_CR_MER (1 << 2)
+#define FLASH_CR_SER (1 << 1)
+#define FLASH_CR_PG (1 << 0)
+#define FLASH_CR_SECTOR_0 (0x00 << 3)
+#define FLASH_CR_SECTOR_1 (0x01 << 3)
+#define FLASH_CR_SECTOR_2 (0x02 << 3)
+#define FLASH_CR_SECTOR_3 (0x03 << 3)
+#define FLASH_CR_SECTOR_4 (0x04 << 3)
+#define FLASH_CR_SECTOR_5 (0x05 << 3)
+#define FLASH_CR_SECTOR_6 (0x06 << 3)
+#define FLASH_CR_SECTOR_7 (0x07 << 3)
+#define FLASH_CR_SECTOR_8 (0x08 << 3)
+#define FLASH_CR_SECTOR_9 (0x09 << 3)
+#define FLASH_CR_SECTOR_10 (0x0a << 3)
+#define FLASH_CR_SECTOR_11 (0x0b << 3)
+#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
+#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
+#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
+#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
-#define FLASH_NRST_STDBY (1 << 7)
-#define FLASH_NRST_STOP (1 << 6)
-#define FLASH_WDG_SW (1 << 5)
-#define FLASH_OPTSTRT (1 << 1)
-#define FLASH_OPTLOCK (1 << 0)
-#define FLASH_BOR_LEVEL_3 (0x00 << 2)
-#define FLASH_BOR_LEVEL_2 (0x01 << 2)
-#define FLASH_BOR_LEVEL_1 (0x02 << 2)
-#define FLASH_BOR_OFF (0x03 << 2)
+#define FLASH_OPTCR_NRST_STDBY (1 << 7)
+#define FLASH_OPTCR_NRST_STOP (1 << 6)
+#define FLASH_OPTCR_WDG_SW (1 << 5)
+#define FLASH_OPTCR_OPTSTRT (1 << 1)
+#define FLASH_OPTCR_OPTLOCK (1 << 0)
+#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
+#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
+#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xcdef89ab)
-#define FLASH_OPTKEY1 ((u32)0x08192a3b)
-#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
+#define FLASH_KEYR_KEY1 ((u32)0x45670123)
+#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
+#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h
index 25fb163..c9b27fd 100644
--- a/include/libopencm3/stm32/f4/pwr.h
+++ b/include/libopencm3/stm32/f4/pwr.h
@@ -1,3 +1,15 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -17,10 +29,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_PWR_F4_H
-#define LIBOPENCM3_PWR_F4_H
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
-#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
/*
* This file extends the common STM32 version with definitions only
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 1688584..a718903 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -427,7 +427,7 @@
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
-#define RCC_CSR_BORRSTF (1 << 26)
+#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
diff --git a/include/libopencm3/stm32/f4/rng.h b/include/libopencm3/stm32/f4/rng.h
index b72f801..e8e6cc4 100644
--- a/include/libopencm3/stm32/f4/rng.h
+++ b/include/libopencm3/stm32/f4/rng.h
@@ -18,7 +18,7 @@
#ifndef LIBOPENCM3_RNG_F4_H
#define LIBOPENCM3_RNG_F4_H
-#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/rng_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f4/rtc.h b/include/libopencm3/stm32/f4/rtc.h
new file mode 100644
index 0000000..ab8d3ee
--- /dev/null
+++ b/include/libopencm3/stm32/f4/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx RTC</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h
index ed0a696..724fec9 100644
--- a/include/libopencm3/stm32/l1/flash.h
+++ b/include/libopencm3/stm32/l1/flash.h
@@ -33,10 +33,10 @@
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
-#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
-#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
-#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
-#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
+#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
+#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
+#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
+#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c)
#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
@@ -45,70 +45,70 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
-#define FLASH_RUNPD (1 << 4)
-#define FLASH_SLEEPPD (1 << 3)
-#define FLASH_ACC64 (1 << 2)
-#define FLASH_PRFTEN (1 << 1)
-#define FLASH_LATENCY_0WS 0x00
-#define FLASH_LATENCY_1WS 0x01
+#define FLASH_ACR_RUNPD (1 << 4)
+#define FLASH_ACR_SLEEPPD (1 << 3)
+#define FLASH_ACR_ACC64 (1 << 2)
+#define FLASH_ACR_PRFTEN (1 << 1)
+#define FLASH_ACR_LATENCY_0WS 0x00
+#define FLASH_ACR_LATENCY_1WS 0x01
/* --- FLASH_PECR values. Program/erase control register */
-#define FLASH_OBL_LAUNCH (1 << 18)
-#define FLASH_ERRIE (1 << 17)
-#define FLASH_EOPIE (1 << 16)
-#define FLASH_PARALLBANK (1 << 15)
-#define FLASH_FPRG (1 << 10)
-#define FLASH_ERASE (1 << 9)
-#define FLASH_FTDW (1 << 8)
-#define FLASH_FTDW (1 << 8)
-#define FLASH_DATA (1 << 4)
-#define FLASH_PROG (1 << 3)
-#define FLASH_OPTLOCK (1 << 2)
-#define FLASH_PRGLOCK (1 << 1)
-#define FLASH_PELOCK (1 << 0)
+#define FLASH_PECR_OBL_LAUNCH (1 << 18)
+#define FLASH_PECR_ERRIE (1 << 17)
+#define FLASH_PECR_EOPIE (1 << 16)
+#define FLASH_PECR_PARALLBANK (1 << 15)
+#define FLASH_PECR_FPRG (1 << 10)
+#define FLASH_PECR_ERASE (1 << 9)
+#define FLASH_PECR_FTDW (1 << 8)
+#define FLASH_PECR_FTDW (1 << 8)
+#define FLASH_PECR_DATA (1 << 4)
+#define FLASH_PECR_PROG (1 << 3)
+#define FLASH_PECR_OPTLOCK (1 << 2)
+#define FLASH_PECR_PRGLOCK (1 << 1)
+#define FLASH_PECR_PELOCK (1 << 0)
/* Power down key register (FLASH_PDKEYR) */
-#define FLASH_PDKEY1 ((u32)0x04152637)
-#define FLASH_PDKEY2 ((u32)0xFAFBFCFD)
+#define FLASH_PDKEYR_PDKEY1 ((u32)0x04152637)
+#define FLASH_PDKEYR_PDKEY2 ((u32)0xFAFBFCFD)
/* Program/erase key register (FLASH_PEKEYR) */
-#define FLASH_PEKEY1 ((u32)0x89ABCDEF)
-#define FLASH_PEKEY2 ((u32)0x02030405)
+#define FLASH_PEKEYR_PEKEY1 ((u32)0x89ABCDEF)
+#define FLASH_PEKEYR_PEKEY2 ((u32)0x02030405)
/* Program memory key register (FLASH_PRGKEYR) */
-#define FLASH_PRGKEY1 ((u32)0x8C9DAEBF)
-#define FLASH_PRGKEY2 ((u32)0x13141516)
+#define FLASH_PRGKEYR_PRGKEY1 ((u32)0x8C9DAEBF)
+#define FLASH_PRGKEYR_PRGKEY2 ((u32)0x13141516)
/* Option byte key register (FLASH_OPTKEYR) */
-#define FLASH_OPTKEY1 ((u32)0xFBEAD9C8)
-#define FLASH_OPTKEY2 ((u32)0x24252627)
+#define FLASH_OPTKEYR_OPTKEY1 ((u32)0xFBEAD9C8)
+#define FLASH_OPTKEYR_OPTKEY2 ((u32)0x24252627)
/* --- FLASH_SR values ----------------------------------------------------- */
-#define FLASH_OPTVERRUSR (1 << 12)
-#define FLASH_OPTVERR (1 << 11)
-#define FLASH_SIZEERR (1 << 10)
-#define FLASH_PGAERR (1 << 9)
-#define FLASH_WRPERR (1 << 8)
-#define FLASH_READY (1 << 3)
-#define FLASH_ENDHV (1 << 2)
-#define FLASH_EOP (1 << 1)
-#define FLASH_BSY (1 << 0)
+#define FLASH_SR_OPTVERRUSR (1 << 12)
+#define FLASH_SR_OPTVERR (1 << 11)
+#define FLASH_SR_SIZEERR (1 << 10)
+#define FLASH_SR_PGAERR (1 << 9)
+#define FLASH_SR_WRPERR (1 << 8)
+#define FLASH_SR_READY (1 << 3)
+#define FLASH_SR_ENDHV (1 << 2)
+#define FLASH_SR_EOP (1 << 1)
+#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_OBR values ----------------------------------------------------- */
-#define FLASH_BFB2 (1 << 23)
-#define FLASH_NRST_STDBY (1 << 22)
-#define FLASH_NRST_STOP (1 << 21)
-#define FLASH_IWDG_SW (1 << 20)
-#define FLASH_BOR_OFF (0x0 << 16)
-#define FLASH_BOR_LEVEL_1 (0x8 << 16)
-#define FLASH_BOR_LEVEL_2 (0x9 << 16)
-#define FLASH_BOR_LEVEL_3 (0xa << 16)
-#define FLASH_BOR_LEVEL_4 (0xb << 16)
-#define FLASH_BOR_LEVEL_5 (0xc << 16)
-#define FLASH_RDPRT_LEVEL_0 (0xaa)
-#define FLASH_RDPRT_LEVEL_1 (0x00)
-#define FLASH_RDPRT_LEVEL_2 (0xcc)
+#define FLASH_OBR_BFB2 (1 << 23)
+#define FLASH_OBR_NRST_STDBY (1 << 22)
+#define FLASH_OBR_NRST_STOP (1 << 21)
+#define FLASH_OBR_IWDG_SW (1 << 20)
+#define FLASH_OBR_BOR_OFF (0x0 << 16)
+#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16)
+#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16)
+#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16)
+#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16)
+#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16)
+#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa)
+#define FLASH_OBR_RDPRT_LEVEL_1 (0x00)
+#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc)
/* --- Function prototypes ------------------------------------------------- */
diff --git a/include/libopencm3/stm32/l1/irq.yaml b/include/libopencm3/stm32/l1/irq.yaml
index c2f118f..a10e96c 100644
--- a/include/libopencm3/stm32/l1/irq.yaml
+++ b/include/libopencm3/stm32/l1/irq.yaml
@@ -4,8 +4,8 @@ partname_doxygen: STM32L1
irqs:
- wwdg
- pvd
- - tamper
- - rtc
+ - tamper_stamp
+ - rtc_wkup
- flash
- rcc
- exti0
@@ -44,6 +44,19 @@ irqs:
- usart3
- exti15_10
- rtc_alarm
- - usb_wakeup
+ - usb_fs_wakeup
- tim6
- tim7
+ # below here is medium+/high density
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - dma2_ch1
+ - dma2_ch2
+ - dma2_ch3
+ - dma2_ch4
+ - dma2_ch5
+ - aes
+ - comp_acq \ No newline at end of file
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
index d89dbd6..60f1c57 100644
--- a/include/libopencm3/stm32/l1/memorymap.h
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -47,7 +47,6 @@
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
-// datasheet has an error? here
#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
@@ -61,6 +60,7 @@
/* gap */
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
@@ -85,13 +85,16 @@
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
/* gap */
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
/* gap */
#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
/* gap */
-#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
/* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
diff --git a/include/libopencm3/stm32/l1/pwr.h b/include/libopencm3/stm32/l1/pwr.h
index 309b464..e976d46 100644
--- a/include/libopencm3/stm32/l1/pwr.h
+++ b/include/libopencm3/stm32/l1/pwr.h
@@ -1,3 +1,18 @@
+/** @defgroup pwr_defines PWR Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
+@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
/*
* This file is part of the libopencm3 project.
*
@@ -18,10 +33,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_PWR_L1_H
-#define LIBOPENCM3_PWR_L1_H
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
-#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/pwr_common_all.h>
/*
* This file extends the common STM32 version with definitions only
@@ -53,6 +69,9 @@
/* ULP: Ultralow power mode */
#define PWR_CR_ULP (1 << 9)
+/* LPSDSR: Low-power deepsleep/sleep/low power run */
+#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
+
/* --- PWR_CSR values ------------------------------------------------------- */
/* Bits [31:11]: Reserved */
diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h
index 21b073b..4dc5102 100644
--- a/include/libopencm3/stm32/l1/rcc.h
+++ b/include/libopencm3/stm32/l1/rcc.h
@@ -46,7 +46,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
-#include <libopencm3/stm32/l1/pwr.h>
+#include <libopencm3/stm32/pwr.h>
/* --- RCC registers ------------------------------------------------------- */
@@ -82,11 +82,31 @@ LGPL License Terms @ref lgpl_license
#define RCC_CR_RTCPRE_DIV2 0
#define RCC_CR_RTCPRE_DIV4 1
#define RCC_CR_RTCPRE_DIV8 2
-#define RCC_CR_RTCPRE_DIV18 3
+#define RCC_CR_RTCPRE_DIV16 3
+#define RCC_CR_RTCPRE_SHIFT 29
+#define RCC_CR_RTCPRE_MASK 0x3
/* --- RCC_ICSCR values ---------------------------------------------------- */
-// TODO
+#define RCC_ICSCR_MSITRIM_SHIFT 24
+#define RCC_ICSCR_MSITRIM_MASK 0xff
+#define RCC_ICSCR_MSICAL_SHIFT 16
+#define RCC_ICSCR_MSICAL_MASK 0xff
+
+#define RCC_ICSCR_MSIRANGE_SHIFT 13
+#define RCC_ICSCR_MSIRANGE_MASK 0x7
+#define RCC_ICSCR_MSIRANGE_65KHZ 0x0
+#define RCC_ICSCR_MSIRANGE_131KHZ 0x1
+#define RCC_ICSCR_MSIRANGE_262KHZ 0x2
+#define RCC_ICSCR_MSIRANGE_524KHZ 0x3
+#define RCC_ICSCR_MSIRANGE_1MHZ 0x4
+#define RCC_ICSCR_MSIRANGE_2MHZ 0x5
+#define RCC_ICSCR_MSIRANGE_4MHZ 0x6
+
+#define RCC_ICSCR_HSITRIM_SHIFT 8
+#define RCC_ICSCR_HSITRIM_MASK 0x1f
+#define RCC_ICSCR_HSICAL_SHIFT 0
+#define RCC_ICSCR_HSICAL_MASK 0xff
/* --- RCC_CFGR values ----------------------------------------------------- */
@@ -347,7 +367,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_RTCRST (1 << 23)
#define RCC_CSR_RTCEN (1 << 22)
-/* RTCSEL[1:0] */
+#define RCC_CSR_RTCSEL_SHIFT (16)
+#define RCC_CSR_RTCSEL_MASK (0x3)
+#define RCC_CSR_RTCSEL_NONE (0x0)
+#define RCC_CSR_RTCSEL_LSE (0x1)
+#define RCC_CSR_RTCSEL_LSI (0x2)
+#define RCC_CSR_RTCSEL_HSI (0x3)
+#define RCC_CSR_LSECSSD (1 << 12)
+#define RCC_CSR_LSECSSON (1 << 11)
#define RCC_CSR_LSEBYP (1 << 10)
#define RCC_CSR_LSERDY (1 << 9)
#define RCC_CSR_LSEON (1 << 8)
@@ -365,16 +392,20 @@ typedef struct {
vos_scale_t voltage_scale;
uint32_t apb1_frequency;
uint32_t apb2_frequency;
+ uint8_t msi_range;
} clock_scale_t;
typedef enum {
CLOCK_VRANGE1_HSI_PLL_24MHZ,
CLOCK_VRANGE1_HSI_PLL_32MHZ,
CLOCK_VRANGE1_HSI_RAW_16MHZ,
- CLOCK_VRANGE1_END
-} clock_volt_range1_t;
+ CLOCK_VRANGE1_HSI_RAW_4MHZ,
+ CLOCK_VRANGE1_MSI_RAW_4MHZ,
+ CLOCK_VRANGE1_MSI_RAW_2MHZ,
+ CLOCK_CONFIG_END
+} clock_config_entry_t;
-extern const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END];
+extern const clock_scale_t clock_config[CLOCK_CONFIG_END];
/* --- Variable definitions ------------------------------------------------ */
@@ -413,6 +444,8 @@ void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
+void rcc_rtc_select_clock(u32 clock);
+void rcc_clock_setup_msi(const clock_scale_t *clock);
void rcc_clock_setup_hsi(const clock_scale_t *clock);
void rcc_clock_setup_pll(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
diff --git a/include/libopencm3/stm32/l1/rtc.h b/include/libopencm3/stm32/l1/rtc.h
new file mode 100644
index 0000000..d364fb5
--- /dev/null
+++ b/include/libopencm3/stm32/l1/rtc.h
@@ -0,0 +1,39 @@
+/** @defgroup rtc_defines RTC Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx RTC</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
+
+#endif \ No newline at end of file
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
index 34b2407..1d907a9 100644
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -1,22 +1,8 @@
-/** @defgroup STM32F_pwr_defines PWR Defines
+/* This provides unification of code over STM32F subfamilies */
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 STM32F Power Control</b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 17 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_PWR_H
-#define LIBOPENCM3_PWR_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- PWR registers ------------------------------------------------------- */
-
-/* Power control register (PWR_CR) */
-#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
-
-/* Power control/status register (PWR_CSR) */
-#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
-
-/* --- PWR_CR values ------------------------------------------------------- */
-
-/* Bits [31:9]: Reserved, must be kept at reset value. */
-
-/* DBP: Disable backup domain write protection */
-#define PWR_CR_DBP (1 << 8)
-
-/* PLS[7:5]: PVD level selection */
-#define PWR_CR_PLS_LSB 5
-/** @defgroup pwr_pls PVD level selection
-@ingroup STM32F_pwr_defines
-
-@{*/
-#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
-#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
-/**@}*/
-#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
-
-/* PVDE: Power voltage detector enable */
-#define PWR_CR_PVDE (1 << 4)
-
-/* CSBF: Clear standby flag */
-#define PWR_CR_CSBF (1 << 3)
-
-/* CWUF: Clear wakeup flag */
-#define PWR_CR_CWUF (1 << 2)
-
-/* PDDS: Power down deepsleep */
-#define PWR_CR_PDDS (1 << 1)
-
-/* LPDS: Low-power deepsleep */
-#define PWR_CR_LPDS (1 << 0)
-
-/* --- PWR_CSR values ------------------------------------------------------ */
-
-/* Bits [31:9]: Reserved, must be kept at reset value. */
-
-/* EWUP: Enable WKUP pin */
-#define PWR_CSR_EWUP (1 << 8)
-
-/* Bits [7:3]: Reserved, must be kept at reset value. */
-
-/* PVDO: PVD output */
-#define PWR_CSR_PVDO (1 << 2)
-
-/* SBF: Standby flag */
-#define PWR_CSR_SBF (1 << 1)
-
-/* WUF: Wakeup flag */
-#define PWR_CSR_WUF (1 << 0)
-
-/* --- PWR function prototypes ------------------------------------------- */
-
-BEGIN_DECLS
-
-void pwr_disable_backup_domain_write_protect(void);
-void pwr_enable_backup_domain_write_protect(void);
-void pwr_enable_power_voltage_detect(u32 pvd_level);
-void pwr_disable_power_voltage_detect(void);
-void pwr_clear_standby_flag(void);
-void pwr_clear_wakeup_flag(void);
-void pwr_set_standby_mode(void);
-void pwr_set_stop_mode(void);
-void pwr_voltage_regulator_on_in_stop(void);
-void pwr_voltage_regulator_low_power_in_stop(void);
-void pwr_enable_wakeup_pin(void);
-void pwr_disable_wakeup_pin(void);
-bool pwr_voltage_high(void);
-bool pwr_get_standby_flag(void);
-bool pwr_get_wakeup_flag(void);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/pwr.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/pwr.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/pwr.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/pwr.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/rtc.h b/include/libopencm3/stm32/rtc.h
new file mode 100644
index 0000000..a927dd8
--- /dev/null
+++ b/include/libopencm3/stm32/rtc.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32 subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/rtc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/rtc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/rtc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/rtc.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c
index f7b0f5c..3cfd4f5 100644
--- a/lib/cm3/vector.c
+++ b/lib/cm3/vector.c
@@ -67,8 +67,6 @@ void WEAK __attribute__ ((naked)) reset_handler(void)
{
volatile unsigned *src, *dest;
- __asm__("MSR msp, %0" : : "r"(&_stack));
-
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
diff --git a/lib/lm4f/Makefile b/lib/lm4f/Makefile
index 8f4c151..a3b7dce 100644
--- a/lib/lm4f/Makefile
+++ b/lib/lm4f/Makefile
@@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DLM4F
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = gpio.o vector.o assert.o
+OBJS = gpio.o vector.o assert.o systemcontrol.o rcc.o
VPATH += ../cm3
diff --git a/lib/lm4f/rcc.c b/lib/lm4f/rcc.c
new file mode 100644
index 0000000..48eb2a2
--- /dev/null
+++ b/lib/lm4f/rcc.c
@@ -0,0 +1,493 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/**
+ * @defgroup rcc_file RCC
+ *
+ * @ingroup LM4F
+ *
+ * \brief <b>libopencm3 LM4F Clock control API</b>
+ *
+ * The LM$F clock API provides functionaliity for manipulating the system clock,
+ * oscillator, and PLL. Functions are provided for fine-grained control of clock
+ * control registers, while also providing higher level functionality to easily
+ * configure the main system clock source.
+ *
+ * The following code snippet uses fine-grained mechanisms to configures the
+ * chip to run off an external 16MHz crystal, and use the PLL to derive a clock
+ * frequency of 80MHz.
+ * @code{.c}
+ * // A divisor of 5 gives us a clock of 400/5 = 80MHz
+ * #define PLLDIV_80MHZ 5
+ *
+ * // Enable the main oscillator
+ * rcc_enable_main_osc();
+ *
+ * // Make RCC2 override RCC
+ * rcc_enable_rcc2();
+ *
+ * // Set XTAL value to 16MHz
+ * rcc_configure_xtal(XTAL_16M);
+ * // Set the oscillator source as the main oscillator
+ * rcc_set_osc_source(OSCSRC_MOSC);
+ * // Enable the PLL
+ * rcc_pll_on();
+ *
+ * // Change the clock divisor
+ * rcc_set_pll_divisor(PLLDIV_80MHZ);
+ *
+ * // We cannot use the PLL as a clock source until it locks
+ * rcc_wait_for_pll_ready();
+ * // Disable PLL bypass to derive the system clock from the PLL clock
+ * rcc_pll_bypass_disable();
+ *
+ * // Keep track of frequency
+ * lm4f_rcc_sysclk_freq = 80E6;
+ * @endcode
+ *
+ * The same can be achieved by a simple call to high-level routines:
+ * @code
+ * // A divisor of 5 gives us a clock of 400/5 = 80MHz
+ * #define PLLDIV_80MHZ 5
+ *
+ * rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLLDIV_80MHZ);
+ * @endcode
+ *
+ * @{
+ */
+
+#include <libopencm3/lm4f/rcc.h>
+
+/**
+ * @defgroup rcc_low_level Low-level clock control API
+ * @{
+ */
+/**
+ * \brief System clock frequency
+ *
+ * This variable is provided to keep track of the system clock frequency. It
+ * should be updated every time the system clock is changed via the fine-grained
+ * mechanisms. The initial value is 16MHz, which corresponds to the clock of the
+ * internal 16MHz oscillator.
+ *
+ * High-level routines update the system clock automatically.
+ * For read access, it is recommended to acces this variable via
+ * @code
+ * rcc_get_system_clock_frequency();
+ * @endcode
+ *
+ * If write access is desired (i.e. when changing the system clock via the
+ * fine-grained mechanisms), then include the following line in your code:
+ * @code
+ * extern u32 lm4f_rcc_sysclk_freq;
+ * @endcode
+ */
+u32 lm4f_rcc_sysclk_freq = 16000000;
+
+
+/**
+ * \brief Configure the crystal type connected to the device.
+ *
+ * Configure the crystal type connected between the OSCO and OSCI pins by
+ * writing the appropriate value to the XTAL field in SYSCTL_RCC. The PLL
+ * parameters are automatically adjusted in hardware to provide a PLL clock of
+ * 400MHz.
+ *
+ * @param[in] xtal predefined crystal type @see xtal_t
+ */
+void rcc_configure_xtal(xtal_t xtal)
+{
+ u32 reg32;
+
+ reg32 = SYSCTL_RCC;
+ reg32 &= ~SYSCTL_RCC_XTAL_MASK;
+ reg32 |= (xtal & SYSCTL_RCC_XTAL_MASK);
+ SYSCTL_RCC = reg32;
+}
+
+/**
+ * \brief Disable the main oscillator
+ *
+ * Sets the IOSCDIS bit in SYSCTL_RCC, disabling the main oscillator.
+ */
+void rcc_disable_main_osc(void)
+{
+ SYSCTL_RCC |= SYSCTL_RCC_MOSCDIS;
+}
+
+/**
+ * \brief Disable the internal oscillator
+ *
+ * Sets the IOSCDIS bit in SYSCTL_RCC, disabling the internal oscillator.
+ */
+void rcc_disable_interal_osc(void)
+{
+ SYSCTL_RCC |= SYSCTL_RCC_IOSCDIS;
+}
+
+/**
+ * \brief Enable the main oscillator
+ *
+ * Clears the MOSCDIS bit in SYSCTL_RCC, enabling the main oscillator.
+ */
+void rcc_enable_main_osc(void)
+{
+ SYSCTL_RCC &= ~SYSCTL_RCC_MOSCDIS;
+}
+
+/**
+ * \brief Enable the internal oscillator
+ *
+ * Clears the IOSCDIS bit in SYSCTL_RCC, enabling the internal oscillator.
+ */
+void rcc_enable_interal_osc(void)
+{
+ SYSCTL_RCC &= ~SYSCTL_RCC_IOSCDIS;
+}
+
+/**
+ * \brief Enable the use of SYSCTL_RCC2 register for clock control
+ *
+ * Enables the USERCC2 bit in SYSCTTL_RCC2. Settings in SYSCTL_RCC2 will
+ * override settings in SYSCTL_RCC.
+ * This function must be called before other calls to manipulate the clock, as
+ * libopencm3 uses the SYSCTL_RCC2 register.
+ */
+void rcc_enable_rcc2(void)
+{
+ SYSCTL_RCC2 |= SYSCTL_RCC2_USERCC2;
+}
+
+/**
+ * \brief Power down the main PLL
+ *
+ * Sets the SYSCTL_RCC2_PWRDN2 in SYSCTL_RCC2 to power down the PLL.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_pll_off(void)
+{
+ SYSCTL_RCC2 |= SYSCTL_RCC2_PWRDN2;
+}
+
+/**
+ * \brief Power up the main PLL
+ *
+ * Clears the PWRDN2 in SYSCTL_RCC2 to power on the PLL.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_pll_on(void)
+{
+ SYSCTL_RCC2 &= ~SYSCTL_RCC2_PWRDN2;
+}
+
+/**
+ * \brief Set the oscillator source to be used by the system clock
+ *
+ * Set the clock source for the system clock.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_set_osc_source(osc_src_t src)
+{
+ u32 reg32;
+
+ reg32 = SYSCTL_RCC2;
+ reg32 &= ~SYSCTL_RCC2_OSCSRC2_MASK;
+ reg32 |= (src & SYSCTL_RCC2_OSCSRC2_MASK);
+ SYSCTL_RCC2 = reg32;
+}
+
+/**
+ * \brief Disable the PLL bypass and use the PLL clock
+ *
+ * Clear BYPASS2 in SYSCTL_RCC2. The system clock is derived from the PLL
+ * clock divided by the divisor specified in SYSDIV2.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_pll_bypass_disable(void)
+{
+ SYSCTL_RCC2 &= ~SYSCTL_RCC2_BYPASS2;
+}
+
+/**
+ * \brief Enable the PLL bypass and use the oscillator clock
+ *
+ * Set BYPASS2 in SYSCTL_RCC2. The system clock is derived from the oscillator
+ * clock divided by the divisor specified in SYSDIV2.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_pll_bypass_enable(void)
+{
+ SYSCTL_RCC2 |= SYSCTL_RCC2_BYPASS2;
+}
+
+/**
+ * \brief Set the PLL clock divisor (from 400MHz)
+ *
+ * Set the binary divisor used to predivide the system clock down for use as the
+ * timing reference for the PWM module. The divisor is expected to be a divisor
+ * from 400MHz, not 200MHz. The DIV400 is also set.
+ *
+ * Specifies the divisor that used to generate the system clock from either the
+ * PLL output or the oscillator source (depending on the BYPASS2 bit in
+ * SYSCTL_RCC2). SYSDIV2 is used for the divisor when both the USESYSDIV bit in
+ * SYSCTL_RCC is set.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ *
+ * @param[in] div clock divisor to apply to the 400MHz PLL clock. It is the
+ * caller's responsibility to ensure that the divisor will not create
+ * a system clock that is out of spec.
+ */
+void rcc_set_pll_divisor(u8 div400)
+{
+ u32 reg32;
+
+ SYSCTL_RCC |= SYSCTL_RCC_USESYSDIV;
+
+ reg32 = SYSCTL_RCC2;
+ reg32 &= ~SYSCTL_RCC2_SYSDIV400_MASK;
+ reg32 |= (div400 << 22) & SYSCTL_RCC2_SYSDIV400_MASK;
+ /* We are expecting a divider from 400MHz */
+ reg32 |= SYSCTL_RCC2_DIV400;
+ SYSCTL_RCC2 = reg32;
+}
+/**
+ * \brief Set the PWM unit clock divisor
+ *
+ * Set the binary divisor used to predivide the system clock down for use as the
+ * timing reference for the PWM module.
+ *
+ * @param[in] div clock divisor to use @see pwm_clkdiv_t
+ */
+void rcc_set_pwm_divisor(pwm_clkdiv_t div)
+{
+ u32 reg32;
+
+ reg32 = SYSCTL_RCC;
+ reg32 &= ~SYSCTL_RCC_PWMDIV_MASK;
+ reg32 |= (div & SYSCTL_RCC_PWMDIV_MASK);
+ SYSCTL_RCC = reg32;
+}
+
+/**
+ * \brief Power down the USB PLL
+ *
+ * Sets the USBPWRDN in SYSCTL_RCC2 to power down the USB PLL.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_usb_pll_off(void)
+{
+ SYSCTL_RCC2 |= SYSCTL_RCC2_USBPWRDN;
+}
+
+/**
+ * \brief Power up the USB PLL
+ *
+ * Clears the USBPWRDN in SYSCTL_RCC2 to power on the USB PLL.
+ *
+ * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
+ * function.
+ */
+void rcc_usb_pll_on(void)
+{
+ SYSCTL_RCC2 &= ~SYSCTL_RCC2_USBPWRDN;
+}
+
+/**
+ * \brief Wait for main PLL to lock
+ *
+ * Waits until the LOCK bit in SYSCTL_PLLSTAT is set. This guarantees that the
+ * PLL is locked, and ready to use.
+ */
+void rcc_wait_for_pll_ready(void)
+{
+ while(!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup rcc_high_level High-level clock control API
+ * @{
+ */
+
+/**
+ * \brief Change the PLL divisor
+ *
+ * Changes the divisor applied to the 400MHz PLL clock. The PLL must have
+ * previously been configured by selecting an appropriate XTAL value, and
+ * turning on the PLL. This function does not reconfigure the XTAL value or
+ * oscillator source. It only changes the PLL divisor.
+ *
+ * The PLL is bypassed before modifying the divisor, and the function blocks
+ * until the PLL is locked, then the bypass is disabled, before returning.
+ *
+ * @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
+ */
+void rcc_change_pll_divisor(u8 pll_div400)
+{
+ /* Bypass the PLL while its settings are modified */
+ rcc_pll_bypass_enable();
+ /* Change the clock divisor */
+ rcc_set_pll_divisor(pll_div400);
+ /* We cannot use the PLL as a clock source until it locks */
+ rcc_wait_for_pll_ready();
+ /* Disable PLL bypass to derive the system clock from the PLL clock */
+ rcc_pll_bypass_disable();
+ /* Update the system clock frequency for housekeeping */
+ lm4f_rcc_sysclk_freq = (u32)400E6 / pll_div400;
+}
+
+/**
+ * \brief Get the system clock frequency
+ *
+ * @return System clock frequency in Hz
+ */
+u32 rcc_get_system_clock_frequency(void)
+{
+ return lm4f_rcc_sysclk_freq;
+}
+
+/* Get the clock frequency corresponging to a given XTAL value */
+static u32 xtal_to_freq(xtal_t xtal)
+{
+ const u32 freqs[] = {
+ 4000000, /* XTAL_4M */
+ 4096000, /* XTAL_4M_096 */
+ 4915200, /* XTAL_4M_9152 */
+ 5000000, /* ,XTAL_5M */
+ 5120000, /* XTAL_5M_12 */
+ 6000000, /* XTAL_6M */
+ 6144000, /* XTAL_6M_144 */
+ 7372800, /* XTAL_7M_3728 */
+ 8000000, /* XTAL_8M */
+ 8192000, /* XTAL_8M_192 */
+ 10000000, /* XTAL_10M */
+ 12000000, /* XTAL_12M */
+ 12288000, /* XTAL_12M_288 */
+ 13560000, /* XTAL_13M_56 */
+ 14318180, /* XTAL_14M_31818 */
+ 16000000, /* XTAL_16M */
+ 16384000, /* XTAL_16M_384 */
+ 18000000, /* XTAL_18M */
+ 20000000, /* XTAL_20M */
+ 24000000, /* XTAL_24M */
+ 25000000, /* XTAL_25M */
+ };
+
+ return freqs[xtal - XTAL_4M];
+}
+
+/**
+ * \brief Configure the system clock source
+ *
+ * Sets up the system clock, including configuring the oscillator source, and
+ * PLL to acheve the desired system clock frequency. Where applicable, The LM4F
+ * clock API uses the new RCC2 register to configure clock parameters.
+ *
+ * Enables the main oscillator if the clock source is OSCSRC_MOSC. If the main
+ * oscillator was previously enabled, it will not be disabled. If desired, it
+ * can be separately disabled by a call to rcc_disable_main_osc().
+ *
+ * Configures the system clock to run from the 400MHz PLL with a divisor of
+ * pll_div400 applied. If pll_div400 is 0, then the PLL is disabled, and the
+ * system clock is configured to run off a "raw" clock. If the PLL was
+ * previously powered on, it will not be disabled. If desired, it can de powered
+ * off by a call to rcc_pll_off().
+ *
+ * @param [in] osc_src Oscillator from where to derive the system clock.
+ * @param [in] xtal Type of crystal connected to the OSCO/OSCI pins
+ * @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
+ * If 0, then the PLL is disabled, and the system runs
+ * off a "raw" clock.
+ *
+ * @return System clock frequency in Hz
+ */
+void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, u8 pll_div400)
+{
+ /*
+ * We could be using the PLL at this point, or we could be running of a
+ * raw clock. Either way, it is safer to bypass the PLL now.
+ */
+ rcc_pll_bypass_enable();
+
+ /* Enable the main oscillator, if needed */
+ if (osc_src == OSCSRC_MOSC)
+ rcc_enable_main_osc();
+
+ /* Make RCC2 override RCC */
+ rcc_enable_rcc2();
+
+ /* Set XTAL value to 16MHz */
+ rcc_configure_xtal(xtal);
+ /* Set the oscillator source */
+ rcc_set_osc_source(osc_src);
+ if (pll_div400) {
+ /* Enable the PLL */
+ rcc_pll_on();
+ /* Configure the PLL to the divisor we want */
+ rcc_change_pll_divisor(pll_div400);
+ } else {
+ /* We are running off a raw clock */
+ switch (osc_src) {
+ case OSCSRC_PIOSC:
+ lm4f_rcc_sysclk_freq = 16000000;
+ break;
+ case OSCSRC_PIOSC_D4:
+ lm4f_rcc_sysclk_freq = 4000000;
+ break;
+ case OSCSRC_MOSC:
+ lm4f_rcc_sysclk_freq = xtal_to_freq(xtal);
+ break;
+ case OSCSRC_32K_EXT:
+ lm4f_rcc_sysclk_freq = 32768;
+ break;
+ case OSCSRC_30K_INT: /* Fall through. */
+ default:
+ /*
+ * We either are running off the internal 30KHz
+ * oscillator, which is +- 50% imprecise, or we got a
+ * bad osc_src parameter.
+ */
+ lm4f_rcc_sysclk_freq = 0;
+ }
+ }
+
+}
+
+/**
+ * @}
+ * @}
+ */
diff --git a/lib/lm4f/systemcontrol.c b/lib/lm4f/systemcontrol.c
new file mode 100644
index 0000000..691b661
--- /dev/null
+++ b/lib/lm4f/systemcontrol.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/lm4f/systemcontrol.h>
+
+/**
+ * \brief Enable the clock source for the peripheral
+ *
+ * @param[in] periph peripheral and clock type to enable @see clken_t
+ */
+void periph_clock_enable(clken_t periph)
+{
+ MMIO32(SYSCTL_BASE + (periph >> 5)) |= 1 << (periph & 0x1f);
+}
+
+/**
+ * \brief Disable the clock source for the peripheral
+ *
+ * @param[in] periph peripheral and clock type to enable @see clken_t
+ */
+void periph_clock_disable(clken_t periph)
+{
+ MMIO32(SYSCTL_BASE + (periph >> 5)) &= ~(1 << (periph & 0x1f));
+}
diff --git a/lib/stm32/common/dma_common_f13.c b/lib/stm32/common/dma_common_f13.c
index 0a708aa..35b9da6 100644
--- a/lib/stm32/common/dma_common_f13.c
+++ b/lib/stm32/common/dma_common_f13.c
@@ -55,9 +55,7 @@ The channel is disabled and configuration registers are cleared.
void dma_channel_reset(u32 dma, u8 channel)
{
- /* Disable channel. */
- DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
- /* Reset config bits. */
+ /* Disable channel and reset config bits. */
DMA_CCR(dma, channel) = 0;
/* Reset data transfer number. */
DMA_CNDTR(dma, channel) = 0;
diff --git a/lib/stm32/common/pwr_common_all.c b/lib/stm32/common/pwr_common_all.c
new file mode 100644
index 0000000..451ed1c
--- /dev/null
+++ b/lib/stm32/common/pwr_common_all.c
@@ -0,0 +1,217 @@
+/** @defgroup STM32F1xx-pwr-file PWR
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx Power Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 18 August 2012
+
+This library supports the power control system for the
+STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics.
+
+LGPL License Terms @ref lgpl_license
+*/
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/pwr.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable Backup Domain Write Protection.
+
+This allows backup domain registers to be changed. These registers are write
+protected after a reset.
+*/
+
+void pwr_disable_backup_domain_write_protect(void)
+{
+ PWR_CR |= PWR_CR_DBP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Re-enable Backup Domain Write Protection.
+
+This protects backup domain registers from inadvertent change.
+*/
+
+void pwr_enable_backup_domain_write_protect(void)
+{
+ PWR_CR &= ~PWR_CR_DBP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable Power Voltage Detector.
+
+This provides voltage level threshold detection. The result of detection is
+provided in the power voltage detector output flag (see @ref pwr_voltage_high)
+or by setting the EXTI16 interrupt (see datasheet for configuration details).
+
+@param[in] pvd_level u32. Taken from @ref pwr_pls.
+*/
+
+void pwr_enable_power_voltage_detect(u32 pvd_level)
+{
+ PWR_CR &= ~PWR_CR_PLS_MASK;
+ PWR_CR |= (PWR_CR_PVDE | pvd_level);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable Power Voltage Detector.
+
+*/
+
+void pwr_disable_power_voltage_detect(void)
+{
+ PWR_CR &= ~PWR_CR_PVDE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Clear the Standby Flag.
+
+This is set when the processor returns from a standby mode.
+*/
+
+void pwr_clear_standby_flag(void)
+{
+ PWR_CR |= PWR_CR_CSBF;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Clear the Wakeup Flag.
+
+This is set when the processor receives a wakeup signal.
+*/
+
+void pwr_clear_wakeup_flag(void)
+{
+ PWR_CR |= PWR_CR_CWUF;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set Standby Mode in Deep Sleep.
+
+*/
+
+void pwr_set_standby_mode(void)
+{
+ PWR_CR |= PWR_CR_PDDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set Stop Mode in Deep Sleep.
+
+*/
+
+void pwr_set_stop_mode(void)
+{
+ PWR_CR &= ~PWR_CR_PDDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Voltage Regulator On in Stop Mode.
+
+*/
+
+void pwr_voltage_regulator_on_in_stop(void)
+{
+ PWR_CR &= ~PWR_CR_LPDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Voltage Regulator Low Power in Stop Mode.
+
+*/
+
+void pwr_voltage_regulator_low_power_in_stop(void)
+{
+ PWR_CR |= PWR_CR_LPDS;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable Wakeup Pin.
+
+The wakeup pin is used for waking the processor from standby mode.
+*/
+
+void pwr_enable_wakeup_pin(void)
+{
+ PWR_CSR |= PWR_CSR_EWUP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Release Wakeup Pin.
+
+The wakeup pin is used for general purpose I/O.
+*/
+
+void pwr_disable_wakeup_pin(void)
+{
+ PWR_CSR &= ~PWR_CSR_EWUP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Get Voltage Detector Output.
+
+The voltage detector threshold must be set when the power voltage detector is
+enabled, see @ref pwr_enable_power_voltage_detect.
+
+@returns boolean: TRUE if the power voltage is above the preset voltage
+threshold.
+*/
+
+bool pwr_voltage_high(void)
+{
+ return (PWR_CSR & PWR_CSR_PVDO);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Get Standby Flag.
+
+The standby flag is set when the processor returns from a standby state. It is
+cleared by software (see @ref pwr_clear_standby_flag).
+
+@returns boolean: TRUE if the processor was in standby state.
+*/
+
+bool pwr_get_standby_flag(void)
+{
+ return (PWR_CSR & PWR_CSR_SBF);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Get Wakeup Flag.
+
+The wakeup flag is set when a wakeup event has been received. It is
+cleared by software (see @ref pwr_clear_wakeup_flag).
+
+@returns boolean: TRUE if a wakeup event was received.
+*/
+
+bool pwr_get_wakeup_flag(void)
+{
+ return (PWR_CSR & PWR_CSR_WUF);
+}
+/**@}*/
+
diff --git a/lib/stm32/common/rtc_common_bcd.c b/lib/stm32/common/rtc_common_bcd.c
new file mode 100644
index 0000000..c302ea2
--- /dev/null
+++ b/lib/stm32/common/rtc_common_bcd.c
@@ -0,0 +1,78 @@
+/** @addtogroup rtc_file */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/rtc.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set RTC prescalars.
+
+This sets the RTC synchronous and asynchronous prescalars.
+*/
+
+void rtc_set_prescaler(u32 sync, u32 async) {
+ /*
+ * Even if only one of the two fields needs to be changed,
+ * 2 separate write accesses must be performed to the RTC_PRER register.
+ */
+ RTC_PRER = (sync & RTC_PRER_PREDIV_S_MASK);
+ RTC_PRER |= (async << RTC_PRER_PREDIV_A_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Wait for RTC registers to be synchronised with the APB1 bus
+
+ Time and Date are accessed through shadow registers which must be synchronized
+*/
+
+void rtc_wait_for_synchro(void) {
+ /* Unlock RTC registers */
+ RTC_WPR = 0xca;
+ RTC_WPR = 0x53;
+
+ RTC_ISR &= ~(RTC_ISR_RSF);
+
+ while (!(RTC_ISR & RTC_ISR_RSF)) {
+ ;
+ }
+ /* disable write protection again */
+ RTC_WPR = 0xff;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Unlock write access to the RTC registers
+
+*/
+void rtc_unlock(void) {
+ RTC_WPR = 0xca;
+ RTC_WPR = 0x53;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Lock write access to the RTC registers
+
+*/
+void rtc_lock(void) {
+ RTC_WPR = 0xff;
+}
+
+/**@}*/
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 6bc21f7..ba0d4b8 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
ARFLAGS = rcs
OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
- timer.o usb_f107.o desig.o pwr.o \
+ timer.o usb_f107.o desig.o pwr_common_all.o \
usb_fx07_common.o \
gpio_common_all.o dma_common_f13.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o \
diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c
index 232086c..49f182c 100644
--- a/lib/stm32/f1/flash.c
+++ b/lib/stm32/f1/flash.c
@@ -22,22 +22,22 @@
void flash_prefetch_buffer_enable(void)
{
- FLASH_ACR |= FLASH_PRFTBE;
+ FLASH_ACR |= FLASH_ACR_PRFTBE;
}
void flash_prefetch_buffer_disable(void)
{
- FLASH_ACR &= ~FLASH_PRFTBE;
+ FLASH_ACR &= ~FLASH_ACR_PRFTBE;
}
void flash_halfcycle_enable(void)
{
- FLASH_ACR |= FLASH_HLFCYA;
+ FLASH_ACR |= FLASH_ACR_HLFCYA;
}
void flash_halfcycle_disable(void)
{
- FLASH_ACR &= ~FLASH_HLFCYA;
+ FLASH_ACR &= ~FLASH_ACR_HLFCYA;
}
void flash_set_ws(u32 ws)
@@ -53,33 +53,33 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
- FLASH_KEYR = FLASH_KEY1;
- FLASH_KEYR = FLASH_KEY2;
+ FLASH_KEYR = FLASH_KEYR_KEY1;
+ FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
- FLASH_CR |= FLASH_LOCK;
+ FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgerr_flag(void)
{
- FLASH_SR |= FLASH_PGERR;
+ FLASH_SR |= FLASH_SR_PGERR;
}
void flash_clear_eop_flag(void)
{
- FLASH_SR |= FLASH_EOP;
+ FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrprterr_flag(void)
{
- FLASH_SR |= FLASH_WRPRTERR;
+ FLASH_SR |= FLASH_SR_WRPRTERR;
}
void flash_clear_bsy_flag(void)
{
- FLASH_SR &= ~FLASH_BSY;
+ FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@@ -92,13 +92,14 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
- FLASH_OPTKEYR = FLASH_KEY1;
- FLASH_OPTKEYR = FLASH_KEY2;
+ /* F1 uses same keys for flash and option */
+ FLASH_OPTKEYR = FLASH_KEYR_KEY1;
+ FLASH_OPTKEYR = FLASH_KEYR_KEY2;
}
void flash_wait_for_last_operation(void)
{
- while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
+ while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@@ -108,7 +109,7 @@ void flash_program_word(u32 address, u32 data)
flash_wait_for_last_operation();
/* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
(*(volatile u16 *)address) = (u16)data;
@@ -123,67 +124,67 @@ void flash_program_word(u32 address, u32 data)
flash_wait_for_last_operation();
/* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
+ FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
{
flash_wait_for_last_operation();
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
(*(volatile u16 *)address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_page(u32 page_address)
{
flash_wait_for_last_operation();
- FLASH_CR |= FLASH_PER;
+ FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
- FLASH_CR |= FLASH_STRT;
+ FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PER;
+ FLASH_CR &= ~FLASH_CR_PER;
}
void flash_erase_all_pages(void)
{
flash_wait_for_last_operation();
- FLASH_CR |= FLASH_MER; /* Enable mass erase. */
- FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
+ FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
+ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
+ FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_erase_option_bytes(void)
{
flash_wait_for_last_operation();
- if ((FLASH_CR & FLASH_OPTWRE) == 0)
+ if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
flash_unlock_option_bytes();
- FLASH_CR |= FLASH_OPTER; /* Enable option byte erase. */
- FLASH_CR |= FLASH_STRT;
+ FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */
+ FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_OPTER; /* Disable option byte erase. */
+ FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
void flash_program_option_bytes(u32 address, u16 data)
{
flash_wait_for_last_operation();
- if ((FLASH_CR & FLASH_OPTWRE) == 0)
+ if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
flash_unlock_option_bytes();
- FLASH_CR |= FLASH_OPTPG; /* Enable option byte programming. */
+ FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
(*(volatile u16 *)address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_OPTPG; /* Disable option byte programming. */
+ FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}
diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c
index 9cd8658..707c931 100644
--- a/lib/stm32/f1/rcc.c
+++ b/lib/stm32/f1/rcc.c
@@ -761,7 +761,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 16.
@@ -814,7 +814,7 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_1WS);
+ flash_set_ws(FLASH_ACR_LATENCY_1WS);
/*
* Set the PLL multiplication factor to 12.
@@ -865,7 +865,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_0WS);
+ flash_set_ws(FLASH_ACR_LATENCY_0WS);
/*
* Set the PLL multiplication factor to 6.
@@ -922,7 +922,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_0WS);
+ flash_set_ws(FLASH_ACR_LATENCY_0WS);
/*
* Set the PLL multiplication factor to 3.
@@ -985,7 +985,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@@ -1048,7 +1048,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@@ -1111,7 +1111,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 9.
@@ -1158,7 +1158,7 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
- flash_set_ws(FLASH_LATENCY_2WS);
+ flash_set_ws(FLASH_ACR_LATENCY_2WS);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index 3d3c756..85e6458 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -31,7 +31,8 @@ ARFLAGS = rcs
OBJS = rcc.o gpio.o flash.o exti2.o timer.o \
gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
- crc_common_all.o
+ crc_common_all.o \
+ rtc_common_bcd.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f2/flash.c b/lib/stm32/f2/flash.c
index 6e2c64d..0b9f834 100644
--- a/lib/stm32/f2/flash.c
+++ b/lib/stm32/f2/flash.c
@@ -28,42 +28,42 @@ static inline void flash_set_program_size(u32 psize)
void flash_data_cache_enable(void)
{
- FLASH_ACR |= FLASH_DCE;
+ FLASH_ACR |= FLASH_ACR_DCE;
}
void flash_dcache_disable(void)
{
- FLASH_ACR &= ~FLASH_DCE;
+ FLASH_ACR &= ~FLASH_ACR_DCE;
}
void flash_icache_enable(void)
{
- FLASH_ACR |= FLASH_ICE;
+ FLASH_ACR |= FLASH_ACR_ICE;
}
void flash_icache_disable(void)
{
- FLASH_ACR &= ~FLASH_ICE;
+ FLASH_ACR &= ~FLASH_ACR_ICE;
}
void flash_prefetch_enable(void)
{
- FLASH_ACR |= FLASH_PRFTEN;
+ FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
- FLASH_ACR &= ~FLASH_PRFTEN;
+ FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_dcache_reset(void)
{
- FLASH_ACR |= FLASH_DCRST;
+ FLASH_ACR |= FLASH_ACR_DCRST;
}
void flash_icache_reset(void)
{
- FLASH_ACR |= FLASH_ICRST;
+ FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
@@ -79,43 +79,43 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
- FLASH_KEYR = FLASH_KEY1;
- FLASH_KEYR = FLASH_KEY2;
+ FLASH_KEYR = FLASH_KEYR_KEY1;
+ FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
- FLASH_CR |= FLASH_LOCK;
+ FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgserr_flag(void)
{
- FLASH_SR |= FLASH_PGSERR;
+ FLASH_SR |= FLASH_SR_PGSERR;
}
void flash_clear_pgperr_flag(void)
{
- FLASH_SR |= FLASH_PGPERR;
+ FLASH_SR |= FLASH_SR_PGPERR;
}
void flash_clear_pgaerr_flag(void)
{
- FLASH_SR |= FLASH_PGAERR;
+ FLASH_SR |= FLASH_SR_PGAERR;
}
void flash_clear_eop_flag(void)
{
- FLASH_SR |= FLASH_EOP;
+ FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrperr_flag(void)
{
- FLASH_SR |= FLASH_WRPERR;
+ FLASH_SR |= FLASH_SR_WRPERR;
}
void flash_clear_bsy_flag(void)
{
- FLASH_SR &= ~FLASH_BSY;
+ FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@@ -130,18 +130,18 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
- FLASH_OPTKEYR = FLASH_OPTKEY1;
- FLASH_OPTKEYR = FLASH_OPTKEY2;
+ FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
+ FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
}
void flash_lock_option_bytes(void)
{
- FLASH_OPTCR |= FLASH_OPTLOCK;
+ FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
}
void flash_wait_for_last_operation(void)
{
- while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
+ while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@@ -152,7 +152,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO64(address) = data;
@@ -161,7 +161,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
+ FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data, u32 program_size)
@@ -171,7 +171,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO32(address) = data;
@@ -180,7 +180,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
+ FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data, u32 program_size)
@@ -188,13 +188,13 @@ void flash_program_half_word(u32 address, u16 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data, u32 program_size)
@@ -202,13 +202,13 @@ void flash_program_byte(u32 address, u8 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
MMIO8(address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_sector(u32 sector, u32 program_size)
@@ -218,10 +218,10 @@ void flash_erase_sector(u32 sector, u32 program_size)
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
FLASH_CR |= sector;
- FLASH_CR |= FLASH_STRT;
+ FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_SER;
+ FLASH_CR &= ~FLASH_CR_SER;
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
}
@@ -230,21 +230,21 @@ void flash_erase_all_sectors(u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
- FLASH_CR |= FLASH_MER; /* Enable mass erase. */
- FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
+ FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
+ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
+ FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
{
flash_wait_for_last_operation();
- if (FLASH_OPTCR & FLASH_OPTLOCK)
+ if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
flash_unlock_option_bytes();
FLASH_OPTCR = data & ~0x3;
- FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
+ FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
flash_wait_for_last_operation();
}
diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c
index cc2c9bb..d60c232 100644
--- a/lib/stm32/f2/rcc.c
+++ b/lib/stm32/f2/rcc.c
@@ -37,7 +37,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
- .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
+ .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
diff --git a/lib/stm32/f2/rtc.c b/lib/stm32/f2/rtc.c
new file mode 100644
index 0000000..461d0b1
--- /dev/null
+++ b/lib/stm32/f2/rtc.c
@@ -0,0 +1,27 @@
+/** @defgroup rtc_file RTC
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx RTC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index 2b02281..8ff7c6a 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -32,9 +32,11 @@ ARFLAGS = rcs
OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
usb_f207.o adc.o dma.o \
+ pwr_common_all.o \
gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
- crc_common_all.o
+ crc_common_all.o \
+ rtc_common_bcd.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f4/flash.c b/lib/stm32/f4/flash.c
index a9fe06c..75446ea 100644
--- a/lib/stm32/f4/flash.c
+++ b/lib/stm32/f4/flash.c
@@ -28,42 +28,42 @@ static inline void flash_set_program_size(u32 psize)
void flash_data_cache_enable(void)
{
- FLASH_ACR |= FLASH_DCE;
+ FLASH_ACR |= FLASH_ACR_DCE;
}
void flash_dcache_disable(void)
{
- FLASH_ACR &= ~FLASH_DCE;
+ FLASH_ACR &= ~FLASH_ACR_DCE;
}
void flash_icache_enable(void)
{
- FLASH_ACR |= FLASH_ICE;
+ FLASH_ACR |= FLASH_ACR_ICE;
}
void flash_icache_disable(void)
{
- FLASH_ACR &= ~FLASH_ICE;
+ FLASH_ACR &= ~FLASH_ACR_ICE;
}
void flash_prefetch_enable(void)
{
- FLASH_ACR |= FLASH_PRFTEN;
+ FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
- FLASH_ACR &= ~FLASH_PRFTEN;
+ FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_dcache_reset(void)
{
- FLASH_ACR |= FLASH_DCRST;
+ FLASH_ACR |= FLASH_ACR_DCRST;
}
void flash_icache_reset(void)
{
- FLASH_ACR |= FLASH_ICRST;
+ FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
@@ -79,43 +79,43 @@ void flash_set_ws(u32 ws)
void flash_unlock(void)
{
/* Authorize the FPEC access. */
- FLASH_KEYR = FLASH_KEY1;
- FLASH_KEYR = FLASH_KEY2;
+ FLASH_KEYR = FLASH_KEYR_KEY1;
+ FLASH_KEYR = FLASH_KEYR_KEY2;
}
void flash_lock(void)
{
- FLASH_CR |= FLASH_LOCK;
+ FLASH_CR |= FLASH_CR_LOCK;
}
void flash_clear_pgserr_flag(void)
{
- FLASH_SR |= FLASH_PGSERR;
+ FLASH_SR |= FLASH_SR_PGSERR;
}
void flash_clear_pgperr_flag(void)
{
- FLASH_SR |= FLASH_PGPERR;
+ FLASH_SR |= FLASH_SR_PGPERR;
}
void flash_clear_pgaerr_flag(void)
{
- FLASH_SR |= FLASH_PGAERR;
+ FLASH_SR |= FLASH_SR_PGAERR;
}
void flash_clear_eop_flag(void)
{
- FLASH_SR |= FLASH_EOP;
+ FLASH_SR |= FLASH_SR_EOP;
}
void flash_clear_wrperr_flag(void)
{
- FLASH_SR |= FLASH_WRPERR;
+ FLASH_SR |= FLASH_SR_WRPERR;
}
void flash_clear_bsy_flag(void)
{
- FLASH_SR &= ~FLASH_BSY;
+ FLASH_SR &= ~FLASH_SR_BSY;
}
void flash_clear_status_flags(void)
@@ -130,18 +130,18 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void)
{
- FLASH_OPTKEYR = FLASH_OPTKEY1;
- FLASH_OPTKEYR = FLASH_OPTKEY2;
+ FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
+ FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
}
void flash_lock_option_bytes(void)
{
- FLASH_OPTCR |= FLASH_OPTLOCK;
+ FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
}
void flash_wait_for_last_operation(void)
{
- while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
+ while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
}
@@ -152,7 +152,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO64(address) = data;
@@ -161,7 +161,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
+ FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data, u32 program_size)
@@ -171,7 +171,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_set_program_size(program_size);
/* Enable writes to flash. */
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
MMIO32(address) = data;
@@ -180,7 +180,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_wait_for_last_operation();
/* Disable writes to flash. */
- FLASH_CR &= ~FLASH_PG;
+ FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data, u32 program_size)
@@ -188,13 +188,13 @@ void flash_program_half_word(u32 address, u16 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data, u32 program_size)
@@ -202,13 +202,13 @@ void flash_program_byte(u32 address, u8 data, u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
- FLASH_CR |= FLASH_PG;
+ FLASH_CR |= FLASH_CR_PG;
MMIO8(address) = data;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
+ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_sector(u32 sector, u32 program_size)
@@ -218,11 +218,11 @@ void flash_erase_sector(u32 sector, u32 program_size)
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
FLASH_CR |= sector;
- FLASH_CR |= FLASH_SER;
- FLASH_CR |= FLASH_STRT;
+ FLASH_CR |= FLASH_CR_SER;
+ FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_SER;
+ FLASH_CR &= ~FLASH_CR_SER;
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
}
@@ -231,21 +231,21 @@ void flash_erase_all_sectors(u32 program_size)
flash_wait_for_last_operation();
flash_set_program_size(program_size);
- FLASH_CR |= FLASH_MER; /* Enable mass erase. */
- FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
+ FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
+ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation();
- FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
+ FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
{
flash_wait_for_last_operation();
- if (FLASH_OPTCR & FLASH_OPTLOCK)
+ if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
flash_unlock_option_bytes();
FLASH_OPTCR = data & ~0x3;
- FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
+ FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
flash_wait_for_last_operation();
}
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index f506d4b..1024f0b 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -39,7 +39,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
- .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
+ .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
@@ -51,7 +51,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
- .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS,
+ .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c
new file mode 100644
index 0000000..1b301fa
--- /dev/null
+++ b/lib/stm32/f4/rtc.c
@@ -0,0 +1,27 @@
+/** @defgroup rtc_file RTC
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx RTC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index 32c8fd3..9b677ab 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -31,7 +31,8 @@ ARFLAGS = rcs
OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o
OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o
OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o
-OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
+OBJS += pwr_common_all.o pwr.o
+OBJS += rtc_common_bcd.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c
index 06e8a59..7b20f69 100644
--- a/lib/stm32/l1/flash.c
+++ b/lib/stm32/l1/flash.c
@@ -23,22 +23,22 @@
void flash_64bit_enable(void)
{
- FLASH_ACR |= FLASH_ACC64;
+ FLASH_ACR |= FLASH_ACR_ACC64;
}
void flash_64bit_disable(void)
{
- FLASH_ACR &= ~FLASH_ACC64;
+ FLASH_ACR &= ~FLASH_ACR_ACC64;
}
void flash_prefetch_enable(void)
{
- FLASH_ACR |= FLASH_PRFTEN;
+ FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
- FLASH_ACR &= ~FLASH_PRFTEN;
+ FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_set_ws(u32 ws)
diff --git a/lib/stm32/l1/pwr_chipset.c b/lib/stm32/l1/pwr.c
index 9f4f599..8541851 100644
--- a/lib/stm32/l1/pwr_chipset.c
+++ b/lib/stm32/l1/pwr.c
@@ -17,7 +17,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <libopencm3/stm32/l1/pwr.h>
+#include <libopencm3/stm32/pwr.h>
void pwr_set_vos_scale(vos_scale_t scale)
{
diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c
index bbba9a9..106032a 100644
--- a/lib/stm32/l1/rcc.c
+++ b/lib/stm32/l1/rcc.c
@@ -23,13 +23,13 @@
#include <libopencm3/stm32/l1/rcc.h>
#include <libopencm3/stm32/l1/flash.h>
-#include <libopencm3/stm32/l1/pwr.h>
+#include <libopencm3/stm32/pwr.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 2097000;
u32 rcc_ppre2_frequency = 2097000;
-const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
+const clock_scale_t clock_config[CLOCK_CONFIG_END] =
{
{ /* 24MHz PLL from HSI */
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
@@ -39,7 +39,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_1WS,
+ .flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 24000000,
.apb2_frequency = 24000000,
},
@@ -51,7 +51,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_1WS,
+ .flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 32000000,
.apb2_frequency = 32000000,
},
@@ -60,10 +60,39 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_0WS,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 16000000,
.apb2_frequency = 16000000,
},
+ { /* 4MHz HSI raw */
+ .hpre = RCC_CFGR_HPRE_SYSCLK_DIV4,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE1,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
+ .apb1_frequency = 4000000,
+ .apb2_frequency = 4000000,
+ },
+ { /* 4MHz MSI raw */
+ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE1,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
+ .apb1_frequency = 4194000,
+ .apb2_frequency = 4194000,
+ .msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
+ },
+ { /* 2MHz MSI raw */
+ .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+ .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
+ .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+ .voltage_scale = RANGE1,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
+ .apb1_frequency = 2097000,
+ .apb2_frequency = 2097000,
+ .msi_range = RCC_ICSCR_MSIRANGE_2MHZ,
+ },
};
void rcc_osc_ready_int_clear(osc_t osc)
@@ -408,6 +437,48 @@ u32 rcc_system_clock_source(void)
return ((RCC_CFGR & 0x000c) >> 2);
}
+void rcc_rtc_select_clock(u32 clock)
+{
+ RCC_CSR &= ~(RCC_CSR_RTCSEL_MASK << RCC_CSR_RTCSEL_SHIFT);
+ RCC_CSR |= (clock << RCC_CSR_RTCSEL_SHIFT);
+}
+
+void rcc_clock_setup_msi(const clock_scale_t *clock)
+{
+ /* Enable internal multi-speed oscillator. */
+
+ u32 reg = RCC_ICSCR;
+ reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
+ reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
+ RCC_ICSCR = reg;
+
+ rcc_osc_on(MSI);
+ rcc_wait_for_osc_ready(MSI);
+
+ /* Select MSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_MSICLK);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(clock->hpre);
+ rcc_set_ppre1(clock->ppre1);
+ rcc_set_ppre2(clock->ppre2);
+
+ pwr_set_vos_scale(clock->voltage_scale);
+
+ // I guess this should be in the settings?
+ flash_64bit_enable();
+ flash_prefetch_enable();
+ /* Configure flash settings. */
+ flash_set_ws(clock->flash_config);
+
+ /* Set the peripheral clock frequencies used. */
+ rcc_ppre1_frequency = clock->apb1_frequency;
+ rcc_ppre2_frequency = clock->apb2_frequency;
+}
+
void rcc_clock_setup_hsi(const clock_scale_t *clock)
{
/* Enable internal high-speed oscillator. */
diff --git a/lib/stm32/l1/rtc.c b/lib/stm32/l1/rtc.c
new file mode 100644
index 0000000..bc7f87f
--- /dev/null
+++ b/lib/stm32/l1/rtc.c
@@ -0,0 +1,27 @@
+/** @defgroup rtc_file RTC
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx RTC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/rtc.h>
+#include <libopencm3/stm32/common/rtc_common_bcd.h>