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authorKarl Palsson2013-01-23 12:54:17 +0000
committerKarl Palsson2013-01-23 13:58:06 +0000
commitc0ea74945223df7a40150fbe86d82963942a89bb (patch)
tree30d3a083232cceffb76effb57d777820df57d0b0 /lib/stm32/l1/rcc.c
parent20bfcaeb1c773012f1c41e004915b72f6abba352 (diff)
[flash] l1: use "proper" bit definition naming.
Part 1 of 4: updated l1 to use flash_<reg>_bit instead of just flash_bit
Diffstat (limited to 'lib/stm32/l1/rcc.c')
-rw-r--r--lib/stm32/l1/rcc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c
index bbba9a9..c06a727 100644
--- a/lib/stm32/l1/rcc.c
+++ b/lib/stm32/l1/rcc.c
@@ -39,7 +39,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_1WS,
+ .flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 24000000,
.apb2_frequency = 24000000,
},
@@ -51,7 +51,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_1WS,
+ .flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 32000000,
.apb2_frequency = 32000000,
},
@@ -60,7 +60,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_0WS,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 16000000,
.apb2_frequency = 16000000,
},