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authorPiotr Esden-Tempski2013-02-18 14:12:48 -0800
committerPiotr Esden-Tempski2013-02-18 14:12:48 -0800
commitb13e55da8c10479aa1d0086aacab52f52e2852de (patch)
treee8b6d9f4719aeb2c1354a6126f80f09d9bf2b4c6 /lib/stm32/l1/rcc.c
parent3c110fec8e5a3e39b5ae49e26295608544de4110 (diff)
Adjusted code for l1 to the new api introduced by karlp in pr #84
Diffstat (limited to 'lib/stm32/l1/rcc.c')
-rw-r--r--lib/stm32/l1/rcc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c
index a6078c9..106032a 100644
--- a/lib/stm32/l1/rcc.c
+++ b/lib/stm32/l1/rcc.c
@@ -69,7 +69,7 @@ const clock_scale_t clock_config[CLOCK_CONFIG_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_0WS,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 4000000,
.apb2_frequency = 4000000,
},
@@ -78,7 +78,7 @@ const clock_scale_t clock_config[CLOCK_CONFIG_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_0WS,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 4194000,
.apb2_frequency = 4194000,
.msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
@@ -88,7 +88,7 @@ const clock_scale_t clock_config[CLOCK_CONFIG_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
- .flash_config = FLASH_LATENCY_0WS,
+ .flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 2097000,
.apb2_frequency = 2097000,
.msi_range = RCC_ICSCR_MSIRANGE_2MHZ,