aboutsummaryrefslogtreecommitdiff
path: root/lib/stm32/f4/rcc.c
diff options
context:
space:
mode:
authorKarl Palsson2013-01-23 13:46:08 +0000
committerKarl Palsson2013-01-23 13:58:11 +0000
commit40d9d630f0769a374ddc12616323dc6a94f02b7f (patch)
treeaec9a111f18bdbde4c6825d9f93433fd63dbaa58 /lib/stm32/f4/rcc.c
parent316b068cb4d648b90ae14aa3454ed1d18c9580c9 (diff)
[flash] f4: use "proper" bit definition naming.
Part 4 of 4: updated f4 to use flash_<reg>_bit instead of just flash_bit
Diffstat (limited to 'lib/stm32/f4/rcc.c')
-rw-r--r--lib/stm32/f4/rcc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index f506d4b..1024f0b 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -39,7 +39,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
- .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
+ .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
@@ -51,7 +51,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
- .flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS,
+ .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},