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authorUwe Hermann2011-11-16 19:37:23 +0100
committerUwe Hermann2011-11-17 00:09:27 +0100
commit50f680f3f72badf0391c79d9a5071b759ab4ce98 (patch)
tree890956f082897a30cef3332079fd86148ca38a1d /lib/stm32/f2/rcc.c
parent8725bc51717cce5ac06cc49ab33416099eeca6b1 (diff)
lib/stm32/f2: Coding-style fixes.
Diffstat (limited to 'lib/stm32/f2/rcc.c')
-rw-r--r--lib/stm32/f2/rcc.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c
index 85b3ea0..445ba86 100644
--- a/lib/stm32/f2/rcc.c
+++ b/lib/stm32/f2/rcc.c
@@ -22,7 +22,7 @@
#include <libopencm3/stm32/f2/rcc.h>
#include <libopencm3/stm32/f2/flash.h>
-/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
+/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 16000000;
u32 rcc_ppre2_frequency = 16000000;
@@ -382,16 +382,14 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
- rcc_set_main_pll_hse(clock->pllm,
- clock->plln,
- clock->pllp,
- clock->pllq);
+ rcc_set_main_pll_hse(clock->pllm, clock->plln,
+ clock->pllp, clock->pllq);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
- /* Configure flash settings */
+ /* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */
@@ -400,7 +398,7 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
- /* Set the peripheral clock frequencies used */
+ /* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
}