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authorKarl Palsson2012-11-14 00:10:03 +0000
committerKarl Palsson2012-11-14 00:16:56 +0000
commitdf1808e2dca719a18067e8f4d9ef7b74fd7e84da (patch)
tree83784332285f54625fcea68434f9fdb7a4fe04cd /include/libopencm3/stm32/l1/rcc.h
parent40f3ac58fb00ef4899638b6a42c4d7d1eaa643ce (diff)
[l1] Add rcc clock setup helper routines
Despite the L1 being a low power device, my initial focus is on making it basically compatible with existing devices. To that end, provide clock setup helper routines that configure it for maximum performance, allowing some similar clock speeds to F1 devices to help with testing. This requires adding the power chipset routines to set the voltage range. Clock setup style is similar to the F4 code, which seems nicer than the overflow of different routines used on the F1 code. NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power code, even though it should be compatible
Diffstat (limited to 'include/libopencm3/stm32/l1/rcc.h')
-rw-r--r--include/libopencm3/stm32/l1/rcc.h43
1 files changed, 30 insertions, 13 deletions
diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h
index 6c7dc95..21b073b 100644
--- a/include/libopencm3/stm32/l1/rcc.h
+++ b/include/libopencm3/stm32/l1/rcc.h
@@ -46,6 +46,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/l1/pwr.h>
/* --- RCC registers ------------------------------------------------------- */
@@ -110,6 +111,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_PLLDIV_DIV2 0x1
#define RCC_CFGR_PLLDIV_DIV3 0x2
#define RCC_CFGR_PLLDIV_DIV4 0x3
+#define RCC_CFGR_PLLDIV_SHIFT 22
+#define RCC_CFGR_PLLDIV_MASK 0x3
/* PLLMUL: PLL multiplication factor */
#define RCC_CFGR_PLLMUL_MUL3 0x0
@@ -121,6 +124,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_PLLMUL_MUL24 0x6
#define RCC_CFGR_PLLMUL_MUL32 0x7
#define RCC_CFGR_PLLMUL_MUL48 0x8
+#define RCC_CFGR_PLLMUL_SHIFT 18
+#define RCC_CFGR_PLLMUL_MASK 0xf
/* PLLSRC: PLL entry clock source */
#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
@@ -349,6 +354,28 @@ LGPL License Terms @ref lgpl_license
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
+typedef struct {
+ uint8_t pll_mul;
+ uint16_t pll_div;
+ uint8_t pll_source;
+ uint32_t flash_config;
+ uint8_t hpre;
+ uint8_t ppre1;
+ uint8_t ppre2;
+ vos_scale_t voltage_scale;
+ uint32_t apb1_frequency;
+ uint32_t apb2_frequency;
+} clock_scale_t;
+
+typedef enum {
+ CLOCK_VRANGE1_HSI_PLL_24MHZ,
+ CLOCK_VRANGE1_HSI_PLL_32MHZ,
+ CLOCK_VRANGE1_HSI_RAW_16MHZ,
+ CLOCK_VRANGE1_END
+} clock_volt_range1_t;
+
+extern const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END];
+
/* --- Variable definitions ------------------------------------------------ */
extern u32 rcc_ppre1_frequency;
@@ -378,26 +405,16 @@ void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
-void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor);
void rcc_set_pll_source(u32 pllsrc);
-void rcc_set_pllxtpre(u32 pllxtpre);
void rcc_set_adcpre(u32 adcpre);
void rcc_set_ppre2(u32 ppre2);
void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
-void rcc_clock_setup_in_hsi_out_64mhz(void);
-void rcc_clock_setup_in_hsi_out_48mhz(void);
-
-/**
- * Maximum speed possible for F100 (Value Line) on HSI
- */
-void rcc_clock_setup_in_hsi_out_24mhz(void);
-void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
-void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
-void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
-void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_clock_setup_hsi(const clock_scale_t *clock);
+void rcc_clock_setup_pll(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
/**@}*/