aboutsummaryrefslogtreecommitdiff
path: root/include/libopencm3/stm32/f2/timer.h
diff options
context:
space:
mode:
authorStephen Caudle2011-10-31 11:11:03 -0400
committerStephen Caudle2011-10-31 11:11:03 -0400
commit1fea1df39abde97d1e84f5b99f9793701b1691b7 (patch)
treeec0122ab2b80cea63969cbfb12d19eee15741a5e /include/libopencm3/stm32/f2/timer.h
parent6da485f06dedb5a0401bdec2ce5ea1c9752f5397 (diff)
Fix more STM32 whitespace issues
Diffstat (limited to 'include/libopencm3/stm32/f2/timer.h')
-rw-r--r--include/libopencm3/stm32/f2/timer.h29
1 files changed, 14 insertions, 15 deletions
diff --git a/include/libopencm3/stm32/f2/timer.h b/include/libopencm3/stm32/f2/timer.h
index f7c82ae..b69db2e 100644
--- a/include/libopencm3/stm32/f2/timer.h
+++ b/include/libopencm3/stm32/f2/timer.h
@@ -22,33 +22,32 @@
#include <libopencm3/stm32/timer.h>
-
-/*
+/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4
*/
/* Timer 2/5 option register (TIMx_OR) */
-#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
-#define TIM2_OR TIM_OR(TIM2)
-#define TIM5_OR TIM_OR(TIM5)
+#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
+#define TIM2_OR TIM_OR(TIM2)
+#define TIM5_OR TIM_OR(TIM5)
/* --- TIM2_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
-#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
-#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
-#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
-#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
-#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
+#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
+#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
+#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
/* --- TIM5_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
-#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
-#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
-#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
-#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
-#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
+#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
+#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
+#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
+#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
+#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
#endif