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authorPiotr Esden-Tempski2013-01-09 00:51:24 -0800
committerPiotr Esden-Tempski2013-01-09 01:05:37 -0800
commit204eb047b48d813c1b3b1c08ea1fb232d3bd89e7 (patch)
treee7d6b11fe1c419afa3182be1bd16fa954decd25f
parentcb2fd43666315888df3babcc758e406d93abc53b (diff)
parent85308f562a05db14a89a0335016a44634de072b0 (diff)
Merging pull request #72 Doc
Merge remote-tracking branch 'ksarkies/doc' Conflicts: doc/stm32f1/Doxyfile doc/stm32f2/Doxyfile doc/stm32f4/Doxyfile lib/stm32/f1/Makefile lib/stm32/f2/Makefile lib/stm32/f4/Makefile
-rw-r--r--doc/stm32f1/Doxyfile_latex7
-rw-r--r--doc/stm32f1/DoxygenLayout_stm32f1.xml2
-rw-r--r--doc/stm32f2/Doxyfile2
-rw-r--r--doc/stm32f2/Doxyfile_latex7
-rw-r--r--doc/stm32f4/Doxyfile_latex7
-rw-r--r--doc/stm32l1/Doxyfile25
-rw-r--r--doc/stm32l1/Doxyfile_latex14
-rw-r--r--include/libopencm3/stm32/common/crc_common_all.h85
-rw-r--r--include/libopencm3/stm32/common/dac_common_all.h403
-rw-r--r--include/libopencm3/stm32/common/i2c_common_all.h383
-rw-r--r--include/libopencm3/stm32/common/i2c_common_f24.h35
-rw-r--r--include/libopencm3/stm32/common/iwdg_common_all.h109
-rw-r--r--include/libopencm3/stm32/common/spi_common_all.h399
-rw-r--r--include/libopencm3/stm32/common/spi_common_f24.h50
-rw-r--r--include/libopencm3/stm32/common/usart_common_all.h369
-rw-r--r--include/libopencm3/stm32/common/usart_common_f24.h66
-rw-r--r--include/libopencm3/stm32/crc.h89
-rw-r--r--include/libopencm3/stm32/dac.h409
-rw-r--r--include/libopencm3/stm32/f1/crc.h40
-rw-r--r--include/libopencm3/stm32/f1/dac.h40
-rw-r--r--include/libopencm3/stm32/f1/gpio.h2
-rw-r--r--include/libopencm3/stm32/f1/i2c.h41
-rw-r--r--include/libopencm3/stm32/f1/iwdg.h41
-rw-r--r--include/libopencm3/stm32/f1/spi.h40
-rw-r--r--include/libopencm3/stm32/f1/usart.h40
-rw-r--r--include/libopencm3/stm32/f2/crc.h40
-rw-r--r--include/libopencm3/stm32/f2/dac.h40
-rw-r--r--include/libopencm3/stm32/f2/gpio.h2
-rw-r--r--include/libopencm3/stm32/f2/i2c.h41
-rw-r--r--include/libopencm3/stm32/f2/iwdg.h41
-rw-r--r--include/libopencm3/stm32/f2/spi.h43
-rw-r--r--include/libopencm3/stm32/f2/usart.h63
-rw-r--r--include/libopencm3/stm32/f4/crc.h40
-rw-r--r--include/libopencm3/stm32/f4/dac.h40
-rw-r--r--include/libopencm3/stm32/f4/gpio.h2
-rw-r--r--include/libopencm3/stm32/f4/i2c.h41
-rw-r--r--include/libopencm3/stm32/f4/iwdg.h41
-rw-r--r--include/libopencm3/stm32/f4/spi.h43
-rw-r--r--include/libopencm3/stm32/f4/usart.h63
-rw-r--r--include/libopencm3/stm32/i2c.h387
-rw-r--r--include/libopencm3/stm32/iwdg.h112
-rw-r--r--include/libopencm3/stm32/l1/crc.h40
-rw-r--r--include/libopencm3/stm32/l1/dac.h40
-rw-r--r--include/libopencm3/stm32/l1/i2c.h41
-rw-r--r--include/libopencm3/stm32/l1/iwdg.h41
-rw-r--r--include/libopencm3/stm32/l1/memorymap.h5
-rw-r--r--include/libopencm3/stm32/l1/spi.h40
-rw-r--r--include/libopencm3/stm32/l1/usart.h40
-rw-r--r--include/libopencm3/stm32/rcc.h31
-rw-r--r--include/libopencm3/stm32/spi.h405
-rw-r--r--include/libopencm3/stm32/usart.h374
-rw-r--r--lib/stm32/common/crc_common_all.c (renamed from lib/stm32/crc.c)6
-rw-r--r--lib/stm32/common/dac_common_all.c (renamed from lib/stm32/dac.c)6
-rw-r--r--lib/stm32/common/i2c_common_all.c (renamed from lib/stm32/i2c.c)8
-rw-r--r--lib/stm32/common/iwdg_common_all.c (renamed from lib/stm32/iwdg.c)6
-rw-r--r--lib/stm32/common/spi_common_all.c (renamed from lib/stm32/spi.c)18
-rw-r--r--lib/stm32/common/usart_common_all.c (renamed from lib/stm32/usart.c)19
-rw-r--r--lib/stm32/f1/Makefile9
-rw-r--r--lib/stm32/f1/crc.c29
-rw-r--r--lib/stm32/f1/dac.c28
-rw-r--r--lib/stm32/f1/i2c.c28
-rw-r--r--lib/stm32/f1/iwdg.c28
-rw-r--r--lib/stm32/f1/spi.c28
-rw-r--r--lib/stm32/f1/usart.c28
-rw-r--r--lib/stm32/f2/Makefile7
-rw-r--r--lib/stm32/f2/crc.c29
-rw-r--r--lib/stm32/f2/dac.c28
-rw-r--r--lib/stm32/f2/i2c.c28
-rw-r--r--lib/stm32/f2/iwdg.c28
-rw-r--r--lib/stm32/f2/spi.c28
-rw-r--r--lib/stm32/f2/usart.c28
-rw-r--r--lib/stm32/f4/Makefile7
-rw-r--r--lib/stm32/f4/crc.c29
-rw-r--r--lib/stm32/f4/dac.c28
-rw-r--r--lib/stm32/f4/i2c.c28
-rw-r--r--lib/stm32/f4/iwdg.c28
-rw-r--r--lib/stm32/f4/spi.c28
-rw-r--r--lib/stm32/f4/usart.c28
-rw-r--r--lib/stm32/l1/Makefile8
-rw-r--r--lib/stm32/l1/crc.c29
-rw-r--r--lib/stm32/l1/dac.c28
-rw-r--r--lib/stm32/l1/i2c.c28
-rw-r--r--lib/stm32/l1/iwdg.c28
-rw-r--r--lib/stm32/l1/spi.c28
-rw-r--r--lib/stm32/l1/usart.c28
85 files changed, 3638 insertions, 1933 deletions
diff --git a/doc/stm32f1/Doxyfile_latex b/doc/stm32f1/Doxyfile_latex
index 217b6f9..97c32e7 100644
--- a/doc/stm32f1/Doxyfile_latex
+++ b/doc/stm32f1/Doxyfile_latex
@@ -18,9 +18,10 @@ WARN_LOGFILE = doxygen_stm32f1_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f1 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/f1 \
- ../../lib/stm32/common
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f1 \
+ ../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f1/doc-stm32f1.h \
../../include/libopencm3/stm32/f1/usb.h \
diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml
index c3dfdf2..3e435b3 100644
--- a/doc/stm32f1/DoxygenLayout_stm32f1.xml
+++ b/doc/stm32f1/DoxygenLayout_stm32f1.xml
@@ -5,7 +5,7 @@
<tab type="pages" visible="yes" title="General Information" intro=""/>
<tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/>
<tab type="user" visible="yes" url="../../cm3/html/modules.html" title="CM3 Core" intro=""/>
- <tab type="modules" visible="yes" title="STMF1" intro=""/>
+ <tab type="modules" visible="yes" title="STM32F1" intro=""/>
<tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/>
<tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/>
<tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/>
diff --git a/doc/stm32f2/Doxyfile b/doc/stm32f2/Doxyfile
index d03f4e9..bc0348e 100644
--- a/doc/stm32f2/Doxyfile
+++ b/doc/stm32f2/Doxyfile
@@ -24,6 +24,8 @@ INPUT += ../../lib/stm32/f2 \
EXCLUDE =
+EXCLUDE_PATTERNS =
+
LAYOUT_FILE = DoxygenLayout_stm32f2.xml
TAGFILES = ../cm3/cm3.tag=../../cm3/html
diff --git a/doc/stm32f2/Doxyfile_latex b/doc/stm32f2/Doxyfile_latex
index 29bdc95..dad6848 100644
--- a/doc/stm32f2/Doxyfile_latex
+++ b/doc/stm32f2/Doxyfile_latex
@@ -18,12 +18,15 @@ WARN_LOGFILE = doxygen_stm32f2_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f2 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/f2 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f2 \
../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f2/doc-stm32f2.h
+EXCLUDE_PATTERNS =
+
LAYOUT_FILE = DoxygenLayout_stm32f2.xml
GENERATE_HTML = NO
diff --git a/doc/stm32f4/Doxyfile_latex b/doc/stm32f4/Doxyfile_latex
index 6f62b21..e93248c 100644
--- a/doc/stm32f4/Doxyfile_latex
+++ b/doc/stm32f4/Doxyfile_latex
@@ -18,12 +18,15 @@ WARN_LOGFILE = doxygen_stm32f4_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/f4 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/f4 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f4 \
../../lib/stm32/common
EXCLUDE = ../../include/libopencm3/stm32/f4/doc-stm32f4.h
+EXCLUDE_PATTERNS =
+
LAYOUT_FILE = DoxygenLayout_stm32f4.xml
GENERATE_HTML = NO
diff --git a/doc/stm32l1/Doxyfile b/doc/stm32l1/Doxyfile
index deca18b..566bb01 100644
--- a/doc/stm32l1/Doxyfile
+++ b/doc/stm32l1/Doxyfile
@@ -1,13 +1,13 @@
-# HTML Documentation for STM32F1 code level
+# HTML Documentation for STM32L1 code level
-# 14 September 2012
+# 15 December 2012
# (C) Ken Sarkies <ksarkies@internode.on.net>
#---------------------------------------------------------------------------
# Common Include File
#---------------------------------------------------------------------------
-@INCLUDE = ../Doxyfile_common
+@INCLUDE = ../Doxyfile_common
#---------------------------------------------------------------------------
# Local settings
@@ -16,18 +16,21 @@
WARN_LOGFILE = doxygen_stm32l1.log
INPUT = ../../include/libopencm3/license.dox \
- ../../include/libopencm3/stm32/l1 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/l1 \
- ../../lib/stm32/common
+ ../../include/libopencm3/stm32/l1 \
+ ../../include/libopencm3/stm32/common
-EXCLUDE =
+INPUT += ../../lib/stm32/l1 \
+ ../../lib/stm32/common
-EXCLUDE_PATTERNS = *_common_f24.h
+EXCLUDE = ../../include/libopencm3/stm32/common/gpio_common_f24.h
-LAYOUT_FILE = DoxygenLayout_stm32l1.xml
+EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c
-TAGFILES = ../cm3/cm3.tag=../../cm3/html \
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_stm32l1.xml
+
+TAGFILES = ../cm3/cm3.tag=../../cm3/html
GENERATE_TAGFILE = stm32l1.tag
diff --git a/doc/stm32l1/Doxyfile_latex b/doc/stm32l1/Doxyfile_latex
index 80b5600..51d217f 100644
--- a/doc/stm32l1/Doxyfile_latex
+++ b/doc/stm32l1/Doxyfile_latex
@@ -18,13 +18,17 @@ WARN_LOGFILE = doxygen_stm32l1_latex.log
INPUT = ../../include/libopencm3/docmain.dox \
../../include/libopencm3/license.dox \
../../include/libopencm3/stm32/l1 \
- ../../include/libopencm3/stm32/common \
- ../../lib/stm32/l1 \
- ../../lib/stm32/common
+ ../../include/libopencm3/stm32/common
-EXCLUDE = ../../include/libopencm3/stm32/l1/doc-stm32l1.h
+INPUT += ../../lib/stm32/l1 \
+ ../../lib/stm32/common
-EXCLUDE_PATTERNS = *_common_f24.h
+EXCLUDE = ../../include/libopencm3/stm32/l1/doc-stm32l1.h \
+ ../../include/libopencm3/stm32/common/gpio_common_f24.h
+
+EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c
+
+EXCLUDE_PATTERNS =
LAYOUT_FILE = DoxygenLayout_stm32l1.xml
diff --git a/include/libopencm3/stm32/common/crc_common_all.h b/include/libopencm3/stm32/common/crc_common_all.h
new file mode 100644
index 0000000..892f41b
--- /dev/null
+++ b/include/libopencm3/stm32/common/crc_common_all.h
@@ -0,0 +1,85 @@
+/** @addtogroup crc_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_CRC_COMMON_ALL_H
+#define LIBOPENCM3_CRC_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- CRC registers ------------------------------------------------------- */
+
+/* Data register (CRC_DR) */
+#define CRC_DR MMIO32(CRC_BASE + 0x00)
+
+/* Independent data register (CRC_IDR) */
+#define CRC_IDR MMIO32(CRC_BASE + 0x04)
+
+/* Control register (CRC_CR) */
+#define CRC_CR MMIO32(CRC_BASE + 0x08)
+
+/* --- CRC_DR values ------------------------------------------------------- */
+
+/* Bits [31:0]: Data register */
+
+/* --- CRC_IDR values ------------------------------------------------------ */
+
+/* Bits [31:8]: Reserved */
+
+/* Bits [7:0]: General-purpose 8-bit data register bits */
+
+/* --- CRC_CR values ------------------------------------------------------- */
+
+/* Bits [31:1]: Reserved */
+
+/* RESET bit */
+#define CRC_CR_RESET (1 << 0)
+
+/* --- CRC function prototypes --------------------------------------------- */
+
+BEGIN_DECLS
+
+/* TODO */
+
+/**
+ * Reset the CRC calculator to initial values.
+ */
+void crc_reset(void);
+
+/**
+ * Add a word to the crc calculator and return the result.
+ * @param data new word to add to the crc calculator
+ * @return final crc calculator value
+ */
+u32 crc_calculate(u32 data);
+
+/**
+ * Add a block of data to the CRC calculator and return the final result
+ * @param datap pointer to the start of a block of 32bit data words
+ * @param size length of data, in 32bit increments
+ * @return final CRC calculator value
+ */
+u32 crc_calculate_block(u32 *datap, int size);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h
new file mode 100644
index 0000000..c843c55
--- /dev/null
+++ b/include/libopencm3/stm32/common/dac_common_all.h
@@ -0,0 +1,403 @@
+/** @addtogroup dac_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
+#define LIBOPENCM3_DAC_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+
+/* --- DAC registers ------------------------------------------------------- */
+
+/* DAC control register (DAC_CR) */
+#define DAC_CR MMIO32(DAC_BASE + 0x00)
+
+/* DAC software trigger register (DAC_SWTRIGR) */
+#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
+
+/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
+#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
+
+/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
+#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
+
+/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
+#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
+
+/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
+#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
+
+/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
+#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
+
+/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
+#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
+
+/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
+#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
+
+/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
+#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
+
+/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
+#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
+
+/* DAC channel1 data output register (DAC_DOR1) */
+#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
+
+/* DAC channel2 data output register (DAC_DOR2) */
+#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
+
+
+/* --- DAC_CR values ------------------------------------------------------- */
+
+/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
+/* doesn't exist in most members of the STM32F1 family */
+#define DAC_CR_DMAUDRIE2 (1 << 29)
+
+/* DMAEN2: DAC channel2 DMA enable */
+#define DAC_CR_DMAEN2 (1 << 28)
+
+/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
+/* DAC_CR_MAMP2_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP2_SHIFT 24
+/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
+@ingroup STM32F_dac_defines
+
+Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
+@{*/
+#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
+/**@}*/
+
+/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ */
+#define DAC_CR_WAVE2_SHIFT 22
+#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
+/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
+@ingroup STM32F_dac_defines
+
+@li NOISE: Noise wave generation enabled
+@li TRI: Triangle wave generation enabled
+
+@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
+@{*/
+#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
+/**@}*/
+
+/* TSEL2[2:0]: DAC channel2 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event
+ * T8: Timer 8 TRGO event
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL2_SHIFT 19
+/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
+@ingroup STM32F_dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
+@{*/
+#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
+/**@}*/
+
+/* TEN2: DAC channel2 trigger enable */
+#define DAC_CR_TEN2 (1 << 18)
+
+/* BOFF2: DAC channel2 output buffer disable */
+#define DAC_CR_BOFF2 (1 << 17)
+
+/* EN2: DAC channel2 enable */
+#define DAC_CR_EN2 (1 << 16)
+
+/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
+/* doesn't exist in most members of the STM32F1 family */
+#define DAC_CR_DMAUDRIE1 (1 << 13)
+
+/* DMAEN1: DAC channel1 DMA enable */
+#define DAC_CR_DMAEN1 (1 << 12)
+
+/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
+/* DAC_CR_MAMP1_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP1_SHIFT 8
+/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
+@ingroup STM32F_dac_defines
+
+Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
+@{*/
+#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
+/**@}*/
+
+/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ */
+#define DAC_CR_WAVE1_SHIFT 6
+#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
+/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
+@ingroup STM32F_dac_defines
+
+@li DIS: wave generation disabled
+@li NOISE: Noise wave generation enabled
+@li TRI: Triangle wave generation enabled
+
+@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+@{*/
+#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
+/**@}*/
+
+/* TSEL1[2:0]: DAC channel1 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event in connectivity line devices
+ * T8: Timer 8 TRGO event in high-density and XL-density devices
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL1_SHIFT 3
+/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
+@ingroup STM32F_dac_defines
+
+@li T6: Timer 6 TRGO event
+@li T3: Timer 3 TRGO event
+@li T8: Timer 8 TRGO event
+@li T7: Timer 7 TRGO event
+@li T5: Timer 5 TRGO event
+@li T15: Timer 15 TRGO event
+@li T2: Timer 2 TRGO event
+@li T4: Timer 4 TRGO event
+@li E9: External line 9
+@li SW: Software trigger
+
+@note: Refer to the timer documentation for details of the TRGO event.
+@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
+@note: this is <b>not</b> valid for the STM32L1 family.
+@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
+@{*/
+#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
+/**@}*/
+
+/* TEN1: DAC channel1 trigger enable */
+#define DAC_CR_TEN1 (1 << 2)
+
+/* BOFF1: DAC channel1 output buffer disable */
+#define DAC_CR_BOFF1 (1 << 1)
+
+/* EN1: DAC channel1 enable */
+#define DAC_CR_EN1 (1 << 0)
+
+
+/* --- DAC_SWTRIGR values -------------------------------------------------- */
+
+/* SWTRIG2: DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
+
+/* SWTRIG1: DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
+
+
+/* --- DAC_DHR12R1 values -------------------------------------------------- */
+#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
+
+
+/* --- DAC_DHR12L1 values -------------------------------------------------- */
+#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
+#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
+
+
+/* --- DAC_DHR8R1 values --------------------------------------------------- */
+#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
+
+
+/* --- DAC_DHR12R2 values -------------------------------------------------- */
+#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
+#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
+
+
+/* --- DAC_DHR12L2 values -------------------------------------------------- */
+#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
+#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
+
+
+/* --- DAC_DHR8R2 values --------------------------------------------------- */
+#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
+#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
+
+
+/* --- DAC_DHR12RD values -------------------------------------------------- */
+#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
+#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
+#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
+
+
+/* --- DAC_DHR12LD values -------------------------------------------------- */
+#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
+#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
+#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
+
+
+/* --- DAC_DHR8RD values --------------------------------------------------- */
+#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
+#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
+#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
+#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
+
+
+/* --- DAC_DOR1 values ----------------------------------------------------- */
+#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
+#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
+
+
+/* --- DAC_DOR2 values ----------------------------------------------------- */
+#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
+#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
+
+/** DAC channel identifier */
+typedef enum {
+ CHANNEL_1, CHANNEL_2, CHANNEL_D
+} data_channel;
+
+/** DAC data size (8/12 bits), alignment (right/left) */
+typedef enum {
+ RIGHT8, RIGHT12, LEFT12
+} data_align;
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void dac_enable(data_channel dac_channel);
+void dac_disable(data_channel dac_channel);
+void dac_buffer_enable(data_channel dac_channel);
+void dac_buffer_disable(data_channel dac_channel);
+void dac_dma_enable(data_channel dac_channel);
+void dac_dma_disable(data_channel dac_channel);
+void dac_trigger_enable(data_channel dac_channel);
+void dac_trigger_disable(data_channel dac_channel);
+void dac_set_trigger_source(u32 dac_trig_src);
+void dac_set_waveform_generation(u32 dac_wave_ens);
+void dac_disable_waveform_generation(data_channel dac_channel);
+void dac_set_waveform_characteristics(u32 dac_mamp);
+void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel);
+void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
+void dac_software_trigger(data_channel dac_channel);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/i2c_common_all.h b/include/libopencm3/stm32/common/i2c_common_all.h
new file mode 100644
index 0000000..d5cc490
--- /dev/null
+++ b/include/libopencm3/stm32/common/i2c_common_all.h
@@ -0,0 +1,383 @@
+/** @addtogroup i2c_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */
+
+#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
+#define LIBOPENCM3_I2C_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* I2C register base adresses (for convenience) */
+/****************************************************************************/
+/** @defgroup i2c_reg_base I2C register base address
+@ingroup i2c_defines
+
+@{*/
+#define I2C1 I2C1_BASE
+#define I2C2 I2C2_BASE
+/**@}*/
+
+/* --- I2C registers ------------------------------------------------------- */
+
+/* Control register 1 (I2Cx_CR1) */
+#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
+#define I2C1_CR1 I2C_CR1(I2C1)
+#define I2C2_CR1 I2C_CR1(I2C2)
+
+/* Control register 2 (I2Cx_CR2) */
+#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
+#define I2C1_CR2 I2C_CR2(I2C1)
+#define I2C2_CR2 I2C_CR2(I2C2)
+
+/* Own address register 1 (I2Cx_OAR1) */
+#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
+#define I2C1_OAR1 I2C_OAR1(I2C1)
+#define I2C2_OAR1 I2C_OAR1(I2C2)
+
+/* Own address register 2 (I2Cx_OAR2) */
+#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
+#define I2C1_OAR2 I2C_OAR2(I2C1)
+#define I2C2_OAR2 I2C_OAR2(I2C2)
+
+/* Data register (I2Cx_DR) */
+#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
+#define I2C1_DR I2C_DR(I2C1)
+#define I2C2_DR I2C_DR(I2C2)
+
+/* Status register 1 (I2Cx_SR1) */
+#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
+#define I2C1_SR1 I2C_SR1(I2C1)
+#define I2C2_SR1 I2C_SR1(I2C2)
+
+/* Status register 2 (I2Cx_SR2) */
+#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
+#define I2C1_SR2 I2C_SR2(I2C1)
+#define I2C2_SR2 I2C_SR2(I2C2)
+
+/* Clock control register (I2Cx_CCR) */
+#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
+#define I2C1_CCR I2C_CCR(I2C1)
+#define I2C2_CCR I2C_CCR(I2C2)
+
+/* TRISE register (I2Cx_CCR) */
+#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
+#define I2C1_TRISE I2C_TRISE(I2C1)
+#define I2C2_TRISE I2C_TRISE(I2C2)
+
+/* --- I2Cx_CR1 values ----------------------------------------------------- */
+
+/* SWRST: Software reset */
+#define I2C_CR1_SWRST (1 << 15)
+
+/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
+
+/* ALERT: SMBus alert */
+#define I2C_CR1_ALERT (1 << 13)
+
+/* PEC: Packet error checking */
+#define I2C_CR1_PEC (1 << 12)
+
+/* POS: Acknowledge / PEC postition */
+#define I2C_CR1_POS (1 << 11)
+
+/* ACK: Acknowledge enable */
+#define I2C_CR1_ACK (1 << 10)
+
+/* STOP: STOP generation */
+#define I2C_CR1_STOP (1 << 9)
+
+/* START: START generation */
+#define I2C_CR1_START (1 << 8)
+
+/* NOSTRETCH: Clock stretching disable (slave mode) */
+#define I2C_CR1_NOSTRETCH (1 << 7)
+
+/* ENGC: General call enable */
+#define I2C_CR1_ENGC (1 << 6)
+
+/* ENPEC: Enable PEC */
+#define I2C_CR1_ENPEC (1 << 5)
+
+/* ENARP: ARP enable */
+#define I2C_CR1_ENARP (1 << 4)
+
+/* SMBTYPE: SMBus type */
+#define I2C_CR1_SMBTYPE (1 << 3)
+
+/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
+
+/* SMBUS: SMBus mode */
+#define I2C_CR1_SMBUS (1 << 1)
+
+/* PE: Peripheral enable */
+#define I2C_CR1_PE (1 << 0)
+
+/* --- I2Cx_CR2 values ----------------------------------------------------- */
+
+/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
+
+/* LAST: DMA last transfer */
+#define I2C_CR2_LAST (1 << 12)
+
+/* DMAEN: DMA requests enable */
+#define I2C_CR2_DMAEN (1 << 11)
+
+/* ITBUFEN: Buffer interrupt enable */
+#define I2C_CR2_ITBUFEN (1 << 10)
+
+/* ITEVTEN: Event interrupt enable */
+#define I2C_CR2_ITEVTEN (1 << 9)
+
+/* ITERREN: Error interrupt enable */
+#define I2C_CR2_ITERREN (1 << 8)
+
+/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
+
+/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
+/****************************************************************************/
+/** @defgroup i2c_clock I2C clock frequency settings
+@ingroup i2c_defines
+
+@{*/
+#define I2C_CR2_FREQ_2MHZ 0x02
+#define I2C_CR2_FREQ_3MHZ 0x03
+#define I2C_CR2_FREQ_4MHZ 0x04
+#define I2C_CR2_FREQ_5MHZ 0x05
+#define I2C_CR2_FREQ_6MHZ 0x06
+#define I2C_CR2_FREQ_7MHZ 0x07
+#define I2C_CR2_FREQ_8MHZ 0x08
+#define I2C_CR2_FREQ_9MHZ 0x09
+#define I2C_CR2_FREQ_10MHZ 0x0a
+#define I2C_CR2_FREQ_11MHZ 0x0b
+#define I2C_CR2_FREQ_12MHZ 0x0c
+#define I2C_CR2_FREQ_13MHZ 0x0d
+#define I2C_CR2_FREQ_14MHZ 0x0e
+#define I2C_CR2_FREQ_15MHZ 0x0f
+#define I2C_CR2_FREQ_16MHZ 0x10
+#define I2C_CR2_FREQ_17MHZ 0x11
+#define I2C_CR2_FREQ_18MHZ 0x12
+#define I2C_CR2_FREQ_19MHZ 0x13
+#define I2C_CR2_FREQ_20MHZ 0x14
+#define I2C_CR2_FREQ_21MHZ 0x15
+#define I2C_CR2_FREQ_22MHZ 0x16
+#define I2C_CR2_FREQ_23MHZ 0x17
+#define I2C_CR2_FREQ_24MHZ 0x18
+#define I2C_CR2_FREQ_25MHZ 0x19
+#define I2C_CR2_FREQ_26MHZ 0x1a
+#define I2C_CR2_FREQ_27MHZ 0x1b
+#define I2C_CR2_FREQ_28MHZ 0x1c
+#define I2C_CR2_FREQ_29MHZ 0x1d
+#define I2C_CR2_FREQ_30MHZ 0x1e
+#define I2C_CR2_FREQ_31MHZ 0x1f
+#define I2C_CR2_FREQ_32MHZ 0x20
+#define I2C_CR2_FREQ_33MHZ 0x21
+#define I2C_CR2_FREQ_34MHZ 0x22
+#define I2C_CR2_FREQ_35MHZ 0x23
+#define I2C_CR2_FREQ_36MHZ 0x24
+/**@}*/
+
+/* --- I2Cx_OAR1 values ---------------------------------------------------- */
+
+/* ADDMODE: Addressing mode (slave mode) */
+#define I2C_OAR1_ADDMODE (1 << 15)
+#define I2C_OAR1_ADDMODE_7BIT 0
+#define I2C_OAR1_ADDMODE_10BIT 1
+
+/* Note: Bit 14 should always be kept at 1 by software! */
+
+/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
+
+/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
+
+/* --- I2Cx_OAR2 values ---------------------------------------------------- */
+
+/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
+
+/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
+
+/* ENDUAL: Dual addressing mode enable */
+#define I2C_OAR2_ENDUAL (1 << 0)
+
+/* --- I2Cx_DR values ------------------------------------------------------ */
+
+/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
+
+/* DR[7:0] 8-bit data register */
+
+/* --- I2Cx_SR1 values ----------------------------------------------------- */
+
+/* SMBALERT: SMBus alert */
+#define I2C_SR1_SMBALERT (1 << 15)
+
+/* TIMEOUT: Timeout or Tlow Error */
+#define I2C_SR1_TIMEOUT (1 << 14)
+
+/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
+
+/* PECERR: PEC Error in reception */
+#define I2C_SR1_PECERR (1 << 12)
+
+/* OVR: Overrun/Underrun */
+#define I2C_SR1_OVR (1 << 11)
+
+/* AF: Acknowledge failure */
+#define I2C_SR1_AF (1 << 10)
+
+/* ARLO: Arbitration lost (master mode) */
+#define I2C_SR1_ARLO (1 << 9)
+
+/* BERR: Bus error */
+#define I2C_SR1_BERR (1 << 8)
+
+/* TxE: Data register empty (transmitters) */
+#define I2C_SR1_TxE (1 << 7)
+
+/* RxNE: Data register not empty (receivers) */
+#define I2C_SR1_RxNE (1 << 6)
+
+/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
+
+/* STOPF: STOP detection (slave mode) */
+#define I2C_SR1_STOPF (1 << 4)
+
+/* ADD10: 10-bit header sent (master mode) */
+#define I2C_SR1_ADD10 (1 << 3)
+
+/* BTF: Byte transfer finished */
+#define I2C_SR1_BTF (1 << 2)
+
+/* ADDR: Address sent (master mode) / address matched (slave mode) */
+#define I2C_SR1_ADDR (1 << 1)
+
+/* SB: Start bit (master mode) */
+#define I2C_SR1_SB (1 << 0)
+
+/* --- I2Cx_SR2 values ----------------------------------------------------- */
+
+/* Bits [15:8]: PEC[7:0]: Packet error checking register */
+
+/* DUALF: Dual flag (slave mode) */
+#define I2C_SR2_DUALF (1 << 7)
+
+/* SMBHOST: SMBus host header (slave mode) */
+#define I2C_SR2_SMBHOST (1 << 6)
+
+/* SMBDEFAULT: SMBus device default address (slave mode) */
+#define I2C_SR2_SMBDEFAULT (1 << 5)
+
+/* GENCALL: General call address (slave mode) */
+#define I2C_SR2_GENCALL (1 << 4)
+
+/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
+
+/* TRA: Transmitter / receiver */
+#define I2C_SR2_TRA (1 << 2)
+
+/* BUSY: Bus busy */
+#define I2C_SR2_BUSY (1 << 1)
+
+/* MSL: Master / slave */
+#define I2C_SR2_MSL (1 << 0)
+
+/* --- I2Cx_CCR values ----------------------------------------------------- */
+
+/* F/S: I2C Master mode selection (fast / standard) */
+#define I2C_CCR_FS (1 << 15)
+
+/* DUTY: Fast Mode Duty Cycle */
+/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
+@ingroup i2c_defines
+
+@{*/
+#define I2C_CCR_DUTY (1 << 14)
+#define I2C_CCR_DUTY_DIV2 0
+#define I2C_CCR_DUTY_16_DIV_9 1
+/**@}*/
+
+/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
+
+/*
+ * Bits [11:0]:
+ * CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
+ */
+
+/* --- I2Cx_TRISE values --------------------------------------------------- */
+
+/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
+
+/*
+ * Bits [5:0]:
+ * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
+ */
+
+/* --- I2C const definitions ----------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup i2c_rw I2C Read/Write bit
+@ingroup i2c_defines
+
+@{*/
+#define I2C_WRITE 0
+#define I2C_READ 1
+/**@}*/
+
+/* --- I2C funtion prototypes----------------------------------------------- */
+
+BEGIN_DECLS
+
+void i2c_reset(u32 i2c);
+void i2c_peripheral_enable(u32 i2c);
+void i2c_peripheral_disable(u32 i2c);
+void i2c_send_start(u32 i2c);
+void i2c_send_stop(u32 i2c);
+void i2c_clear_stop(u32 i2c);
+void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
+void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
+void i2c_set_fast_mode(u32 i2c);
+void i2c_set_standard_mode(u32 i2c);
+void i2c_set_clock_frequency(u32 i2c, u8 freq);
+void i2c_set_ccr(u32 i2c, u16 freq);
+void i2c_set_trise(u32 i2c, u16 trise);
+void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
+void i2c_send_data(u32 i2c, u8 data);
+uint8_t i2c_get_data(u32 i2c);
+void i2c_enable_interrupt(u32 i2c, u32 interrupt);
+void i2c_disable_interrupt(u32 i2c, u32 interrupt);
+void i2c_enable_ack(u32 i2c);
+void i2c_disable_ack(u32 i2c);
+void i2c_nack_next(u32 i2c);
+void i2c_nack_current(u32 i2c);
+void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
+void i2c_enable_dma(u32 i2c);
+void i2c_disable_dma(u32 i2c);
+void i2c_set_dma_last_transfer(u32 i2c);
+void i2c_clear_dma_last_transfer(u32 i2c);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/i2c_common_f24.h b/include/libopencm3/stm32/common/i2c_common_f24.h
new file mode 100644
index 0000000..22a5733
--- /dev/null
+++ b/include/libopencm3/stm32/common/i2c_common_f24.h
@@ -0,0 +1,35 @@
+/** @addtogroup i2c_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */
+
+#ifndef LIBOPENCM3_I2C_COMMON_F24_H
+#define LIBOPENCM3_I2C_COMMON_F24_H
+
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
+/**@{*/
+
+#define I2C3 I2C3_BASE
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/common/iwdg_common_all.h b/include/libopencm3/stm32/common/iwdg_common_all.h
new file mode 100644
index 0000000..ea2ad16
--- /dev/null
+++ b/include/libopencm3/stm32/common/iwdg_common_all.h
@@ -0,0 +1,109 @@
+/** @addtogroup iwdg_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H */
+
+#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H
+#define LIBOPENCM3_IWDG_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* --- IWDG registers ------------------------------------------------------ */
+
+/* Key Register (IWDG_KR) */
+#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
+
+/* Prescaler register (IWDG_PR) */
+#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
+
+/* Reload register (IWDG_RLR) */
+#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
+
+/* Status register (IWDG_SR) */
+#define IWDG_SR MMIO32(IWDG_BASE + 0x0c)
+
+/* --- IWDG_KR values ------------------------------------------------------ */
+
+/* Bits [31:16]: Reserved. */
+
+/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
+/** @defgroup iwdg_key IWDG Key Values
+@ingroup STM32F_iwdg_defines
+
+@{*/
+#define IWDG_KR_RESET 0xaaaa
+#define IWDG_KR_UNLOCK 0x5555
+#define IWDG_KR_START 0xcccc
+/**@}*/
+
+/* --- IWDG_PR values ------------------------------------------------------ */
+
+/* Bits [31:3]: Reserved. */
+
+/* PR[2:0]: Prescaler divider */
+#define IWDG_PR_LSB 0
+/** @defgroup iwdg_prediv IWDG Prescaler divider
+@ingroup STM32F_iwdg_defines
+
+@{*/
+#define IWDG_PR_DIV4 0x0
+#define IWDG_PR_DIV8 0x1
+#define IWDG_PR_DIV16 0x2
+#define IWDG_PR_DIV32 0x3
+#define IWDG_PR_DIV64 0x4
+#define IWDG_PR_DIV128 0x5
+#define IWDG_PR_DIV256 0x6
+/**@}*/
+/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
+/* #define IWDG_PR_DIV256 0x7 */
+
+/* --- IWDG_RLR values ----------------------------------------------------- */
+
+/* Bits [31:12]: Reserved. */
+
+/* RL[11:0]: Watchdog counter reload value */
+
+/* --- IWDG_SR values ------------------------------------------------------ */
+
+/* Bits [31:2]: Reserved. */
+
+/* RVU: Watchdog counter reload value update */
+#define IWDG_SR_RVU (1 << 1)
+
+/* PVU: Watchdog prescaler value update */
+#define IWDG_SR_PVU (1 << 0)
+
+/* --- IWDG function prototypes---------------------------------------------- */
+
+BEGIN_DECLS
+
+void iwdg_start(void);
+void iwdg_set_period_ms(u32 period);
+bool iwdg_reload_busy(void);
+bool iwdg_prescaler_busy(void);
+void iwdg_reset(void);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h
new file mode 100644
index 0000000..57b1465
--- /dev/null
+++ b/include/libopencm3/stm32/common/spi_common_all.h
@@ -0,0 +1,399 @@
+/** @addtogroup spi_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_SPI_COMMON_ALL_H
+#define LIBOPENCM3_SPI_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/**@{*/
+
+/* Registers can be accessed as 16bit or 32bit values. */
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup spi_reg_base SPI Register base address
+@ingroup spi_defines
+
+@{*/
+#define SPI1 SPI1_BASE
+#define SPI2 SPI2_I2S_BASE
+#define SPI3 SPI3_I2S_BASE
+/**@}*/
+
+/* --- SPI registers ------------------------------------------------------- */
+
+/* Control register 1 (SPIx_CR1) */
+/* Note: Not used in I2S mode. */
+#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
+#define SPI1_CR1 SPI_CR1(SPI1_BASE)
+#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
+#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
+
+/* Control register 2 (SPIx_CR2) */
+#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
+#define SPI1_CR2 SPI_CR2(SPI1_BASE)
+#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
+#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
+
+/* Status register (SPIx_SR) */
+#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
+#define SPI1_SR SPI_SR(SPI1_BASE)
+#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
+#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
+
+/* Data register (SPIx_DR) */
+#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
+#define SPI1_DR SPI_DR(SPI1_BASE)
+#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
+#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
+
+/* CRC polynomial register (SPIx_CRCPR) */
+/* Note: Not used in I2S mode. */
+#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
+#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
+#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
+#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
+
+/* RX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
+#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
+#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
+#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
+
+/* TX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
+#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
+#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
+#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
+
+/* I2S configuration register (SPIx_I2SCFGR) */
+#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
+#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
+#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
+#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
+
+/* I2S prescaler register (SPIx_I2SPR) */
+#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
+#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
+#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
+#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
+
+/* --- SPI_CR1 values ------------------------------------------------------ */
+
+/* Note: None of the CR1 bits are used in I2S mode. */
+
+/* BIDIMODE: Bidirectional data mode enable */
+#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
+#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
+#define SPI_CR1_BIDIMODE (1 << 15)
+
+/* BIDIOE: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIOE (1 << 14)
+
+/* CRCEN: Hardware CRC calculation enable */
+#define SPI_CR1_CRCEN (1 << 13)
+
+/* CRCNEXT: Transmit CRC next */
+#define SPI_CR1_CRCNEXT (1 << 12)
+
+/* DFF: Data frame format */
+/****************************************************************************/
+/** @defgroup spi_dff SPI data frame format
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_DFF_8BIT (0 << 11)
+#define SPI_CR1_DFF_16BIT (1 << 11)
+/**@}*/
+#define SPI_CR1_DFF (1 << 11)
+
+/* RXONLY: Receive only */
+#define SPI_CR1_RXONLY (1 << 10)
+
+/* SSM: Software slave management */
+#define SPI_CR1_SSM (1 << 9)
+
+/* SSI: Internal slave select */
+#define SPI_CR1_SSI (1 << 8)
+
+/* LSBFIRST: Frame format */
+/****************************************************************************/
+/** @defgroup spi_lsbfirst SPI lsb/msb first
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_MSBFIRST (0 << 7)
+#define SPI_CR1_LSBFIRST (1 << 7)
+/**@}*/
+
+/* SPE: SPI enable */
+#define SPI_CR1_SPE (1 << 6)
+
+/* BR[2:0]: Baud rate control */
+/****************************************************************************/
+/** @defgroup spi_baudrate SPI peripheral baud rates
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
+/**@}*/
+/****************************************************************************/
+/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_BR_FPCLK_DIV_2 0x0
+#define SPI_CR1_BR_FPCLK_DIV_4 0x1
+#define SPI_CR1_BR_FPCLK_DIV_8 0x2
+#define SPI_CR1_BR_FPCLK_DIV_16 0x3
+#define SPI_CR1_BR_FPCLK_DIV_32 0x4
+#define SPI_CR1_BR_FPCLK_DIV_64 0x5
+#define SPI_CR1_BR_FPCLK_DIV_128 0x6
+#define SPI_CR1_BR_FPCLK_DIV_256 0x7
+/**@}*/
+
+/* MSTR: Master selection */
+#define SPI_CR1_MSTR (1 << 2)
+
+/* CPOL: Clock polarity */
+/****************************************************************************/
+/** @defgroup spi_cpol SPI clock polarity
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
+#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
+/**@}*/
+#define SPI_CR1_CPOL (1 << 1)
+
+/* CPHA: Clock phase */
+/****************************************************************************/
+/** @defgroup spi_cpha SPI clock phase
+@ingroup spi_defines
+
+@{*/
+#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
+#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
+/**@}*/
+#define SPI_CR1_CPHA (1 << 0)
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* TXEIE: Tx buffer empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7)
+
+/* RXNEIE: Rx buffer not empty interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6)
+
+/* ERRIE: Error interrupt enable */
+#define SPI_CR2_ERRIE (1 << 5)
+
+/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
+
+/* SSOE: SS output enable */
+/* Note: Not used in I2S mode. */
+#define SPI_CR2_SSOE (1 << 2)
+
+/* TXDMAEN: Tx buffer DMA enable */
+#define SPI_CR2_TXDMAEN (1 << 1)
+
+/* RXDMAEN: Rx buffer DMA enable */
+#define SPI_CR2_RXDMAEN (1 << 0)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* BSY: Busy flag */
+#define SPI_SR_BSY (1 << 7)
+
+/* OVR: Overrun flag */
+#define SPI_SR_OVR (1 << 6)
+
+/* MODF: Mode fault */
+/* Note: Not used in I2S mode. */
+#define SPI_SR_MODF (1 << 5)
+
+/* CRCERR: CRC error flag */
+/* Note: Not used in I2S mode. */
+#define SPI_SR_CRCERR (1 << 4)
+
+/* UDR: Underrun flag */
+/* Note: Not used in SPI mode. */
+#define SPI_SR_UDR (1 << 3)
+
+/* CHSIDE: Channel side */
+/* Note: Not used in SPI mode. No meaning in PCM mode. */
+#define SPI_SR_CHSIDE (1 << 2)
+
+/* TXE: Transmit buffer empty */
+#define SPI_SR_TXE (1 << 1)
+
+/* RXNE: Receive buffer not empty */
+#define SPI_SR_RXNE (1 << 0)
+
+/* --- SPI_DR values ------------------------------------------------------- */
+
+/* SPI_DR[15:0]: Data Register. */
+
+/* --- SPI_CRCPR values ---------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
+
+/* --- SPI_RXCRCR values --------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_RXCRCR [15:0]: RX CRC Register. */
+
+/* --- SPI_TXCRCR values --------------------------------------------------- */
+
+/* Note: Not used in I2S mode. */
+/* SPI_TXCRCR [15:0]: TX CRC Register. */
+
+/* --- SPI_I2SCFGR values -------------------------------------------------- */
+
+/* Note: None of these bits are used in SPI mode. */
+
+/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
+
+/* I2SMOD: I2S mode selection */
+#define SPI_I2SCFGR_I2SMOD (1 << 11)
+
+/* I2SE: I2S enable */
+#define SPI_I2SCFGR_I2SE (1 << 10)
+
+/* I2SCFG[9:8]: I2S configuration mode */
+#define SPI_I2SCFGR_I2SCFG_LSB 8
+#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
+#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
+#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
+#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
+
+/* PCMSYNC: PCM frame synchronization */
+#define SPI_I2SCFGR_PCMSYNC (1 << 7)
+
+/* Bit 6: Reserved. Forced to 0 by hardware. */
+
+/* I2SSTD[5:4]: I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_LSB 4
+#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
+#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
+#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
+#define SPI_I2SCFGR_I2SSTD_PCM 0x3
+
+/* CKPOL: Steady state clock polarity */
+#define SPI_I2SCFGR_CKPOL (1 << 3)
+
+/* DATLEN[2:1]: Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_LSB 1
+#define SPI_I2SCFGR_DATLEN_16BIT 0x0
+#define SPI_I2SCFGR_DATLEN_24BIT 0x1
+#define SPI_I2SCFGR_DATLEN_32BIT 0x2
+
+/* CHLEN: Channel length */
+#define SPI_I2SCFGR_CHLEN (1 << 0)
+
+/* --- SPI_I2SPR values ---------------------------------------------------- */
+
+/* Note: None of these bits are used in SPI mode. */
+
+/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
+
+/* MCKOE: Master clock output enable */
+#define SPI_I2SPR_MCKOE (1 << 9)
+
+/* ODD: Odd factor for the prescaler */
+#define SPI_I2SPR_ODD (1 << 8)
+
+/* I2SDIV[7:0]: I2S linear prescaler */
+/* 0 and 1 are forbidden values */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void spi_reset(u32 spi_peripheral);
+int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
+void spi_enable(u32 spi);
+void spi_disable(u32 spi);
+void spi_write(u32 spi, u16 data);
+void spi_send(u32 spi, u16 data);
+u16 spi_read(u32 spi);
+u16 spi_xfer(u32 spi, u16 data);
+void spi_set_bidirectional_mode(u32 spi);
+void spi_set_unidirectional_mode(u32 spi);
+void spi_set_bidirectional_receive_only_mode(u32 spi);
+void spi_set_bidirectional_transmit_only_mode(u32 spi);
+void spi_enable_crc(u32 spi);
+void spi_disable_crc(u32 spi);
+void spi_set_next_tx_from_buffer(u32 spi);
+void spi_set_next_tx_from_crc(u32 spi);
+void spi_set_dff_8bit(u32 spi);
+void spi_set_dff_16bit(u32 spi);
+void spi_set_full_duplex_mode(u32 spi);
+void spi_set_receive_only_mode(u32 spi);
+void spi_disable_software_slave_management(u32 spi);
+void spi_enable_software_slave_management(u32 spi);
+void spi_set_nss_high(u32 spi);
+void spi_set_nss_low(u32 spi);
+void spi_send_lsb_first(u32 spi);
+void spi_send_msb_first(u32 spi);
+void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
+void spi_set_master_mode(u32 spi);
+void spi_set_slave_mode(u32 spi);
+void spi_set_clock_polarity_1(u32 spi);
+void spi_set_clock_polarity_0(u32 spi);
+void spi_set_clock_phase_1(u32 spi);
+void spi_set_clock_phase_0(u32 spi);
+void spi_enable_tx_buffer_empty_interrupt(u32 spi);
+void spi_disable_tx_buffer_empty_interrupt(u32 spi);
+void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_enable_error_interrupt(u32 spi);
+void spi_disable_error_interrupt(u32 spi);
+void spi_enable_ss_output(u32 spi);
+void spi_disable_ss_output(u32 spi);
+void spi_enable_tx_dma(u32 spi);
+void spi_disable_tx_dma(u32 spi);
+void spi_enable_rx_dma(u32 spi);
+void spi_disable_rx_dma(u32 spi);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/common/spi_common_f24.h b/include/libopencm3/stm32/common/spi_common_f24.h
new file mode 100644
index 0000000..6b3764e
--- /dev/null
+++ b/include/libopencm3/stm32/common/spi_common_f24.h
@@ -0,0 +1,50 @@
+/** @addtogroup spi_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_SPI_COMMON_F24_H
+#define LIBOPENCM3_SPI_COMMON_F24_H
+
+/**@{*/
+
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+/*
+ * This file extends the common STM32 version with definitions only
+ * applicable to the STM32F2/4 series of devices.
+ */
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* FRF: Frame format */
+/* Note: Not used in I2S mode. */
+#define SPI_CR2_FRF (1 << 4)
+#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
+#define SPI_CR2_FRF_TI_MODE (1 << 4)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* TIFRFE: TI frame format error */
+#define SPI_SR_TIFRFE (1 << 8)
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/usart_common_all.h b/include/libopencm3/stm32/common/usart_common_all.h
new file mode 100644
index 0000000..1334420
--- /dev/null
+++ b/include/libopencm3/stm32/common/usart_common_all.h
@@ -0,0 +1,369 @@
+/** @addtogroup usart_defines */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_USART_COMMON_ALL_H
+#define LIBOPENCM3_USART_COMMON_ALL_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup usart_reg_base USART register base addresses
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART1 USART1_BASE
+#define USART2 USART2_BASE
+#define USART3 USART3_BASE
+/**@}*/
+#define UART4 UART4_BASE
+#define UART5 UART5_BASE
+
+/* --- USART registers ----------------------------------------------------- */
+
+/* Status register (USARTx_SR) */
+#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
+#define USART1_SR USART_SR(USART1_BASE)
+#define USART2_SR USART_SR(USART2_BASE)
+#define USART3_SR USART_SR(USART3_BASE)
+#define UART4_SR USART_SR(UART4_BASE)
+#define UART5_SR USART_SR(UART5_BASE)
+
+/* Data register (USARTx_DR) */
+#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
+#define USART1_DR USART_DR(USART1_BASE)
+#define USART2_DR USART_DR(USART2_BASE)
+#define USART3_DR USART_DR(USART3_BASE)
+#define UART4_DR USART_DR(UART4_BASE)
+#define UART5_DR USART_DR(UART5_BASE)
+
+/* Baud rate register (USARTx_BRR) */
+#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
+#define USART1_BRR USART_BRR(USART1_BASE)
+#define USART2_BRR USART_BRR(USART2_BASE)
+#define USART3_BRR USART_BRR(USART3_BASE)
+#define UART4_BRR USART_BRR(UART4_BASE)
+#define UART5_BRR USART_BRR(UART5_BASE)
+
+/* Control register 1 (USARTx_CR1) */
+#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
+#define USART1_CR1 USART_CR1(USART1_BASE)
+#define USART2_CR1 USART_CR1(USART2_BASE)
+#define USART3_CR1 USART_CR1(USART3_BASE)
+#define UART4_CR1 USART_CR1(UART4_BASE)
+#define UART5_CR1 USART_CR1(UART5_BASE)
+
+/* Control register 2 (USARTx_CR2) */
+#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
+#define USART1_CR2 USART_CR2(USART1_BASE)
+#define USART2_CR2 USART_CR2(USART2_BASE)
+#define USART3_CR2 USART_CR2(USART3_BASE)
+#define UART4_CR2 USART_CR2(UART4_BASE)
+#define UART5_CR2 USART_CR2(UART5_BASE)
+
+/* Control register 3 (USARTx_CR3) */
+#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
+#define USART1_CR3 USART_CR3(USART1_BASE)
+#define USART2_CR3 USART_CR3(USART2_BASE)
+#define USART3_CR3 USART_CR3(USART3_BASE)
+#define UART4_CR3 USART_CR3(UART4_BASE)
+#define UART5_CR3 USART_CR3(UART5_BASE)
+
+/* Guard time and prescaler register (USARTx_GTPR) */
+#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
+#define USART1_GTPR USART_GTPR(USART1_BASE)
+#define USART2_GTPR USART_GTPR(USART2_BASE)
+#define USART3_GTPR USART_GTPR(USART3_BASE)
+#define UART4_GTPR USART_GTPR(UART4_BASE)
+#define UART5_GTPR USART_GTPR(UART5_BASE)
+
+/* --- USART_SR values ----------------------------------------------------- */
+/****************************************************************************/
+/** @defgroup usart_sr_flags USART Status register Flags
+@ingroup STM32F_usart_defines
+
+@{*/
+
+/** CTS: CTS flag */
+/** @note: undefined on UART4 and UART5 */
+#define USART_SR_CTS (1 << 9)
+
+/** LBD: LIN break detection flag */
+#define USART_SR_LBD (1 << 8)
+
+/** TXE: Transmit data buffer empty */
+#define USART_SR_TXE (1 << 7)
+
+/** TC: Transmission complete */
+#define USART_SR_TC (1 << 6)
+
+/** RXNE: Read data register not empty */
+#define USART_SR_RXNE (1 << 5)
+
+/** IDLE: Idle line detected */
+#define USART_SR_IDLE (1 << 4)
+
+/** ORE: Overrun error */
+#define USART_SR_ORE (1 << 3)
+
+/** NE: Noise error flag */
+#define USART_SR_NE (1 << 2)
+
+/** FE: Framing error */
+#define USART_SR_FE (1 << 1)
+
+/** PE: Parity error */
+#define USART_SR_PE (1 << 0)
+/**@}*/
+
+/* --- USART_DR values ----------------------------------------------------- */
+
+/* USART_DR[8:0]: DR[8:0]: Data value */
+#define USART_DR_MASK 0x1FF
+
+/* --- USART_BRR values ---------------------------------------------------- */
+
+/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
+/* DIV_Fraction[3:0]: fraction of USARTDIV */
+#define USART_BRR_DIV_FRACTION_MASK 0xF
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* UE: USART enable */
+#define USART_CR1_UE (1 << 13)
+
+/* M: Word length */
+#define USART_CR1_M (1 << 12)
+
+/* WAKE: Wakeup method */
+#define USART_CR1_WAKE (1 << 11)
+
+/* PCE: Parity control enable */
+#define USART_CR1_PCE (1 << 10)
+
+/* PS: Parity selection */
+#define USART_CR1_PS (1 << 9)
+
+/* PEIE: PE interrupt enable */
+#define USART_CR1_PEIE (1 << 8)
+
+/* TXEIE: TXE interrupt enable */
+#define USART_CR1_TXEIE (1 << 7)
+
+/* TCIE: Transmission complete interrupt enable */
+#define USART_CR1_TCIE (1 << 6)
+
+/* RXNEIE: RXNE interrupt enable */
+#define USART_CR1_RXNEIE (1 << 5)
+
+/* IDLEIE: IDLE interrupt enable */
+#define USART_CR1_IDLEIE (1 << 4)
+
+/* TE: Transmitter enable */
+#define USART_CR1_TE (1 << 3)
+
+/* RE: Receiver enable */
+#define USART_CR1_RE (1 << 2)
+
+/* RWU: Receiver wakeup */
+#define USART_CR1_RWU (1 << 1)
+
+/* SBK: Send break */
+#define USART_CR1_SBK (1 << 0)
+
+/* --- USART_CR2 values ---------------------------------------------------- */
+
+/* LINEN: LIN mode enable */
+#define USART_CR2_LINEN (1 << 14)
+
+/* STOP[13:12]: STOP bits */
+#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
+#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
+#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
+#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
+#define USART_CR2_STOPBITS_MASK (0x03 << 12)
+#define USART_CR2_STOPBITS_SHIFT 12
+
+/* CLKEN: Clock enable */
+#define USART_CR2_CLKEN (1 << 11)
+
+/* CPOL: Clock polarity */
+#define USART_CR2_CPOL (1 << 10)
+
+/* CPHA: Clock phase */
+#define USART_CR2_CPHA (1 << 9)
+
+/* LBCL: Last bit clock pulse */
+#define USART_CR2_LBCL (1 << 8)
+
+/* LBDIE: LIN break detection interrupt enable */
+#define USART_CR2_LBDIE (1 << 6)
+
+/* LBDL: LIN break detection length */
+#define USART_CR2_LBDL (1 << 5)
+
+/* ADD[3:0]: Addres of the usart node */
+#define USART_CR2_ADD_MASK 0xF
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* CTSIE: CTS interrupt enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_CTSIE (1 << 10)
+
+/* CTSE: CTS enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_CTSE (1 << 9)
+
+/* RTSE: RTS enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_RTSE (1 << 8)
+
+/* DMAT: DMA enable transmitter */
+/* Note: N/A on UART5 */
+#define USART_CR3_DMAT (1 << 7)
+
+/* DMAR: DMA enable receiver */
+/* Note: N/A on UART5 */
+#define USART_CR3_DMAR (1 << 6)
+
+/* SCEN: Smartcard mode enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_SCEN (1 << 5)
+
+/* NACK: Smartcard NACK enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_NACK (1 << 4)
+
+/* HDSEL: Half-duplex selection */
+#define USART_CR3_HDSEL (1 << 3)
+
+/* IRLP: IrDA low-power */
+#define USART_CR3_IRLP (1 << 2)
+
+/* IREN: IrDA mode enable */
+#define USART_CR3_IREN (1 << 1)
+
+/* EIE: Error interrupt enable */
+#define USART_CR3_EIE (1 << 0)
+
+/* --- USART_GTPR values --------------------------------------------------- */
+
+/* GT[7:0]: Guard time value */
+/* Note: N/A on UART4 & UART5 */
+#define USART_GTPR_GT_MASK (0xFF << 8)
+
+/* PSC[7:0]: Prescaler value */
+/* Note: N/A on UART4/5 */
+#define USART_GTPR_PSC_MASK 0xFF
+
+/* TODO */ /* Note to Uwe: what needs to be done here? */
+
+/* --- Convenience defines ------------------------------------------------- */
+
+/* CR1_PCE / CR1_PS combined values */
+/****************************************************************************/
+/** @defgroup usart_cr1_parity USART Parity Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_PARITY_NONE 0x00
+#define USART_PARITY_EVEN USART_CR1_PCE
+#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
+/**@}*/
+#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
+
+/* CR1_TE/CR1_RE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_MODE_RX USART_CR1_RE
+#define USART_MODE_TX USART_CR1_TE
+#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
+/**@}*/
+#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
+
+/****************************************************************************/
+/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
+#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
+#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
+#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
+/**@}*/
+
+/* CR3_CTSE/CR3_RTSE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define USART_FLOWCONTROL_NONE 0x00
+#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
+#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
+#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+/**@}*/
+#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void usart_set_baudrate(u32 usart, u32 baud);
+void usart_set_databits(u32 usart, u32 bits);
+void usart_set_stopbits(u32 usart, u32 stopbits);
+void usart_set_parity(u32 usart, u32 parity);
+void usart_set_mode(u32 usart, u32 mode);
+void usart_set_flow_control(u32 usart, u32 flowcontrol);
+void usart_enable(u32 usart);
+void usart_disable(u32 usart);
+void usart_send(u32 usart, u16 data);
+u16 usart_recv(u32 usart);
+void usart_wait_send_ready(u32 usart);
+void usart_wait_recv_ready(u32 usart);
+void usart_send_blocking(u32 usart, u16 data);
+u16 usart_recv_blocking(u32 usart);
+void usart_enable_rx_dma(u32 usart);
+void usart_disable_rx_dma(u32 usart);
+void usart_enable_tx_dma(u32 usart);
+void usart_disable_tx_dma(u32 usart);
+void usart_enable_rx_interrupt(u32 usart);
+void usart_disable_rx_interrupt(u32 usart);
+void usart_enable_tx_interrupt(u32 usart);
+void usart_disable_tx_interrupt(u32 usart);
+bool usart_get_flag(u32 usart, u32 flag);
+bool usart_get_interrupt_source(u32 usart, u32 flag);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/include/libopencm3/stm32/common/usart_common_f24.h b/include/libopencm3/stm32/common/usart_common_f24.h
new file mode 100644
index 0000000..089a0c2
--- /dev/null
+++ b/include/libopencm3/stm32/common/usart_common_f24.h
@@ -0,0 +1,66 @@
+/** @addtogroup usart_defines */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H */
+
+#ifndef LIBOPENCM3_USART_COMMON_F24_H
+#define LIBOPENCM3_USART_COMMON_F24_H
+
+#include <libopencm3/stm32/common/usart_common_all.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+#define USART6 USART6_BASE
+
+/* --- USART registers ----------------------------------------------------- */
+
+/* Status register (USARTx_SR) */
+#define USART6_SR USART_SR(USART6_BASE)
+
+/* Data register (USARTx_DR) */
+#define USART6_DR USART_DR(USART6_BASE)
+
+/* Baud rate register (USARTx_BRR) */
+#define USART6_BRR USART_BRR(USART6_BASE)
+
+/* Control register 1 (USARTx_CR1) */
+#define USART6_CR1 USART_CR1(USART6_BASE)
+
+/* Control register 2 (USARTx_CR2) */
+#define USART6_CR2 USART_CR2(USART6_BASE)
+
+/* Control register 3 (USARTx_CR3) */
+#define USART6_CR3 USART_CR3(USART6_BASE)
+
+/* Guard time and prescaler register (USARTx_GTPR) */
+#define USART6_GTPR USART_GTPR(USART6_BASE)
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* OVER8: Oversampling mode */
+#define USART_CR1_OVER8 (1 << 15)
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* ONEBIT: One sample bit method enable */
+#define USART_CR3_ONEBIT (1 << 11)
+
+#endif
diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h
index aa30182..3d43061 100644
--- a/include/libopencm3/stm32/crc.h
+++ b/include/libopencm3/stm32/crc.h
@@ -1,22 +1,8 @@
-/** @defgroup crc_defines CRC Defines
+/* This provides unification of code over STM32F subfamilies */
-@brief <b>libopencm3 Defined Constants and Types for the STM32F CRC Generator </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,66 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_CRC_H
-#define LIBOPENCM3_CRC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- CRC registers ------------------------------------------------------- */
-
-/* Data register (CRC_DR) */
-#define CRC_DR MMIO32(CRC_BASE + 0x00)
-
-/* Independent data register (CRC_IDR) */
-#define CRC_IDR MMIO32(CRC_BASE + 0x04)
-
-/* Control register (CRC_CR) */
-#define CRC_CR MMIO32(CRC_BASE + 0x08)
-
-/* --- CRC_DR values ------------------------------------------------------- */
-
-/* Bits [31:0]: Data register */
-
-/* --- CRC_IDR values ------------------------------------------------------ */
-
-/* Bits [31:8]: Reserved */
-
-/* Bits [7:0]: General-purpose 8-bit data register bits */
-
-/* --- CRC_CR values ------------------------------------------------------- */
-
-/* Bits [31:1]: Reserved */
-
-/* RESET bit */
-#define CRC_CR_RESET (1 << 0)
-
-/* --- CRC function prototypes --------------------------------------------- */
-
-BEGIN_DECLS
-
-/* TODO */
-
-/**
- * Reset the CRC calculator to initial values.
- */
-void crc_reset(void);
-
-/**
- * Add a word to the crc calculator and return the result.
- * @param data new word to add to the crc calculator
- * @return final crc calculator value
- */
-u32 crc_calculate(u32 data);
-
-/**
- * Add a block of data to the CRC calculator and return the final result
- * @param datap pointer to the start of a block of 32bit data words
- * @param size length of data, in 32bit increments
- * @return final CRC calculator value
- */
-u32 crc_calculate_block(u32 *datap, int size);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/crc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/crc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/crc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/crc.h>
+#else
+# error "stm32 family not defined."
#endif
+
diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h
index 75d4edb..242ef89 100644
--- a/include/libopencm3/stm32/dac.h
+++ b/include/libopencm3/stm32/dac.h
@@ -1,24 +1,8 @@
-/** @defgroup STM32F_dac_defines DAC Defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,386 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_DAC_H
-#define LIBOPENCM3_DAC_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-
-/* --- DAC registers ------------------------------------------------------- */
-
-/* DAC control register (DAC_CR) */
-#define DAC_CR MMIO32(DAC_BASE + 0x00)
-
-/* DAC software trigger register (DAC_SWTRIGR) */
-#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
-
-/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
-#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
-
-/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
-#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
-
-/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
-#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
-
-/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
-#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
-
-/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
-#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
-
-/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
-#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
-
-/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
-#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
-
-/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
-#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
-
-/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
-#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
-
-/* DAC channel1 data output register (DAC_DOR1) */
-#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
-
-/* DAC channel2 data output register (DAC_DOR2) */
-#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
-
-
-/* --- DAC_CR values ------------------------------------------------------- */
-
-/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
-/* doesn't exist in most members of the STM32F1 family */
-#define DAC_CR_DMAUDRIE2 (1 << 29)
-
-/* DMAEN2: DAC channel2 DMA enable */
-#define DAC_CR_DMAEN2 (1 << 28)
-
-/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
-/* DAC_CR_MAMP2_n:
- * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
- */
-#define DAC_CR_MAMP2_SHIFT 24
-/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
-@ingroup STM32F_dac_defines
-
-Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
-@{*/
-#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
-#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
-/**@}*/
-
-/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
-/* Legend:
- * DIS: wave generation disabled
- * NOISE: Noise wave generation enabled
- * TRI: Triangle wave generation enabled
- *
- * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
- */
-#define DAC_CR_WAVE2_SHIFT 22
-#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
-/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
-@ingroup STM32F_dac_defines
-
-@li NOISE: Noise wave generation enabled
-@li TRI: Triangle wave generation enabled
-
-@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
-@{*/
-#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
-#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
-/**@}*/
-
-/* TSEL2[2:0]: DAC channel2 trigger selection */
-/* Legend:
- *
- * T6: Timer 6 TRGO event
- * T3: Timer 3 TRGO event
- * T8: Timer 8 TRGO event
- * T7: Timer 7 TRGO event
- * T5: Timer 5 TRGO event
- * T15: Timer 15 TRGO event
- * T2: Timer 2 TRGO event
- * T4: Timer 4 TRGO event
- * E9: External line9
- * SW: Software trigger
- *
- * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
- * Note: T3 == T8; T5 == T15; not both present on one device
- * Note: this is *not* valid for the STM32L1 family
- */
-#define DAC_CR_TSEL2_SHIFT 19
-/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
-@ingroup STM32F_dac_defines
-
-@li T6: Timer 6 TRGO event
-@li T3: Timer 3 TRGO event
-@li T8: Timer 8 TRGO event
-@li T7: Timer 7 TRGO event
-@li T5: Timer 5 TRGO event
-@li T15: Timer 15 TRGO event
-@li T2: Timer 2 TRGO event
-@li T4: Timer 4 TRGO event
-@li E9: External line9
-@li SW: Software trigger
-
-@note: Refer to the timer documentation for details of the TRGO event.
-@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
-@note: this is <b>not</b> valid for the STM32L1 family.
-@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
-@{*/
-#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
-#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
-/**@}*/
-
-/* TEN2: DAC channel2 trigger enable */
-#define DAC_CR_TEN2 (1 << 18)
-
-/* BOFF2: DAC channel2 output buffer disable */
-#define DAC_CR_BOFF2 (1 << 17)
-
-/* EN2: DAC channel2 enable */
-#define DAC_CR_EN2 (1 << 16)
-
-/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
-/* doesn't exist in most members of the STM32F1 family */
-#define DAC_CR_DMAUDRIE1 (1 << 13)
-
-/* DMAEN1: DAC channel1 DMA enable */
-#define DAC_CR_DMAEN1 (1 << 12)
-
-/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
-/* DAC_CR_MAMP1_n:
- * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
- */
-#define DAC_CR_MAMP1_SHIFT 8
-/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
-@ingroup STM32F_dac_defines
-
-Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
-@{*/
-#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
-#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
-/**@}*/
-
-/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
-/* Legend:
- * DIS: wave generation disabled
- * NOISE: Noise wave generation enabled
- * TRI: Triangle wave generation enabled
- *
- * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
- */
-#define DAC_CR_WAVE1_SHIFT 6
-#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
-/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
-@ingroup STM32F_dac_defines
-
-@li DIS: wave generation disabled
-@li NOISE: Noise wave generation enabled
-@li TRI: Triangle wave generation enabled
-
-@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
-@{*/
-#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
-#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
-/**@}*/
-
-/* TSEL1[2:0]: DAC channel1 trigger selection */
-/* Legend:
- *
- * T6: Timer 6 TRGO event
- * T3: Timer 3 TRGO event in connectivity line devices
- * T8: Timer 8 TRGO event in high-density and XL-density devices
- * T7: Timer 7 TRGO event
- * T5: Timer 5 TRGO event
- * T15: Timer 15 TRGO event
- * T2: Timer 2 TRGO event
- * T4: Timer 4 TRGO event
- * E9: External line9
- * SW: Software trigger
- *
- * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
- * Note: T3 == T8; T5 == T15; not both present on one device
- * Note: this is *not* valid for the STM32L1 family
- */
-#define DAC_CR_TSEL1_SHIFT 3
-/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
-@ingroup STM32F_dac_defines
-
-@li T6: Timer 6 TRGO event
-@li T3: Timer 3 TRGO event
-@li T8: Timer 8 TRGO event
-@li T7: Timer 7 TRGO event
-@li T5: Timer 5 TRGO event
-@li T15: Timer 15 TRGO event
-@li T2: Timer 2 TRGO event
-@li T4: Timer 4 TRGO event
-@li E9: External line 9
-@li SW: Software trigger
-
-@note: Refer to the timer documentation for details of the TRGO event.
-@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
-@note: this is <b>not</b> valid for the STM32L1 family.
-@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
-@{*/
-#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
-#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
-/**@}*/
-
-/* TEN1: DAC channel1 trigger enable */
-#define DAC_CR_TEN1 (1 << 2)
-
-/* BOFF1: DAC channel1 output buffer disable */
-#define DAC_CR_BOFF1 (1 << 1)
-
-/* EN1: DAC channel1 enable */
-#define DAC_CR_EN1 (1 << 0)
-
-
-/* --- DAC_SWTRIGR values -------------------------------------------------- */
-
-/* SWTRIG2: DAC channel2 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
-
-/* SWTRIG1: DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
-
-
-/* --- DAC_DHR12R1 values -------------------------------------------------- */
-#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
-
-
-/* --- DAC_DHR12L1 values -------------------------------------------------- */
-#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
-#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
-
-
-/* --- DAC_DHR8R1 values --------------------------------------------------- */
-#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
-
-
-/* --- DAC_DHR12R2 values -------------------------------------------------- */
-#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
-#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
-
-
-/* --- DAC_DHR12L2 values -------------------------------------------------- */
-#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
-#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
-
-
-/* --- DAC_DHR8R2 values --------------------------------------------------- */
-#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
-#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
-
-
-/* --- DAC_DHR12RD values -------------------------------------------------- */
-#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
-#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
-#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
-
-
-/* --- DAC_DHR12LD values -------------------------------------------------- */
-#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
-#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
-#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
-
-
-/* --- DAC_DHR8RD values --------------------------------------------------- */
-#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
-#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
-#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
-#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
-
-
-/* --- DAC_DOR1 values ----------------------------------------------------- */
-#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
-#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
-
-
-/* --- DAC_DOR2 values ----------------------------------------------------- */
-#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
-#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
-
-/** DAC channel identifier */
-typedef enum {
- CHANNEL_1, CHANNEL_2, CHANNEL_D
-} data_channel;
-
-/** DAC data size (8/12 bits), alignment (right/left) */
-typedef enum {
- RIGHT8, RIGHT12, LEFT12
-} data_align;
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void dac_enable(data_channel dac_channel);
-void dac_disable(data_channel dac_channel);
-void dac_buffer_enable(data_channel dac_channel);
-void dac_buffer_disable(data_channel dac_channel);
-void dac_dma_enable(data_channel dac_channel);
-void dac_dma_disable(data_channel dac_channel);
-void dac_trigger_enable(data_channel dac_channel);
-void dac_trigger_disable(data_channel dac_channel);
-void dac_set_trigger_source(u32 dac_trig_src);
-void dac_set_waveform_generation(u32 dac_wave_ens);
-void dac_disable_waveform_generation(data_channel dac_channel);
-void dac_set_waveform_characteristics(u32 dac_mamp);
-void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel);
-void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
-void dac_software_trigger(data_channel dac_channel);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/dac.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/dac.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/dac.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/dac.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/f1/crc.h b/include/libopencm3/stm32/f1/crc.h
new file mode 100644
index 0000000..c3b9939
--- /dev/null
+++ b/include/libopencm3/stm32/f1/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator </b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f1/dac.h b/include/libopencm3/stm32/f1/dac.h
new file mode 100644
index 0000000..1e6ecfa
--- /dev/null
+++ b/include/libopencm3/stm32/f1/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx DAC</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h
index 7fb93c1..580c501 100644
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
-#include <libopencm3/stm32/f1/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/gpio_common_all.h>
/* --- Convenience macros -------------------------------------------------- */
diff --git a/include/libopencm3/stm32/f1/i2c.h b/include/libopencm3/stm32/f1/i2c.h
new file mode 100644
index 0000000..44d906a
--- /dev/null
+++ b/include/libopencm3/stm32/f1/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx I2C </b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/iwdg.h b/include/libopencm3/stm32/f1/iwdg.h
new file mode 100644
index 0000000..c8a1e85
--- /dev/null
+++ b/include/libopencm3/stm32/f1/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog Timer</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/spi.h b/include/libopencm3/stm32/f1/spi.h
new file mode 100644
index 0000000..eb434a1
--- /dev/null
+++ b/include/libopencm3/stm32/f1/spi.h
@@ -0,0 +1,40 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx SPI</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f1/usart.h b/include/libopencm3/stm32/f1/usart.h
new file mode 100644
index 0000000..24a8137
--- /dev/null
+++ b/include/libopencm3/stm32/f1/usart.h
@@ -0,0 +1,40 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx USART</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/crc.h b/include/libopencm3/stm32/f2/crc.h
new file mode 100644
index 0000000..bf2d9fe
--- /dev/null
+++ b/include/libopencm3/stm32/f2/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator </b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f2/dac.h b/include/libopencm3/stm32/f2/dac.h
new file mode 100644
index 0000000..f6e16e7
--- /dev/null
+++ b/include/libopencm3/stm32/f2/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx DAC</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/gpio.h b/include/libopencm3/stm32/f2/gpio.h
index 3ff2ba6..099fb38 100644
--- a/include/libopencm3/stm32/f2/gpio.h
+++ b/include/libopencm3/stm32/f2/gpio.h
@@ -35,7 +35,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
-#include <libopencm3/stm32/f2/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f2/i2c.h b/include/libopencm3/stm32/f2/i2c.h
new file mode 100644
index 0000000..3dc1652
--- /dev/null
+++ b/include/libopencm3/stm32/f2/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx I2C </b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_f24.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/iwdg.h b/include/libopencm3/stm32/f2/iwdg.h
new file mode 100644
index 0000000..d15f9a9
--- /dev/null
+++ b/include/libopencm3/stm32/f2/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog Timer</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f2/spi.h b/include/libopencm3/stm32/f2/spi.h
index df5021c..c1a5f45 100644
--- a/include/libopencm3/stm32/f2/spi.h
+++ b/include/libopencm3/stm32/f2/spi.h
@@ -1,8 +1,21 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx SPI</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,27 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_F2_H
-#define LIBOPENCM3_SPI_F2_H
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
-#include <libopencm3/stm32/spi.h>
-
-/*
- * This file extends the common STM32 version with definitions only
- * applicable to the STM32F2 series of devices.
- */
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* FRF: Frame format */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_FRF (1 << 4)
-#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
-#define SPI_CR2_FRF_TI_MODE (1 << 4)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* TIFRFE: TI frame format error */
-#define SPI_SR_TIFRFE (1 << 8)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f2/usart.h b/include/libopencm3/stm32/f2/usart.h
index 1c007ab..31314bc 100644
--- a/include/libopencm3/stm32/f2/usart.h
+++ b/include/libopencm3/stm32/f2/usart.h
@@ -1,9 +1,21 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32F2xx USART</b>
+
+@ingroup STM32F2xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -18,46 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_USART_F2_H
-#define LIBOPENCM3_USART_F2_H
-
-#include <libopencm3/stm32/usart.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-#define USART6 USART6_BASE
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
-/* --- USART registers ----------------------------------------------------- */
-
-/* Status register (USARTx_SR) */
-#define USART6_SR USART_SR(USART6_BASE)
-
-/* Data register (USARTx_DR) */
-#define USART6_DR USART_DR(USART6_BASE)
-
-/* Baud rate register (USARTx_BRR) */
-#define USART6_BRR USART_BRR(USART6_BASE)
-
-/* Control register 1 (USARTx_CR1) */
-#define USART6_CR1 USART_CR1(USART6_BASE)
-
-/* Control register 2 (USARTx_CR2) */
-#define USART6_CR2 USART_CR2(USART6_BASE)
-
-/* Control register 3 (USARTx_CR3) */
-#define USART6_CR3 USART_CR3(USART6_BASE)
-
-/* Guard time and prescaler register (USARTx_GTPR) */
-#define USART6_GTPR USART_GTPR(USART6_BASE)
-
-/* --- USART_CR1 values ---------------------------------------------------- */
-
-/* OVER8: Oversampling mode */
-#define USART_CR1_OVER8 (1 << 15)
-
-/* --- USART_CR3 values ---------------------------------------------------- */
-
-/* ONEBIT: One sample bit method enable */
-#define USART_CR3_ONEBIT (1 << 11)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/crc.h b/include/libopencm3/stm32/f4/crc.h
new file mode 100644
index 0000000..1c375fa
--- /dev/null
+++ b/include/libopencm3/stm32/f4/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator </b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/f4/dac.h b/include/libopencm3/stm32/f4/dac.h
new file mode 100644
index 0000000..0961c30
--- /dev/null
+++ b/include/libopencm3/stm32/f4/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx DAC</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/gpio.h b/include/libopencm3/stm32/f4/gpio.h
index 9e0685f..4eedc6e 100644
--- a/include/libopencm3/stm32/f4/gpio.h
+++ b/include/libopencm3/stm32/f4/gpio.h
@@ -35,7 +35,7 @@ LGPL License Terms @ref lgpl_license
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
-#include <libopencm3/stm32/f4/memorymap.h>
+#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif
diff --git a/include/libopencm3/stm32/f4/i2c.h b/include/libopencm3/stm32/f4/i2c.h
new file mode 100644
index 0000000..e1a41cf
--- /dev/null
+++ b/include/libopencm3/stm32/f4/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx I2C </b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_f24.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/iwdg.h b/include/libopencm3/stm32/f4/iwdg.h
new file mode 100644
index 0000000..d5baef4
--- /dev/null
+++ b/include/libopencm3/stm32/f4/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog Timer</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/f4/spi.h b/include/libopencm3/stm32/f4/spi.h
index c852a41..6589290 100644
--- a/include/libopencm3/stm32/f4/spi.h
+++ b/include/libopencm3/stm32/f4/spi.h
@@ -1,8 +1,21 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx SPI</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -17,27 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_F4_H
-#define LIBOPENCM3_SPI_F4_H
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
-#include <libopencm3/stm32/spi.h>
-
-/*
- * This file extends the common STM32 version with definitions only
- * applicable to the STM32F4 series of devices.
- */
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* FRF: Frame format */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_FRF (1 << 4)
-#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
-#define SPI_CR2_FRF_TI_MODE (1 << 4)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* TIFRFE: TI frame format error */
-#define SPI_SR_TIFRFE (1 << 8)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/f4/usart.h b/include/libopencm3/stm32/f4/usart.h
index ac113da..740f0a8 100644
--- a/include/libopencm3/stm32/f4/usart.h
+++ b/include/libopencm3/stm32/f4/usart.h
@@ -1,9 +1,21 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32F4xx USART</b>
+
+@ingroup STM32F4xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -18,46 +30,11 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_USART_F4_H
-#define LIBOPENCM3_USART_F4_H
-
-#include <libopencm3/stm32/usart.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-#define USART6 USART6_BASE
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
-/* --- USART registers ----------------------------------------------------- */
-
-/* Status register (USARTx_SR) */
-#define USART6_SR USART_SR(USART6_BASE)
-
-/* Data register (USARTx_DR) */
-#define USART6_DR USART_DR(USART6_BASE)
-
-/* Baud rate register (USARTx_BRR) */
-#define USART6_BRR USART_BRR(USART6_BASE)
-
-/* Control register 1 (USARTx_CR1) */
-#define USART6_CR1 USART_CR1(USART6_BASE)
-
-/* Control register 2 (USARTx_CR2) */
-#define USART6_CR2 USART_CR2(USART6_BASE)
-
-/* Control register 3 (USARTx_CR3) */
-#define USART6_CR3 USART_CR3(USART6_BASE)
-
-/* Guard time and prescaler register (USARTx_GTPR) */
-#define USART6_GTPR USART_GTPR(USART6_BASE)
-
-/* --- USART_CR1 values ---------------------------------------------------- */
-
-/* OVER8: Oversampling mode */
-#define USART_CR1_OVER8 (1 << 15)
-
-/* --- USART_CR3 values ---------------------------------------------------- */
-
-/* ONEBIT: One sample bit method enable */
-#define USART_CR3_ONEBIT (1 << 11)
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_f24.h>
#endif
+
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index 1b2dc0e..c1d0793 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -1,24 +1,8 @@
-/** @defgroup i2c_defines I2C Defines
-
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
-
-@date 12 October 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,364 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_I2C_H
-#define LIBOPENCM3_I2C_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/**@{*/
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* I2C register base adresses (for convenience) */
-/****************************************************************************/
-/** @defgroup i2c_reg_base I2C register base address
-@ingroup i2c_defines
-
-@{*/
-#define I2C1 I2C1_BASE
-#define I2C2 I2C2_BASE
-/**@}*/
-
-/* --- I2C registers ------------------------------------------------------- */
-
-/* Control register 1 (I2Cx_CR1) */
-#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
-#define I2C1_CR1 I2C_CR1(I2C1)
-#define I2C2_CR1 I2C_CR1(I2C2)
-
-/* Control register 2 (I2Cx_CR2) */
-#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
-#define I2C1_CR2 I2C_CR2(I2C1)
-#define I2C2_CR2 I2C_CR2(I2C2)
-
-/* Own address register 1 (I2Cx_OAR1) */
-#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
-#define I2C1_OAR1 I2C_OAR1(I2C1)
-#define I2C2_OAR1 I2C_OAR1(I2C2)
-
-/* Own address register 2 (I2Cx_OAR2) */
-#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
-#define I2C1_OAR2 I2C_OAR2(I2C1)
-#define I2C2_OAR2 I2C_OAR2(I2C2)
-
-/* Data register (I2Cx_DR) */
-#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
-#define I2C1_DR I2C_DR(I2C1)
-#define I2C2_DR I2C_DR(I2C2)
-
-/* Status register 1 (I2Cx_SR1) */
-#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
-#define I2C1_SR1 I2C_SR1(I2C1)
-#define I2C2_SR1 I2C_SR1(I2C2)
-
-/* Status register 2 (I2Cx_SR2) */
-#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
-#define I2C1_SR2 I2C_SR2(I2C1)
-#define I2C2_SR2 I2C_SR2(I2C2)
-
-/* Clock control register (I2Cx_CCR) */
-#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
-#define I2C1_CCR I2C_CCR(I2C1)
-#define I2C2_CCR I2C_CCR(I2C2)
-
-/* TRISE register (I2Cx_CCR) */
-#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
-#define I2C1_TRISE I2C_TRISE(I2C1)
-#define I2C2_TRISE I2C_TRISE(I2C2)
-
-/* --- I2Cx_CR1 values ----------------------------------------------------- */
-
-/* SWRST: Software reset */
-#define I2C_CR1_SWRST (1 << 15)
-
-/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
-
-/* ALERT: SMBus alert */
-#define I2C_CR1_ALERT (1 << 13)
-
-/* PEC: Packet error checking */
-#define I2C_CR1_PEC (1 << 12)
-
-/* POS: Acknowledge / PEC postition */
-#define I2C_CR1_POS (1 << 11)
-
-/* ACK: Acknowledge enable */
-#define I2C_CR1_ACK (1 << 10)
-
-/* STOP: STOP generation */
-#define I2C_CR1_STOP (1 << 9)
-
-/* START: START generation */
-#define I2C_CR1_START (1 << 8)
-
-/* NOSTRETCH: Clock stretching disable (slave mode) */
-#define I2C_CR1_NOSTRETCH (1 << 7)
-
-/* ENGC: General call enable */
-#define I2C_CR1_ENGC (1 << 6)
-
-/* ENPEC: Enable PEC */
-#define I2C_CR1_ENPEC (1 << 5)
-
-/* ENARP: ARP enable */
-#define I2C_CR1_ENARP (1 << 4)
-
-/* SMBTYPE: SMBus type */
-#define I2C_CR1_SMBTYPE (1 << 3)
-
-/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
-
-/* SMBUS: SMBus mode */
-#define I2C_CR1_SMBUS (1 << 1)
-
-/* PE: Peripheral enable */
-#define I2C_CR1_PE (1 << 0)
-
-/* --- I2Cx_CR2 values ----------------------------------------------------- */
-
-/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
-
-/* LAST: DMA last transfer */
-#define I2C_CR2_LAST (1 << 12)
-
-/* DMAEN: DMA requests enable */
-#define I2C_CR2_DMAEN (1 << 11)
-
-/* ITBUFEN: Buffer interrupt enable */
-#define I2C_CR2_ITBUFEN (1 << 10)
-
-/* ITEVTEN: Event interrupt enable */
-#define I2C_CR2_ITEVTEN (1 << 9)
-
-/* ITERREN: Error interrupt enable */
-#define I2C_CR2_ITERREN (1 << 8)
-
-/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
-
-/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
-/****************************************************************************/
-/** @defgroup i2c_clock I2C clock frequency settings
-@ingroup i2c_defines
-
-@{*/
-#define I2C_CR2_FREQ_2MHZ 0x02
-#define I2C_CR2_FREQ_3MHZ 0x03
-#define I2C_CR2_FREQ_4MHZ 0x04
-#define I2C_CR2_FREQ_5MHZ 0x05
-#define I2C_CR2_FREQ_6MHZ 0x06
-#define I2C_CR2_FREQ_7MHZ 0x07
-#define I2C_CR2_FREQ_8MHZ 0x08
-#define I2C_CR2_FREQ_9MHZ 0x09
-#define I2C_CR2_FREQ_10MHZ 0x0a
-#define I2C_CR2_FREQ_11MHZ 0x0b
-#define I2C_CR2_FREQ_12MHZ 0x0c
-#define I2C_CR2_FREQ_13MHZ 0x0d
-#define I2C_CR2_FREQ_14MHZ 0x0e
-#define I2C_CR2_FREQ_15MHZ 0x0f
-#define I2C_CR2_FREQ_16MHZ 0x10
-#define I2C_CR2_FREQ_17MHZ 0x11
-#define I2C_CR2_FREQ_18MHZ 0x12
-#define I2C_CR2_FREQ_19MHZ 0x13
-#define I2C_CR2_FREQ_20MHZ 0x14
-#define I2C_CR2_FREQ_21MHZ 0x15
-#define I2C_CR2_FREQ_22MHZ 0x16
-#define I2C_CR2_FREQ_23MHZ 0x17
-#define I2C_CR2_FREQ_24MHZ 0x18
-#define I2C_CR2_FREQ_25MHZ 0x19
-#define I2C_CR2_FREQ_26MHZ 0x1a
-#define I2C_CR2_FREQ_27MHZ 0x1b
-#define I2C_CR2_FREQ_28MHZ 0x1c
-#define I2C_CR2_FREQ_29MHZ 0x1d
-#define I2C_CR2_FREQ_30MHZ 0x1e
-#define I2C_CR2_FREQ_31MHZ 0x1f
-#define I2C_CR2_FREQ_32MHZ 0x20
-#define I2C_CR2_FREQ_33MHZ 0x21
-#define I2C_CR2_FREQ_34MHZ 0x22
-#define I2C_CR2_FREQ_35MHZ 0x23
-#define I2C_CR2_FREQ_36MHZ 0x24
-/**@}*/
-
-/* --- I2Cx_OAR1 values ---------------------------------------------------- */
-
-/* ADDMODE: Addressing mode (slave mode) */
-#define I2C_OAR1_ADDMODE (1 << 15)
-#define I2C_OAR1_ADDMODE_7BIT 0
-#define I2C_OAR1_ADDMODE_10BIT 1
-
-/* Note: Bit 14 should always be kept at 1 by software! */
-
-/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
-
-/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
-
-/* --- I2Cx_OAR2 values ---------------------------------------------------- */
-
-/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
-
-/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
-
-/* ENDUAL: Dual addressing mode enable */
-#define I2C_OAR2_ENDUAL (1 << 0)
-
-/* --- I2Cx_DR values ------------------------------------------------------ */
-
-/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
-
-/* DR[7:0] 8-bit data register */
-
-/* --- I2Cx_SR1 values ----------------------------------------------------- */
-
-/* SMBALERT: SMBus alert */
-#define I2C_SR1_SMBALERT (1 << 15)
-
-/* TIMEOUT: Timeout or Tlow Error */
-#define I2C_SR1_TIMEOUT (1 << 14)
-
-/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
-
-/* PECERR: PEC Error in reception */
-#define I2C_SR1_PECERR (1 << 12)
-
-/* OVR: Overrun/Underrun */
-#define I2C_SR1_OVR (1 << 11)
-
-/* AF: Acknowledge failure */
-#define I2C_SR1_AF (1 << 10)
-
-/* ARLO: Arbitration lost (master mode) */
-#define I2C_SR1_ARLO (1 << 9)
-
-/* BERR: Bus error */
-#define I2C_SR1_BERR (1 << 8)
-
-/* TxE: Data register empty (transmitters) */
-#define I2C_SR1_TxE (1 << 7)
-
-/* RxNE: Data register not empty (receivers) */
-#define I2C_SR1_RxNE (1 << 6)
-
-/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
-
-/* STOPF: STOP detection (slave mode) */
-#define I2C_SR1_STOPF (1 << 4)
-
-/* ADD10: 10-bit header sent (master mode) */
-#define I2C_SR1_ADD10 (1 << 3)
-
-/* BTF: Byte transfer finished */
-#define I2C_SR1_BTF (1 << 2)
-
-/* ADDR: Address sent (master mode) / address matched (slave mode) */
-#define I2C_SR1_ADDR (1 << 1)
-
-/* SB: Start bit (master mode) */
-#define I2C_SR1_SB (1 << 0)
-
-/* --- I2Cx_SR2 values ----------------------------------------------------- */
-
-/* Bits [15:8]: PEC[7:0]: Packet error checking register */
-
-/* DUALF: Dual flag (slave mode) */
-#define I2C_SR2_DUALF (1 << 7)
-
-/* SMBHOST: SMBus host header (slave mode) */
-#define I2C_SR2_SMBHOST (1 << 6)
-
-/* SMBDEFAULT: SMBus device default address (slave mode) */
-#define I2C_SR2_SMBDEFAULT (1 << 5)
-
-/* GENCALL: General call address (slave mode) */
-#define I2C_SR2_GENCALL (1 << 4)
-
-/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
-
-/* TRA: Transmitter / receiver */
-#define I2C_SR2_TRA (1 << 2)
-
-/* BUSY: Bus busy */
-#define I2C_SR2_BUSY (1 << 1)
-
-/* MSL: Master / slave */
-#define I2C_SR2_MSL (1 << 0)
-
-/* --- I2Cx_CCR values ----------------------------------------------------- */
-
-/* F/S: I2C Master mode selection (fast / standard) */
-#define I2C_CCR_FS (1 << 15)
-
-/* DUTY: Fast Mode Duty Cycle */
-/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
-@ingroup i2c_defines
-
-@{*/
-#define I2C_CCR_DUTY (1 << 14)
-#define I2C_CCR_DUTY_DIV2 0
-#define I2C_CCR_DUTY_16_DIV_9 1
-/**@}*/
-
-/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
-
-/*
- * Bits [11:0]:
- * CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
- */
-
-/* --- I2Cx_TRISE values --------------------------------------------------- */
-
-/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
-
-/*
- * Bits [5:0]:
- * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
- */
-
-/* --- I2C const definitions ----------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup i2c_rw I2C Read/Write bit
-@ingroup i2c_defines
-
-@{*/
-#define I2C_WRITE 0
-#define I2C_READ 1
-/**@}*/
-
-/* --- I2C funtion prototypes----------------------------------------------- */
-
-BEGIN_DECLS
-
-void i2c_reset(u32 i2c);
-void i2c_peripheral_enable(u32 i2c);
-void i2c_peripheral_disable(u32 i2c);
-void i2c_send_start(u32 i2c);
-void i2c_send_stop(u32 i2c);
-void i2c_clear_stop(u32 i2c);
-void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
-void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
-void i2c_set_fast_mode(u32 i2c);
-void i2c_set_standard_mode(u32 i2c);
-void i2c_set_clock_frequency(u32 i2c, u8 freq);
-void i2c_set_ccr(u32 i2c, u16 freq);
-void i2c_set_trise(u32 i2c, u16 trise);
-void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
-void i2c_send_data(u32 i2c, u8 data);
-uint8_t i2c_get_data(u32 i2c);
-void i2c_enable_interrupt(u32 i2c, u32 interrupt);
-void i2c_disable_interrupt(u32 i2c, u32 interrupt);
-void i2c_enable_ack(u32 i2c);
-void i2c_disable_ack(u32 i2c);
-void i2c_nack_next(u32 i2c);
-void i2c_nack_current(u32 i2c);
-void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
-void i2c_enable_dma(u32 i2c);
-void i2c_disable_dma(u32 i2c);
-void i2c_set_dma_last_transfer(u32 i2c);
-void i2c_clear_dma_last_transfer(u32 i2c);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/i2c.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/i2c.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/i2c.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/i2c.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h
index 4e44907..60bbd9e 100644
--- a/include/libopencm3/stm32/iwdg.h
+++ b/include/libopencm3/stm32/iwdg.h
@@ -1,22 +1,8 @@
-/** @defgroup STM32F_iwdg_defines IWDG Defines
+/* This provides unification of code over STM32F subfamilies */
-@brief <b>libopencm3 Defined Constants and Types for the STM32F Independent Watchdog Timer</b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
- */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -31,91 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_IWDG_H
-#define LIBOPENCM3_IWDG_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- IWDG registers ------------------------------------------------------ */
-
-/* Key Register (IWDG_KR) */
-#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
-
-/* Prescaler register (IWDG_PR) */
-#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
-
-/* Reload register (IWDG_RLR) */
-#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
-
-/* Status register (IWDG_SR) */
-#define IWDG_SR MMIO32(IWDG_BASE + 0x0c)
-
-/* --- IWDG_KR values ------------------------------------------------------ */
-
-/* Bits [31:16]: Reserved. */
-
-/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
-/** @defgroup iwdg_key IWDG Key Values
-@ingroup STM32F_iwdg_defines
-
-@{*/
-#define IWDG_KR_RESET 0xaaaa
-#define IWDG_KR_UNLOCK 0x5555
-#define IWDG_KR_START 0xcccc
-/**@}*/
-
-/* --- IWDG_PR values ------------------------------------------------------ */
-
-/* Bits [31:3]: Reserved. */
-
-/* PR[2:0]: Prescaler divider */
-#define IWDG_PR_LSB 0
-/** @defgroup iwdg_prediv IWDG Prescaler divider
-@ingroup STM32F_iwdg_defines
-
-@{*/
-#define IWDG_PR_DIV4 0x0
-#define IWDG_PR_DIV8 0x1
-#define IWDG_PR_DIV16 0x2
-#define IWDG_PR_DIV32 0x3
-#define IWDG_PR_DIV64 0x4
-#define IWDG_PR_DIV128 0x5
-#define IWDG_PR_DIV256 0x6
-/**@}*/
-/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
-/* #define IWDG_PR_DIV256 0x7 */
-
-/* --- IWDG_RLR values ----------------------------------------------------- */
-
-/* Bits [31:12]: Reserved. */
-
-/* RL[11:0]: Watchdog counter reload value */
-
-/* --- IWDG_SR values ------------------------------------------------------ */
-
-/* Bits [31:2]: Reserved. */
-
-/* RVU: Watchdog counter reload value update */
-#define IWDG_SR_RVU (1 << 1)
-
-/* PVU: Watchdog prescaler value update */
-#define IWDG_SR_PVU (1 << 0)
-
-/* --- IWDG function prototypes---------------------------------------------- */
-
-BEGIN_DECLS
-
-void iwdg_start(void);
-void iwdg_set_period_ms(u32 period);
-bool iwdg_reload_busy(void);
-bool iwdg_prescaler_busy(void);
-void iwdg_reset(void);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/iwdg.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/iwdg.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/iwdg.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/iwdg.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/include/libopencm3/stm32/l1/crc.h b/include/libopencm3/stm32/l1/crc.h
new file mode 100644
index 0000000..07370f2
--- /dev/null
+++ b/include/libopencm3/stm32/l1/crc.h
@@ -0,0 +1,40 @@
+/** @defgroup crc_defines CRC Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator </b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+#endif
diff --git a/include/libopencm3/stm32/l1/dac.h b/include/libopencm3/stm32/l1/dac.h
new file mode 100644
index 0000000..7f7ea52
--- /dev/null
+++ b/include/libopencm3/stm32/l1/dac.h
@@ -0,0 +1,40 @@
+/** @defgroup dac_defines DAC Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx DAC</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/i2c.h b/include/libopencm3/stm32/l1/i2c.h
new file mode 100644
index 0000000..1fd419d
--- /dev/null
+++ b/include/libopencm3/stm32/l1/i2c.h
@@ -0,0 +1,41 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx I2C </b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 12 October 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/iwdg.h b/include/libopencm3/stm32/l1/iwdg.h
new file mode 100644
index 0000000..8ba6c44
--- /dev/null
+++ b/include/libopencm3/stm32/l1/iwdg.h
@@ -0,0 +1,41 @@
+/** @defgroup iwdg_defines IWDG Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx Independent Watchdog Timer</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
index 950dd18..d89dbd6 100644
--- a/include/libopencm3/stm32/l1/memorymap.h
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -105,4 +105,9 @@
#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
+/* Make the map names match those for other families to allow commonality */
+#define SPI1_I2S_BASE SPI1_BASE
+#define SPI2_I2S_BASE SPI2_BASE
+#define SPI3_I2S_BASE SPI3_BASE
+
#endif
diff --git a/include/libopencm3/stm32/l1/spi.h b/include/libopencm3/stm32/l1/spi.h
new file mode 100644
index 0000000..0484956
--- /dev/null
+++ b/include/libopencm3/stm32/l1/spi.h
@@ -0,0 +1,40 @@
+/** @defgroup spi_defines SPI Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx SPI</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/l1/usart.h b/include/libopencm3/stm32/l1/usart.h
new file mode 100644
index 0000000..5b67a5a
--- /dev/null
+++ b/include/libopencm3/stm32/l1/usart.h
@@ -0,0 +1,40 @@
+/** @defgroup usart_defines USART Defines
+
+@brief <b>Defined Constants and Types for the STM32L1xx USART</b>
+
+@ingroup STM32L1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
+
+@date 5 December 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
new file mode 100644
index 0000000..2f2c9f3
--- /dev/null
+++ b/include/libopencm3/stm32/rcc.h
@@ -0,0 +1,31 @@
+/* This provides unification of code over STM32F subfamilies */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/rcc.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/rcc.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/rcc.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/rcc.h>
+#else
+# error "stm32 family not defined."
+#endif
+
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index f23df3a..28aadd1 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -1,24 +1,8 @@
-/** @defgroup spi_defines SPI Defines
-
-@ingroup STM32F_defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
-@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
-
-@date 12 October 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -33,380 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef LIBOPENCM3_SPI_H
-#define LIBOPENCM3_SPI_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/**@{*/
-
-/* Registers can be accessed as 16bit or 32bit values. */
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup spi_reg_base SPI Register base address
-@ingroup spi_defines
-
-@{*/
-#define SPI1 SPI1_BASE
-#define SPI2 SPI2_I2S_BASE
-#define SPI3 SPI3_I2S_BASE
-/**@}*/
-
-/* --- SPI registers ------------------------------------------------------- */
-
-/* Control register 1 (SPIx_CR1) */
-/* Note: Not used in I2S mode. */
-#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
-#define SPI1_CR1 SPI_CR1(SPI1_BASE)
-#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
-#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
-
-/* Control register 2 (SPIx_CR2) */
-#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
-#define SPI1_CR2 SPI_CR2(SPI1_BASE)
-#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
-#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
-
-/* Status register (SPIx_SR) */
-#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
-#define SPI1_SR SPI_SR(SPI1_BASE)
-#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
-#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
-
-/* Data register (SPIx_DR) */
-#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
-#define SPI1_DR SPI_DR(SPI1_BASE)
-#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
-#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
-
-/* CRC polynomial register (SPIx_CRCPR) */
-/* Note: Not used in I2S mode. */
-#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
-#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
-#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
-#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
-
-/* RX CRC register (SPIx_RXCRCR) */
-/* Note: Not used in I2S mode. */
-#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
-#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
-#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
-#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
-
-/* TX CRC register (SPIx_RXCRCR) */
-/* Note: Not used in I2S mode. */
-#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
-#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
-#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
-#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
-
-/* I2S configuration register (SPIx_I2SCFGR) */
-#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
-#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
-#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
-#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
-
-/* I2S prescaler register (SPIx_I2SPR) */
-#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
-#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
-#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
-#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
-
-/* --- SPI_CR1 values ------------------------------------------------------ */
-
-/* Note: None of the CR1 bits are used in I2S mode. */
-
-/* BIDIMODE: Bidirectional data mode enable */
-#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
-#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
-#define SPI_CR1_BIDIMODE (1 << 15)
-
-/* BIDIOE: Output enable in bidirectional mode */
-#define SPI_CR1_BIDIOE (1 << 14)
-
-/* CRCEN: Hardware CRC calculation enable */
-#define SPI_CR1_CRCEN (1 << 13)
-
-/* CRCNEXT: Transmit CRC next */
-#define SPI_CR1_CRCNEXT (1 << 12)
-
-/* DFF: Data frame format */
-/****************************************************************************/
-/** @defgroup spi_dff SPI data frame format
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_DFF_8BIT (0 << 11)
-#define SPI_CR1_DFF_16BIT (1 << 11)
-/**@}*/
-#define SPI_CR1_DFF (1 << 11)
-
-/* RXONLY: Receive only */
-#define SPI_CR1_RXONLY (1 << 10)
-
-/* SSM: Software slave management */
-#define SPI_CR1_SSM (1 << 9)
-
-/* SSI: Internal slave select */
-#define SPI_CR1_SSI (1 << 8)
-
-/* LSBFIRST: Frame format */
-/****************************************************************************/
-/** @defgroup spi_lsbfirst SPI lsb/msb first
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_MSBFIRST (0 << 7)
-#define SPI_CR1_LSBFIRST (1 << 7)
-/**@}*/
-
-/* SPE: SPI enable */
-#define SPI_CR1_SPE (1 << 6)
-
-/* BR[2:0]: Baud rate control */
-/****************************************************************************/
-/** @defgroup spi_baudrate SPI peripheral baud rates
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
-#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
-/**@}*/
-/****************************************************************************/
-/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_BR_FPCLK_DIV_2 0x0
-#define SPI_CR1_BR_FPCLK_DIV_4 0x1
-#define SPI_CR1_BR_FPCLK_DIV_8 0x2
-#define SPI_CR1_BR_FPCLK_DIV_16 0x3
-#define SPI_CR1_BR_FPCLK_DIV_32 0x4
-#define SPI_CR1_BR_FPCLK_DIV_64 0x5
-#define SPI_CR1_BR_FPCLK_DIV_128 0x6
-#define SPI_CR1_BR_FPCLK_DIV_256 0x7
-/**@}*/
-
-/* MSTR: Master selection */
-#define SPI_CR1_MSTR (1 << 2)
-
-/* CPOL: Clock polarity */
-/****************************************************************************/
-/** @defgroup spi_cpol SPI clock polarity
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
-#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
-/**@}*/
-#define SPI_CR1_CPOL (1 << 1)
-
-/* CPHA: Clock phase */
-/****************************************************************************/
-/** @defgroup spi_cpha SPI clock phase
-@ingroup spi_defines
-
-@{*/
-#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
-#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
-/**@}*/
-#define SPI_CR1_CPHA (1 << 0)
-
-/* --- SPI_CR2 values ------------------------------------------------------ */
-
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-/* TXEIE: Tx buffer empty interrupt enable */
-#define SPI_CR2_TXEIE (1 << 7)
-
-/* RXNEIE: Rx buffer not empty interrupt enable */
-#define SPI_CR2_RXNEIE (1 << 6)
-
-/* ERRIE: Error interrupt enable */
-#define SPI_CR2_ERRIE (1 << 5)
-
-/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
-
-/* SSOE: SS output enable */
-/* Note: Not used in I2S mode. */
-#define SPI_CR2_SSOE (1 << 2)
-
-/* TXDMAEN: Tx buffer DMA enable */
-#define SPI_CR2_TXDMAEN (1 << 1)
-
-/* RXDMAEN: Rx buffer DMA enable */
-#define SPI_CR2_RXDMAEN (1 << 0)
-
-/* --- SPI_SR values ------------------------------------------------------- */
-
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-/* BSY: Busy flag */
-#define SPI_SR_BSY (1 << 7)
-
-/* OVR: Overrun flag */
-#define SPI_SR_OVR (1 << 6)
-
-/* MODF: Mode fault */
-/* Note: Not used in I2S mode. */
-#define SPI_SR_MODF (1 << 5)
-
-/* CRCERR: CRC error flag */
-/* Note: Not used in I2S mode. */
-#define SPI_SR_CRCERR (1 << 4)
-
-/* UDR: Underrun flag */
-/* Note: Not used in SPI mode. */
-#define SPI_SR_UDR (1 << 3)
-
-/* CHSIDE: Channel side */
-/* Note: Not used in SPI mode. No meaning in PCM mode. */
-#define SPI_SR_CHSIDE (1 << 2)
-
-/* TXE: Transmit buffer empty */
-#define SPI_SR_TXE (1 << 1)
-
-/* RXNE: Receive buffer not empty */
-#define SPI_SR_RXNE (1 << 0)
-
-/* --- SPI_DR values ------------------------------------------------------- */
-
-/* SPI_DR[15:0]: Data Register. */
-
-/* --- SPI_CRCPR values ---------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
-
-/* --- SPI_RXCRCR values --------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_RXCRCR [15:0]: RX CRC Register. */
-
-/* --- SPI_TXCRCR values --------------------------------------------------- */
-
-/* Note: Not used in I2S mode. */
-/* SPI_TXCRCR [15:0]: TX CRC Register. */
-
-/* --- SPI_I2SCFGR values -------------------------------------------------- */
-
-/* Note: None of these bits are used in SPI mode. */
-
-/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
-
-/* I2SMOD: I2S mode selection */
-#define SPI_I2SCFGR_I2SMOD (1 << 11)
-
-/* I2SE: I2S enable */
-#define SPI_I2SCFGR_I2SE (1 << 10)
-
-/* I2SCFG[9:8]: I2S configuration mode */
-#define SPI_I2SCFGR_I2SCFG_LSB 8
-#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
-#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
-#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
-#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
-
-/* PCMSYNC: PCM frame synchronization */
-#define SPI_I2SCFGR_PCMSYNC (1 << 7)
-
-/* Bit 6: Reserved. Forced to 0 by hardware. */
-
-/* I2SSTD[5:4]: I2S standard selection */
-#define SPI_I2SCFGR_I2SSTD_LSB 4
-#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
-#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
-#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
-#define SPI_I2SCFGR_I2SSTD_PCM 0x3
-
-/* CKPOL: Steady state clock polarity */
-#define SPI_I2SCFGR_CKPOL (1 << 3)
-
-/* DATLEN[2:1]: Data length to be transferred */
-#define SPI_I2SCFGR_DATLEN_LSB 1
-#define SPI_I2SCFGR_DATLEN_16BIT 0x0
-#define SPI_I2SCFGR_DATLEN_24BIT 0x1
-#define SPI_I2SCFGR_DATLEN_32BIT 0x2
-
-/* CHLEN: Channel length */
-#define SPI_I2SCFGR_CHLEN (1 << 0)
-
-/* --- SPI_I2SPR values ---------------------------------------------------- */
-
-/* Note: None of these bits are used in SPI mode. */
-
-/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
-
-/* MCKOE: Master clock output enable */
-#define SPI_I2SPR_MCKOE (1 << 9)
-
-/* ODD: Odd factor for the prescaler */
-#define SPI_I2SPR_ODD (1 << 8)
-
-/* I2SDIV[7:0]: I2S linear prescaler */
-/* 0 and 1 are forbidden values */
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void spi_reset(u32 spi_peripheral);
-int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
-void spi_enable(u32 spi);
-void spi_disable(u32 spi);
-void spi_write(u32 spi, u16 data);
-void spi_send(u32 spi, u16 data);
-u16 spi_read(u32 spi);
-u16 spi_xfer(u32 spi, u16 data);
-void spi_set_bidirectional_mode(u32 spi);
-void spi_set_unidirectional_mode(u32 spi);
-void spi_set_bidirectional_receive_only_mode(u32 spi);
-void spi_set_bidirectional_transmit_only_mode(u32 spi);
-void spi_enable_crc(u32 spi);
-void spi_disable_crc(u32 spi);
-void spi_set_next_tx_from_buffer(u32 spi);
-void spi_set_next_tx_from_crc(u32 spi);
-void spi_set_dff_8bit(u32 spi);
-void spi_set_dff_16bit(u32 spi);
-void spi_set_full_duplex_mode(u32 spi);
-void spi_set_receive_only_mode(u32 spi);
-void spi_disable_software_slave_management(u32 spi);
-void spi_enable_software_slave_management(u32 spi);
-void spi_set_nss_high(u32 spi);
-void spi_set_nss_low(u32 spi);
-void spi_send_lsb_first(u32 spi);
-void spi_send_msb_first(u32 spi);
-void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
-void spi_set_master_mode(u32 spi);
-void spi_set_slave_mode(u32 spi);
-void spi_set_clock_polarity_1(u32 spi);
-void spi_set_clock_polarity_0(u32 spi);
-void spi_set_clock_phase_1(u32 spi);
-void spi_set_clock_phase_0(u32 spi);
-void spi_enable_tx_buffer_empty_interrupt(u32 spi);
-void spi_disable_tx_buffer_empty_interrupt(u32 spi);
-void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
-void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
-void spi_enable_error_interrupt(u32 spi);
-void spi_disable_error_interrupt(u32 spi);
-void spi_enable_ss_output(u32 spi);
-void spi_disable_ss_output(u32 spi);
-void spi_enable_tx_dma(u32 spi);
-void spi_disable_tx_dma(u32 spi);
-void spi_enable_rx_dma(u32 spi);
-void spi_disable_rx_dma(u32 spi);
-
-END_DECLS
-
-/**@}*/
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/spi.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/spi.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/spi.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/spi.h>
+#else
+# error "stm32 family not defined."
#endif
+
diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h
index 9994002..fc6cbcb 100644
--- a/include/libopencm3/stm32/usart.h
+++ b/include/libopencm3/stm32/usart.h
@@ -1,23 +1,8 @@
-/** @defgroup STM32F_usart_defines USART Defines
-
-@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
-
-@ingroup STM32F_defines
-
-@version 1.0.0
-
-@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
-
-@date 1 September 2012
-
-LGPL License Terms @ref lgpl_license
- */
+/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
@@ -32,352 +17,15 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
-/**@{*/
-
-#ifndef LIBOPENCM3_USART_H
-#define LIBOPENCM3_USART_H
-
-#include <libopencm3/stm32/memorymap.h>
-#include <libopencm3/cm3/common.h>
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/****************************************************************************/
-/** @defgroup usart_reg_base USART register base addresses
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART1 USART1_BASE
-#define USART2 USART2_BASE
-#define USART3 USART3_BASE
-/**@}*/
-#define UART4 UART4_BASE
-#define UART5 UART5_BASE
-
-/* --- USART registers ----------------------------------------------------- */
-
-/* Status register (USARTx_SR) */
-#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
-#define USART1_SR USART_SR(USART1_BASE)
-#define USART2_SR USART_SR(USART2_BASE)
-#define USART3_SR USART_SR(USART3_BASE)
-#define UART4_SR USART_SR(UART4_BASE)
-#define UART5_SR USART_SR(UART5_BASE)
-
-/* Data register (USARTx_DR) */
-#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
-#define USART1_DR USART_DR(USART1_BASE)
-#define USART2_DR USART_DR(USART2_BASE)
-#define USART3_DR USART_DR(USART3_BASE)
-#define UART4_DR USART_DR(UART4_BASE)
-#define UART5_DR USART_DR(UART5_BASE)
-
-/* Baud rate register (USARTx_BRR) */
-#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
-#define USART1_BRR USART_BRR(USART1_BASE)
-#define USART2_BRR USART_BRR(USART2_BASE)
-#define USART3_BRR USART_BRR(USART3_BASE)
-#define UART4_BRR USART_BRR(UART4_BASE)
-#define UART5_BRR USART_BRR(UART5_BASE)
-
-/* Control register 1 (USARTx_CR1) */
-#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
-#define USART1_CR1 USART_CR1(USART1_BASE)
-#define USART2_CR1 USART_CR1(USART2_BASE)
-#define USART3_CR1 USART_CR1(USART3_BASE)
-#define UART4_CR1 USART_CR1(UART4_BASE)
-#define UART5_CR1 USART_CR1(UART5_BASE)
-
-/* Control register 2 (USARTx_CR2) */
-#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
-#define USART1_CR2 USART_CR2(USART1_BASE)
-#define USART2_CR2 USART_CR2(USART2_BASE)
-#define USART3_CR2 USART_CR2(USART3_BASE)
-#define UART4_CR2 USART_CR2(UART4_BASE)
-#define UART5_CR2 USART_CR2(UART5_BASE)
-
-/* Control register 3 (USARTx_CR3) */
-#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
-#define USART1_CR3 USART_CR3(USART1_BASE)
-#define USART2_CR3 USART_CR3(USART2_BASE)
-#define USART3_CR3 USART_CR3(USART3_BASE)
-#define UART4_CR3 USART_CR3(UART4_BASE)
-#define UART5_CR3 USART_CR3(UART5_BASE)
-
-/* Guard time and prescaler register (USARTx_GTPR) */
-#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
-#define USART1_GTPR USART_GTPR(USART1_BASE)
-#define USART2_GTPR USART_GTPR(USART2_BASE)
-#define USART3_GTPR USART_GTPR(USART3_BASE)
-#define UART4_GTPR USART_GTPR(UART4_BASE)
-#define UART5_GTPR USART_GTPR(UART5_BASE)
-
-/* --- USART_SR values ----------------------------------------------------- */
-/****************************************************************************/
-/** @defgroup usart_sr_flags USART Status register Flags
-@ingroup STM32F_usart_defines
-
-@{*/
-
-/** CTS: CTS flag */
-/** @note: undefined on UART4 and UART5 */
-#define USART_SR_CTS (1 << 9)
-
-/** LBD: LIN break detection flag */
-#define USART_SR_LBD (1 << 8)
-
-/** TXE: Transmit data buffer empty */
-#define USART_SR_TXE (1 << 7)
-
-/** TC: Transmission complete */
-#define USART_SR_TC (1 << 6)
-
-/** RXNE: Read data register not empty */
-#define USART_SR_RXNE (1 << 5)
-
-/** IDLE: Idle line detected */
-#define USART_SR_IDLE (1 << 4)
-
-/** ORE: Overrun error */
-#define USART_SR_ORE (1 << 3)
-
-/** NE: Noise error flag */
-#define USART_SR_NE (1 << 2)
-
-/** FE: Framing error */
-#define USART_SR_FE (1 << 1)
-
-/** PE: Parity error */
-#define USART_SR_PE (1 << 0)
-/**@}*/
-
-/* --- USART_DR values ----------------------------------------------------- */
-
-/* USART_DR[8:0]: DR[8:0]: Data value */
-#define USART_DR_MASK 0x1FF
-
-/* --- USART_BRR values ---------------------------------------------------- */
-
-/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
-#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
-/* DIV_Fraction[3:0]: fraction of USARTDIV */
-#define USART_BRR_DIV_FRACTION_MASK 0xF
-
-/* --- USART_CR1 values ---------------------------------------------------- */
-
-/* UE: USART enable */
-#define USART_CR1_UE (1 << 13)
-
-/* M: Word length */
-#define USART_CR1_M (1 << 12)
-
-/* WAKE: Wakeup method */
-#define USART_CR1_WAKE (1 << 11)
-
-/* PCE: Parity control enable */
-#define USART_CR1_PCE (1 << 10)
-
-/* PS: Parity selection */
-#define USART_CR1_PS (1 << 9)
-
-/* PEIE: PE interrupt enable */
-#define USART_CR1_PEIE (1 << 8)
-
-/* TXEIE: TXE interrupt enable */
-#define USART_CR1_TXEIE (1 << 7)
-
-/* TCIE: Transmission complete interrupt enable */
-#define USART_CR1_TCIE (1 << 6)
-
-/* RXNEIE: RXNE interrupt enable */
-#define USART_CR1_RXNEIE (1 << 5)
-
-/* IDLEIE: IDLE interrupt enable */
-#define USART_CR1_IDLEIE (1 << 4)
-
-/* TE: Transmitter enable */
-#define USART_CR1_TE (1 << 3)
-
-/* RE: Receiver enable */
-#define USART_CR1_RE (1 << 2)
-
-/* RWU: Receiver wakeup */
-#define USART_CR1_RWU (1 << 1)
-
-/* SBK: Send break */
-#define USART_CR1_SBK (1 << 0)
-
-/* --- USART_CR2 values ---------------------------------------------------- */
-
-/* LINEN: LIN mode enable */
-#define USART_CR2_LINEN (1 << 14)
-
-/* STOP[13:12]: STOP bits */
-#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
-#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
-#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
-#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
-#define USART_CR2_STOPBITS_MASK (0x03 << 12)
-#define USART_CR2_STOPBITS_SHIFT 12
-
-/* CLKEN: Clock enable */
-#define USART_CR2_CLKEN (1 << 11)
-
-/* CPOL: Clock polarity */
-#define USART_CR2_CPOL (1 << 10)
-
-/* CPHA: Clock phase */
-#define USART_CR2_CPHA (1 << 9)
-
-/* LBCL: Last bit clock pulse */
-#define USART_CR2_LBCL (1 << 8)
-
-/* LBDIE: LIN break detection interrupt enable */
-#define USART_CR2_LBDIE (1 << 6)
-
-/* LBDL: LIN break detection length */
-#define USART_CR2_LBDL (1 << 5)
-
-/* ADD[3:0]: Addres of the usart node */
-#define USART_CR2_ADD_MASK 0xF
-
-/* --- USART_CR3 values ---------------------------------------------------- */
-
-/* CTSIE: CTS interrupt enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_CTSIE (1 << 10)
-
-/* CTSE: CTS enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_CTSE (1 << 9)
-
-/* RTSE: RTS enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_RTSE (1 << 8)
-
-/* DMAT: DMA enable transmitter */
-/* Note: N/A on UART5 */
-#define USART_CR3_DMAT (1 << 7)
-
-/* DMAR: DMA enable receiver */
-/* Note: N/A on UART5 */
-#define USART_CR3_DMAR (1 << 6)
-
-/* SCEN: Smartcard mode enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_SCEN (1 << 5)
-
-/* NACK: Smartcard NACK enable */
-/* Note: N/A on UART4 & UART5 */
-#define USART_CR3_NACK (1 << 4)
-
-/* HDSEL: Half-duplex selection */
-#define USART_CR3_HDSEL (1 << 3)
-
-/* IRLP: IrDA low-power */
-#define USART_CR3_IRLP (1 << 2)
-
-/* IREN: IrDA mode enable */
-#define USART_CR3_IREN (1 << 1)
-
-/* EIE: Error interrupt enable */
-#define USART_CR3_EIE (1 << 0)
-
-/* --- USART_GTPR values --------------------------------------------------- */
-
-/* GT[7:0]: Guard time value */
-/* Note: N/A on UART4 & UART5 */
-#define USART_GTPR_GT_MASK (0xFF << 8)
-
-/* PSC[7:0]: Prescaler value */
-/* Note: N/A on UART4/5 */
-#define USART_GTPR_PSC_MASK 0xFF
-
-/* TODO */ /* Note to Uwe: what needs to be done here? */
-
-/* --- Convenience defines ------------------------------------------------- */
-
-/* CR1_PCE / CR1_PS combined values */
-/****************************************************************************/
-/** @defgroup usart_cr1_parity USART Parity Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_PARITY_NONE 0x00
-#define USART_PARITY_EVEN USART_CR1_PCE
-#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
-/**@}*/
-#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
-
-/* CR1_TE/CR1_RE combined values */
-/****************************************************************************/
-/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_MODE_RX USART_CR1_RE
-#define USART_MODE_TX USART_CR1_TE
-#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
-/**@}*/
-#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
-
-/****************************************************************************/
-/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
-#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
-#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
-#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
-/**@}*/
-
-/* CR3_CTSE/CR3_RTSE combined values */
-/****************************************************************************/
-/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
-@ingroup STM32F_usart_defines
-
-@{*/
-#define USART_FLOWCONTROL_NONE 0x00
-#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
-#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
-#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
-/**@}*/
-#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
-
-/* --- Function prototypes ------------------------------------------------- */
-
-BEGIN_DECLS
-
-void usart_set_baudrate(u32 usart, u32 baud);
-void usart_set_databits(u32 usart, u32 bits);
-void usart_set_stopbits(u32 usart, u32 stopbits);
-void usart_set_parity(u32 usart, u32 parity);
-void usart_set_mode(u32 usart, u32 mode);
-void usart_set_flow_control(u32 usart, u32 flowcontrol);
-void usart_enable(u32 usart);
-void usart_disable(u32 usart);
-void usart_send(u32 usart, u16 data);
-u16 usart_recv(u32 usart);
-void usart_wait_send_ready(u32 usart);
-void usart_wait_recv_ready(u32 usart);
-void usart_send_blocking(u32 usart, u16 data);
-u16 usart_recv_blocking(u32 usart);
-void usart_enable_rx_dma(u32 usart);
-void usart_disable_rx_dma(u32 usart);
-void usart_enable_tx_dma(u32 usart);
-void usart_disable_tx_dma(u32 usart);
-void usart_enable_rx_interrupt(u32 usart);
-void usart_disable_rx_interrupt(u32 usart);
-void usart_enable_tx_interrupt(u32 usart);
-void usart_disable_tx_interrupt(u32 usart);
-void usart_enable_error_interrupt(u32 usart);
-void usart_disable_error_interrupt(u32 usart);
-bool usart_get_flag(u32 usart, u32 flag);
-bool usart_get_interrupt_source(u32 usart, u32 flag);
-
-END_DECLS
-
+#if defined(STM32F1)
+# include <libopencm3/stm32/f1/usart.h>
+#elif defined(STM32F2)
+# include <libopencm3/stm32/f2/usart.h>
+#elif defined(STM32F4)
+# include <libopencm3/stm32/f4/usart.h>
+#elif defined(STM32L1)
+# include <libopencm3/stm32/l1/usart.h>
+#else
+# error "stm32 family not defined."
#endif
-/**@}*/
diff --git a/lib/stm32/crc.c b/lib/stm32/common/crc_common_all.c
index bd9e8d2..d65d1b7 100644
--- a/lib/stm32/crc.c
+++ b/lib/stm32/common/crc_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup crc_file CRC
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32Fxxx CRC</b>
+/** @addtogroup crc_file
@version 1.0.0
diff --git a/lib/stm32/dac.c b/lib/stm32/common/dac_common_all.c
index 55440bf..a6be233 100644
--- a/lib/stm32/dac.c
+++ b/lib/stm32/common/dac_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup STM32F_dac_file DAC
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32Fxx Digital to Analog Converter</b>
+/** @addtogroup dac_file
@version 1.0.0
diff --git a/lib/stm32/i2c.c b/lib/stm32/common/i2c_common_all.c
index a67bece..28ae199 100644
--- a/lib/stm32/i2c.c
+++ b/lib/stm32/common/i2c_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup i2c_file I2C
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32Fxxx I2C</b>
+/** @addtogroup i2c_file
@version 1.0.0
@@ -43,7 +39,7 @@ LGPL License Terms @ref lgpl_license
*/
#include <libopencm3/stm32/i2c.h>
-#include <libopencm3/stm32/f4/rcc.h>
+#include <libopencm3/stm32/rcc.h>
/**@{*/
diff --git a/lib/stm32/iwdg.c b/lib/stm32/common/iwdg_common_all.c
index 251bec1..d3d9364 100644
--- a/lib/stm32/iwdg.c
+++ b/lib/stm32/common/iwdg_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup STM32F_iwdg_file IWDG
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>
+/** @addtogroup iwdg_file
@version 1.0.0
diff --git a/lib/stm32/spi.c b/lib/stm32/common/spi_common_all.c
index 90675b3..2e6473d 100644
--- a/lib/stm32/spi.c
+++ b/lib/stm32/common/spi_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup spi_file SPI
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32Fxxx SPI</b>
+/** @addtogroup spi_file
@version 1.0.0
@@ -58,15 +54,7 @@ LGPL License Terms @ref lgpl_license
*/
#include <libopencm3/stm32/spi.h>
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/rcc.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/rcc.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/rcc.h>
-#else
-# error "stm32 family not defined."
-#endif
+#include <libopencm3/stm32/rcc.h>
/*
* SPI and I2S code.
@@ -103,10 +91,12 @@ void spi_reset(u32 spi_peripheral)
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST);
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST);
break;
+#if defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
case SPI3:
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST);
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST);
break;
+#endif
}
}
diff --git a/lib/stm32/usart.c b/lib/stm32/common/usart_common_all.c
index cb46db8..0c3d302 100644
--- a/lib/stm32/usart.c
+++ b/lib/stm32/common/usart_common_all.c
@@ -1,8 +1,4 @@
-/** @defgroup STM32F1xx_usart_file USART
-
-@ingroup STM32F_files
-
-@brief <b>libopencm3 STM32F USART</b>
+/** @addtogroup usart_file
@version 1.0.0
@@ -39,18 +35,7 @@ LGPL License Terms @ref lgpl_license
/**@{*/
#include <libopencm3/stm32/usart.h>
-
-#if defined(STM32F1)
-# include <libopencm3/stm32/f1/rcc.h>
-#elif defined(STM32F2)
-# include <libopencm3/stm32/f2/rcc.h>
-#elif defined(STM32F4)
-# include <libopencm3/stm32/f4/rcc.h>
-#elif defined(STM32L1)
-# include <libopencm3/stm32/l1/rcc.h>
-#else
-# error "stm32 family not defined."
-#endif
+#include <libopencm3/stm32/rcc.h>
/*-----------------------------------------------------------------------------*/
/** @brief USART Set Baudrate.
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index b236c72..6bc21f7 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -28,12 +28,13 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F1
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \
- rtc.o i2c.o dma.o exti.o ethernet.o \
+OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
- timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \
+ timer.o usb_f107.o desig.o pwr.o \
usb_fx07_common.o \
- gpio_common_all.o dma_common_f13.o
+ gpio_common_all.o dma_common_f13.o spi_common_all.o \
+ dac_common_all.o usart_common_all.o iwdg_common_all.o \
+ i2c_common_all.o crc_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f1/crc.c b/lib/stm32/f1/crc.c
new file mode 100644
index 0000000..505fb79
--- /dev/null
+++ b/lib/stm32/f1/crc.c
@@ -0,0 +1,29 @@
+/** @defgroup crc_file CRC
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx CRC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/crc.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+
diff --git a/lib/stm32/f1/dac.c b/lib/stm32/f1/dac.c
new file mode 100644
index 0000000..90dc029
--- /dev/null
+++ b/lib/stm32/f1/dac.c
@@ -0,0 +1,28 @@
+/** @defgroup dac_file DAC
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx DAC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/dac.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
diff --git a/lib/stm32/f1/i2c.c b/lib/stm32/f1/i2c.c
new file mode 100644
index 0000000..2d86bf3
--- /dev/null
+++ b/lib/stm32/f1/i2c.c
@@ -0,0 +1,28 @@
+/** @defgroup i2c_file I2C
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx I2C</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>
+#include <libopencm3/stm32/common/i2c_common_all.h>
+
diff --git a/lib/stm32/f1/iwdg.c b/lib/stm32/f1/iwdg.c
new file mode 100644
index 0000000..85cf18c
--- /dev/null
+++ b/lib/stm32/f1/iwdg.c
@@ -0,0 +1,28 @@
+/** @defgroup iwdg_file IWDG
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/iwdg.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
diff --git a/lib/stm32/f1/spi.c b/lib/stm32/f1/spi.c
new file mode 100644
index 0000000..3be5c23
--- /dev/null
+++ b/lib/stm32/f1/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/f1/usart.c b/lib/stm32/f1/usart.c
new file mode 100644
index 0000000..ecf2b06
--- /dev/null
+++ b/lib/stm32/f1/usart.c
@@ -0,0 +1,28 @@
+/** @defgroup usart_file USART
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx USART</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index c6a274d..3d3c756 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -28,9 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F2
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o spi.o flash.o \
- i2c.o exti2.o timer.o \
- gpio_common_all.o gpio_common_f24.o dma_common_f24.o
+OBJS = rcc.o gpio.o flash.o exti2.o timer.o \
+ gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
+ dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
+ crc_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f2/crc.c b/lib/stm32/f2/crc.c
new file mode 100644
index 0000000..5437f7c
--- /dev/null
+++ b/lib/stm32/f2/crc.c
@@ -0,0 +1,29 @@
+/** @defgroup crc_file CRC
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx CRC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/crc.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+
diff --git a/lib/stm32/f2/dac.c b/lib/stm32/f2/dac.c
new file mode 100644
index 0000000..5d20703
--- /dev/null
+++ b/lib/stm32/f2/dac.c
@@ -0,0 +1,28 @@
+/** @defgroup dac_file DAC
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx DAC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/dac.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
diff --git a/lib/stm32/f2/i2c.c b/lib/stm32/f2/i2c.c
new file mode 100644
index 0000000..f20a840
--- /dev/null
+++ b/lib/stm32/f2/i2c.c
@@ -0,0 +1,28 @@
+/** @defgroup i2c_file I2C
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx I2C</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/f2/iwdg.c b/lib/stm32/f2/iwdg.c
new file mode 100644
index 0000000..0440d88
--- /dev/null
+++ b/lib/stm32/f2/iwdg.c
@@ -0,0 +1,28 @@
+/** @defgroup iwdg_file IWDG
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx Independent Watchdog Timer</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/iwdg.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
diff --git a/lib/stm32/f2/spi.c b/lib/stm32/f2/spi.c
new file mode 100644
index 0000000..bc4a4ee
--- /dev/null
+++ b/lib/stm32/f2/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
+
diff --git a/lib/stm32/f2/usart.c b/lib/stm32/f2/usart.c
new file mode 100644
index 0000000..225b706
--- /dev/null
+++ b/lib/stm32/f2/usart.c
@@ -0,0 +1,28 @@
+/** @defgroup usart_file USART
+
+@ingroup STM32F2xx
+
+@brief <b>libopencm3 STM32F2xx USART</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index a73dbae..2b02281 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -29,11 +29,12 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32F4
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o usart.o spi.o flash.o \
- i2c.o exti2.o pwr.o timer.o \
+OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
usb_f207.o adc.o dma.o \
- gpio_common_all.o gpio_common_f24.o dma_common_f24.o
+ gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \
+ dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \
+ crc_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f4/crc.c b/lib/stm32/f4/crc.c
new file mode 100644
index 0000000..90e6782
--- /dev/null
+++ b/lib/stm32/f4/crc.c
@@ -0,0 +1,29 @@
+/** @defgroup crc_file CRC
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx CRC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/crc.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+
diff --git a/lib/stm32/f4/dac.c b/lib/stm32/f4/dac.c
new file mode 100644
index 0000000..4776c41
--- /dev/null
+++ b/lib/stm32/f4/dac.c
@@ -0,0 +1,28 @@
+/** @defgroup dac_file DAC
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx DAC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/dac.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
diff --git a/lib/stm32/f4/i2c.c b/lib/stm32/f4/i2c.c
new file mode 100644
index 0000000..3250faa
--- /dev/null
+++ b/lib/stm32/f4/i2c.c
@@ -0,0 +1,28 @@
+/** @defgroup i2c_file I2C
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx I2C</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/f4/iwdg.c b/lib/stm32/f4/iwdg.c
new file mode 100644
index 0000000..9332fc4
--- /dev/null
+++ b/lib/stm32/f4/iwdg.c
@@ -0,0 +1,28 @@
+/** @defgroup iwdg_file IWDG
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx Independent Watchdog Timer</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/iwdg.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
diff --git a/lib/stm32/f4/spi.c b/lib/stm32/f4/spi.c
new file mode 100644
index 0000000..40f5501
--- /dev/null
+++ b/lib/stm32/f4/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_f24.h>
+
diff --git a/lib/stm32/f4/usart.c b/lib/stm32/f4/usart.c
new file mode 100644
index 0000000..e0f7be8
--- /dev/null
+++ b/lib/stm32/f4/usart.c
@@ -0,0 +1,28 @@
+/** @defgroup usart_file USART
+
+@ingroup STM32F4xx
+
+@brief <b>libopencm3 STM32F4xx USART</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index a3c8856..32c8fd3 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -28,10 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-ffunction-sections -fdata-sections -MD -DSTM32L1
# ARFLAGS = rcsv
ARFLAGS = rcs
-OBJS = rcc.o gpio.o desig.o crc.o usart.o exti2.o
-OBJS += flash.o gpio_common_all.o gpio_common_f24.o
-OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
-OBJS += timer.o
+OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o
+OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o
+OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o
+OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/l1/crc.c b/lib/stm32/l1/crc.c
new file mode 100644
index 0000000..7d51341
--- /dev/null
+++ b/lib/stm32/l1/crc.c
@@ -0,0 +1,29 @@
+/** @defgroup crc_file CRC
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx CRC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/crc.h>
+#include <libopencm3/stm32/common/crc_common_all.h>
+
+
diff --git a/lib/stm32/l1/dac.c b/lib/stm32/l1/dac.c
new file mode 100644
index 0000000..534f9f1
--- /dev/null
+++ b/lib/stm32/l1/dac.c
@@ -0,0 +1,28 @@
+/** @defgroup dac_file DAC
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx DAC</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/dac.h>
+#include <libopencm3/stm32/common/dac_common_all.h>
+
diff --git a/lib/stm32/l1/i2c.c b/lib/stm32/l1/i2c.c
new file mode 100644
index 0000000..7a6fe84
--- /dev/null
+++ b/lib/stm32/l1/i2c.c
@@ -0,0 +1,28 @@
+/** @defgroup i2c_file I2C
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx I2C</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/l1/iwdg.c b/lib/stm32/l1/iwdg.c
new file mode 100644
index 0000000..05ddf04
--- /dev/null
+++ b/lib/stm32/l1/iwdg.c
@@ -0,0 +1,28 @@
+/** @defgroup iwdg_file IWDG
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx Independent Watchdog Timer</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/iwdg.h>
+#include <libopencm3/stm32/common/iwdg_common_all.h>
+
diff --git a/lib/stm32/l1/spi.c b/lib/stm32/l1/spi.c
new file mode 100644
index 0000000..30c44dd
--- /dev/null
+++ b/lib/stm32/l1/spi.c
@@ -0,0 +1,28 @@
+/** @defgroup spi_file SPI
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx SPI</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/spi.h>
+#include <libopencm3/stm32/common/spi_common_all.h>
+
diff --git a/lib/stm32/l1/usart.c b/lib/stm32/l1/usart.c
new file mode 100644
index 0000000..67fd674
--- /dev/null
+++ b/lib/stm32/l1/usart.c
@@ -0,0 +1,28 @@
+/** @defgroup usart_file USART
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx USART</b>
+
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/common/usart_common_all.h>
+