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authorMichael Ossmann2012-05-21 22:38:24 -0600
committerMichael Ossmann2012-05-21 22:38:24 -0600
commitb6d1dc06d1f5bff8eb138514ee097a83c2c0d356 (patch)
tree7bb462ab79cd56f92c39e9494e80b76783d24f75
parent3596075ee0f189f8a95090c4fb5522844255a029 (diff)
started include/lpc43xx with copy of lpc17xx
-rw-r--r--include/libopencm3/lpc43xx/gpio.h138
-rw-r--r--include/libopencm3/lpc43xx/memorymap.h65
2 files changed, 203 insertions, 0 deletions
diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h
new file mode 100644
index 0000000..7b07ac5
--- /dev/null
+++ b/include/libopencm3/lpc43xx/gpio.h
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LPC17XX_GPIO_H
+#define LPC17XX_GPIO_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/lpc17xx/memorymap.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIO0 GPIO_PIO0_BASE
+#define GPIO1 GPIO_PIO1_BASE
+#define GPIO2 GPIO_PIO2_BASE
+#define GPIO3 GPIO_PIO3_BASE
+#define GPIO4 GPIO_PIO4_BASE
+
+/* GPIO number definitions (for convenience) */
+#define GPIOPIN0 (1 << 0)
+#define GPIOPIN1 (1 << 1)
+#define GPIOPIN2 (1 << 2)
+#define GPIOPIN3 (1 << 3)
+#define GPIOPIN4 (1 << 4)
+#define GPIOPIN5 (1 << 5)
+#define GPIOPIN6 (1 << 6)
+#define GPIOPIN7 (1 << 7)
+#define GPIOPIN8 (1 << 8)
+#define GPIOPIN9 (1 << 9)
+#define GPIOPIN10 (1 << 10)
+#define GPIOPIN11 (1 << 11)
+#define GPIOPIN12 (1 << 12)
+#define GPIOPIN13 (1 << 13)
+#define GPIOPIN14 (1 << 14)
+#define GPIOPIN15 (1 << 15)
+#define GPIOPIN16 (1 << 16)
+#define GPIOPIN17 (1 << 17)
+#define GPIOPIN18 (1 << 18)
+#define GPIOPIN19 (1 << 19)
+#define GPIOPIN20 (1 << 20)
+#define GPIOPIN21 (1 << 21)
+#define GPIOPIN22 (1 << 22)
+#define GPIOPIN23 (1 << 23)
+#define GPIOPIN24 (1 << 24)
+#define GPIOPIN25 (1 << 25)
+#define GPIOPIN26 (1 << 26)
+#define GPIOPIN27 (1 << 27)
+#define GPIOPIN28 (1 << 28)
+#define GPIOPIN29 (1 << 29)
+#define GPIOPIN30 (1 << 30)
+#define GPIOPIN31 (1 << 31)
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* GPIO data direction register (GPIOn_DIR) */
+#define GPIO_DIR(port) MMIO32(port + 0x00)
+#define GPIO0_DIR GPIO_DIR(GPIO0)
+#define GPIO1_DIR GPIO_DIR(GPIO1)
+#define GPIO2_DIR GPIO_DIR(GPIO2)
+#define GPIO3_DIR GPIO_DIR(GPIO3)
+#define GPIO4_DIR GPIO_DIR(GPIO4)
+
+/* GPIO fast mask register (GPIOn_DIR) */
+#define GPIO_MASK(port) MMIO32(port + 0x10)
+#define GPIO0_MASK GPIO_MASK(GPIO0)
+#define GPIO1_MASK GPIO_MASK(GPIO1)
+#define GPIO2_MASK GPIO_MASK(GPIO2)
+#define GPIO3_MASK GPIO_MASK(GPIO3)
+#define GPIO4_MASK GPIO_MASK(GPIO4)
+
+/* GPIO port pin value register (GPIOn_PIN) */
+#define GPIO_PIN(port) MMIO32(port + 0x14)
+#define GPIO0_PIN GPIO_PIN(GPIO0)
+#define GPIO1_PIN GPIO_PIN(GPIO1)
+#define GPIO2_PIN GPIO_PIN(GPIO2)
+#define GPIO3_PIN GPIO_PIN(GPIO3)
+#define GPIO4_PIN GPIO_PIN(GPIO4)
+
+/* GPIO port output set register (GPIOn_SET) */
+#define GPIO_SET(port) MMIO32(port + 0x18)
+#define GPIO0_SET GPIO_SET(GPIO0)
+#define GPIO1_SET GPIO_SET(GPIO1)
+#define GPIO2_SET GPIO_SET(GPIO2)
+#define GPIO3_SET GPIO_SET(GPIO3)
+#define GPIO4_SET GPIO_SET(GPIO4)
+
+/* GPIO port output clear register (GPIOn_CLR) */
+#define GPIO_CLR(port) MMIO32(port + 0x1C)
+#define GPIO0_CLR GPIO_CLR(GPIO0)
+#define GPIO1_CLR GPIO_CLR(GPIO1)
+#define GPIO2_CLR GPIO_CLR(GPIO2)
+#define GPIO3_CLR GPIO_CLR(GPIO3)
+#define GPIO4_CLR GPIO_CLR(GPIO4)
+
+/* GPIO interrupt register map */
+/* Interrupt enable rising edge */
+#define GPIO0_IER MMIO32(GPIOINTERRPUT_BASE + 0x90)
+#define GPIO2_IER MMIO32(GPIOINTERRPUT_BASE + 0xB0)
+
+/* Interrupt enable falling edge */
+#define GPIO0_IEF MMIO32(GPIOINTERRPUT_BASE + 0x94)
+#define GPIO2_IEF MMIO32(GPIOINTERRPUT_BASE + 0xB4)
+
+/* Interrupt status rising edge */
+#define GPIO0_ISR MMIO32(GPIOINTERRPUT_BASE + 0x84)
+#define GPIO2_ISR MMIO32(GPIOINTERRPUT_BASE + 0xA4)
+
+/* Interrupt status falling edge */
+#define GPIO0_ISF MMIO32(GPIOINTERRPUT_BASE + 0x88)
+#define GPIO2_ISF MMIO32(GPIOINTERRPUT_BASE + 0xA8)
+
+/* Interrupt clear */
+#define GPIO0_IC MMIO32(GPIOINTERRPUT_BASE + 0x8C)
+#define GPIO1_IC MMIO32(GPIOINTERRPUT_BASE + 0xAC)
+
+/* Overall interrupt status */
+#define GPIO_IS MMIO32(GPIOINTERRPUT_BASE + 0x80)
+
+void gpio_set(u32 gpioport, u32 gpios);
+void gpio_clear(u32 gpioport, u32 gpios);
+
+#endif
diff --git a/include/libopencm3/lpc43xx/memorymap.h b/include/libopencm3/lpc43xx/memorymap.h
new file mode 100644
index 0000000..1114442
--- /dev/null
+++ b/include/libopencm3/lpc43xx/memorymap.h
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LPC17XX_MEMORYMAP_H
+#define LPC17XX_MEMORYMAP_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- LPC17XX specific peripheral definitions ----------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE_APB0 0x40000000
+#define PERIPH_BASE_APB1 0x40080000
+#define PERIPH_BASE_AHB 0x20000000
+
+/* Register boundary addresses */
+
+/* APB0 */
+#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
+#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
+#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
+#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
+#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
+/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
+#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
+#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
+#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
+#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
+#define GPIOINTERRPUT_BASE (PERIPH_BASE_APB0 + 0x28000)
+#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
+#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
+#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
+#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
+#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
+#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
+#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
+#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
+/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
+#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
+/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */
+
+/* AHB */
+#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000)
+#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020)
+#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040)
+#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060)
+#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080)
+
+#endif