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authorTitanMKD2012-06-03 18:57:33 +0200
committerTitanMKD2012-06-03 18:57:33 +0200
commit67a048b5b054f9470d45f7285a622f4dc90aff78 (patch)
treeed0ca0ffb0fed5491ed161eccb539b5adb241a4b
parent646e8f20f1cdefe49142fd626ac7558f7a4ebfea (diff)
Added SCU I2C0 specific configuration.
-rw-r--r--examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c3
-rw-r--r--include/libopencm3/lpc43xx/scu.h74
2 files changed, 77 insertions, 0 deletions
diff --git a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c
index 567d9dc..2826126 100644
--- a/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c
+++ b/examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c
@@ -37,6 +37,9 @@ void gpio_setup(void)
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
+ /* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */
+ SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
+
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h
index 146aafc..324ee57 100644
--- a/include/libopencm3/lpc43xx/scu.h
+++ b/include/libopencm3/lpc43xx/scu.h
@@ -312,6 +312,80 @@
/* Pin interrupt select register for pin interrupts 4 to 7 */
#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04)
+/**************************/
+/* SCU I2C0 Configuration */
+/**************************/
+/* Select input glitch filter time constant for the SCL pin.
+ 0 = 50 ns glitch filter.
+ 1 = 3ns glitch filter.
+ */
+#define SCU_SCL_EFP (BIT0)
+
+/* BIT1 Reserved. Always write a 0 to this bit. */
+
+/* Select I2C mode for the SCL pin.
+ 0 = Standard/Fast mode transmit.
+ 1 = Fast-mode Plus transmit.
+*/
+#define SCU_SCL_EHD (BIT2)
+
+/* Enable the input receiver for the SCL pin.
+Always write a 1 to this bit when using the
+I2C0.
+ 0 = Disabled.
+ 1 = Enabled.
+*/
+#define SCU_SCL_EZI_EN (BIT3)
+
+/* BIT4-6 Reserved. */
+
+/* Enable or disable input glitch filter for the
+SCL pin. The filter time constant is
+determined by bit EFP.
+ 0 = Enable input filter.
+ 1 = Disable input filter.
+*/
+#define SCU_SCL_ZIF_DIS (BIT7)
+
+/* Select input glitch filter time constant for the SDA pin.
+ 0 = 50 ns glitch filter.
+ 1 = 3ns glitch filter.
+ */
+#define SCU_SDA_EFP (BIT8)
+
+/* BIT9 Reserved. Always write a 0 to this bit. */
+
+/* Select I2C mode for the SDA pin.
+ 0 = Standard/Fast mode transmit.
+ 1 = Fast-mode Plus transmit.
+*/
+#define SCU_SDA_EHD (BIT10)
+
+/* Enable the input receiver for the SDA pin.
+Always write a 1 to this bit when using the
+I2C0.
+ 0 = Disabled.
+ 1 = Enabled.
+*/
+#define SCU_SDA_EZI_EN (BIT11)
+
+/* BIT 12-14 - Reserved */
+
+/* Enable or disable input glitch filter for the
+SDA pin. The filter time constant is
+determined by bit SDA_EFP.
+ 0 = Enable input filter.
+ 1 = Disable input filter.
+*/
+#define SCU_SDA_ZIF_DIS (BIT15)
+
+/* Standard mode for I2C SCL/SDA Standard/Fast mode */
+#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)
+
+/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */
+#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \
+ SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)
+
/*
SCU PIN Normal Drive:
The pin configuration registers for normal-drive pins control the following pins: