From 8c877d6dfa5aff2b70ce2c96ef6314bcae7a25c2 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Mon, 17 Jun 2013 15:53:32 +1200 Subject: Fix trailing whitespace everywhere. --- src/lmi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/lmi.c') diff --git a/src/lmi.c b/src/lmi.c index 09a9dd5..cb620c0 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -/* This file implements TI/LMI LM3S target specific functions providing +/* This file implements TI/LMI LM3S target specific functions providing * the XML memory map and Flash memory programming. * * Issues: @@ -35,7 +35,7 @@ #include "target.h" static int lmi_flash_erase(struct target_s *target, uint32_t addr, int len); -static int lmi_flash_write(struct target_s *target, uint32_t dest, +static int lmi_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, int len); static const char lmi_driver_str[] = "LuminaryMicro Stellaris"; @@ -135,7 +135,7 @@ int lmi_flash_erase(struct target_s *target, uint32_t addr, int len) return 0; } -int lmi_flash_write(struct target_s *target, uint32_t dest, +int lmi_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, int len) { uint32_t data[(len>>2)+2]; -- cgit v1.2.3 From 346258934b99c0ea50acfb5ea05fdf0537b3194a Mon Sep 17 00:00:00 2001 From: Fredrik Ahlberg Date: Sun, 23 Nov 2014 22:59:16 +0100 Subject: Added support for TI TM4C123 Launchpad --- src/lmi.c | 20 +- src/platforms/launchpad-icdi/Makefile.inc | 23 ++ src/platforms/launchpad-icdi/platform.c | 86 +++++ src/platforms/launchpad-icdi/platform.h | 137 +++++++ src/platforms/tm4c/cdcacm.c | 577 ++++++++++++++++++++++++++++++ src/platforms/tm4c/gdb_if.c | 100 ++++++ src/platforms/tm4c/jtagtap.c | 58 +++ src/platforms/tm4c/swdptap.c | 125 +++++++ src/platforms/tm4c/tm4c.ld | 29 ++ src/platforms/tm4c/traceswo.c | 165 +++++++++ src/platforms/tm4c/usbuart.c | 182 ++++++++++ 11 files changed, 1501 insertions(+), 1 deletion(-) create mode 100644 src/platforms/launchpad-icdi/Makefile.inc create mode 100644 src/platforms/launchpad-icdi/platform.c create mode 100644 src/platforms/launchpad-icdi/platform.h create mode 100644 src/platforms/tm4c/cdcacm.c create mode 100644 src/platforms/tm4c/gdb_if.c create mode 100644 src/platforms/tm4c/jtagtap.c create mode 100644 src/platforms/tm4c/swdptap.c create mode 100644 src/platforms/tm4c/tm4c.ld create mode 100644 src/platforms/tm4c/traceswo.c create mode 100644 src/platforms/tm4c/usbuart.c (limited to 'src/lmi.c') diff --git a/src/lmi.c b/src/lmi.c index cb620c0..a08819e 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -38,7 +38,7 @@ static int lmi_flash_erase(struct target_s *target, uint32_t addr, int len); static int lmi_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, int len); -static const char lmi_driver_str[] = "LuminaryMicro Stellaris"; +static const char lmi_driver_str[] = "TI Stellaris/Tiva"; static const char lmi_xml_memory_map[] = "" /* "" " " ""; +static const char tm4c123gh6pm_xml_memory_map[] = "" +/* ""*/ + "" + " " + " 0x400" + " " + " " + ""; + uint16_t lmi_flash_write_stub[] = { // _start: @@ -100,6 +111,13 @@ bool lmi_probe(struct target_s *target) target->flash_erase = lmi_flash_erase; target->flash_write = lmi_flash_write; return true; + + case 0x10A1: /* TM4C123GH6PM */ + target->driver = lmi_driver_str; + target->xml_mem_map = tm4c123gh6pm_xml_memory_map; + target->flash_erase = lmi_flash_erase; + target->flash_write = lmi_flash_write; + return true; } return false; } diff --git a/src/platforms/launchpad-icdi/Makefile.inc b/src/platforms/launchpad-icdi/Makefile.inc new file mode 100644 index 0000000..8a0f9a3 --- /dev/null +++ b/src/platforms/launchpad-icdi/Makefile.inc @@ -0,0 +1,23 @@ +CROSS_COMPILE ?= arm-none-eabi- +CC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy + +INCLUDES = -I../libopencm3/include + +CPU_FLAGS = -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard +CFLAGS += $(INCLUDES) $(CPU_FLAGS) -DTARGET_IS_BLIZZARD_RB1 -DLM4F -DPART_TM4C123GH6PM + +LINKER_SCRIPT="platforms/tm4c/tm4c.ld" +LDFLAGS = -nostartfiles -lc $(CPU_FLAGS) -nodefaultlibs -T$(LINKER_SCRIPT) -Wl,--gc-sections \ + -L../libopencm3/lib -lopencm3_lm4f -lnosys -lm -lgcc + +VPATH += platforms/tm4c + +SRC += cdcacm.c \ + usbuart.c \ + traceswo.o + +all: blackmagic.bin + +blackmagic.bin: blackmagic + $(OBJCOPY) -O binary $^ $@ diff --git a/src/platforms/launchpad-icdi/platform.c b/src/platforms/launchpad-icdi/platform.c new file mode 100644 index 0000000..848271e --- /dev/null +++ b/src/platforms/launchpad-icdi/platform.c @@ -0,0 +1,86 @@ +#include "platform.h" +#include "gdb_if.h" +#include "usbuart.h" + +#include +#include +#include +#include + +#define SYSTICKHZ 100 +#define SYSTICKMS (1000 / SYSTICKHZ) + +#define PLL_DIV_80MHZ 5 +#define PLL_DIV_25MHZ 16 + +extern void trace_tick(void); + +jmp_buf fatal_error_jmpbuf; +uint8_t running_status; +volatile uint32_t timeout_counter; + +const char *morse_msg; + +void morse(const char *msg, char repeat) +{ + (void) msg; + (void) repeat; +} + +void sys_tick_handler(void) +{ + if(timeout_counter) + timeout_counter--; + trace_tick(); +} + +int +platform_init(void) +{ + int i; + for(i=0; i<1000000; i++); + + rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLL_DIV_80MHZ); + + // Enable all JTAG ports and set pins to output + periph_clock_enable(RCC_GPIOA); + periph_clock_enable(RCC_GPIOB); + + gpio_enable_ahb_aperture(); + + gpio_mode_setup(TMS_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, TMS_PIN); + gpio_mode_setup(TCK_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, TCK_PIN); + gpio_mode_setup(TDI_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, TDI_PIN); + gpio_mode_setup(TDO_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, TDO_PIN); + gpio_mode_setup(SRST_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SRST_PIN); + gpio_set_output_config(SRST_PORT, GPIO_OTYPE_OD, GPIO_DRIVE_2MA, SRST_PIN); + gpio_set(SRST_PORT, SRST_PIN); + + systick_set_clocksource(STK_CSR_CLKSOURCE_AHB_DIV8); + systick_set_reload(rcc_get_system_clock_frequency() / (SYSTICKHZ * 8)); + + systick_interrupt_enable(); + systick_counter_enable(); + + nvic_enable_irq(NVIC_SYSTICK_IRQ); + nvic_enable_irq(NVIC_UART0_IRQ); + + usbuart_init(); + cdcacm_init(); + + //jtag_scan(NULL); + + return 0; +} + +void platform_delay(uint32_t delay) +{ + timeout_counter = delay * 10; + while(timeout_counter); +} + +const char *platform_target_voltage(void) +{ + return "not supported"; +} + diff --git a/src/platforms/launchpad-icdi/platform.h b/src/platforms/launchpad-icdi/platform.h new file mode 100644 index 0000000..7f5d55f --- /dev/null +++ b/src/platforms/launchpad-icdi/platform.h @@ -0,0 +1,137 @@ +#ifndef __PLATFORM_H +#define __PLATFORM_H + +#include + +#include +#include + +#include +#include + +#include "gdb_packet.h" + +#define CDCACM_PACKET_SIZE 64 +#define BOARD_IDENT "Black Magic Probe (Launchpad ICDI), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" +#define BOARD_IDENT_DFU "Black Magic (Upgrade) for Launchpad, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" +#define DFU_IDENT "Black Magic Firmware Upgrade (Launchpad)" +#define DFU_IFACE_STRING "lolwut" + +extern usbd_device *usbdev; +#define CDCACM_GDB_ENDPOINT 1 +#define CDCACM_UART_ENDPOINT 3 + +extern jmp_buf fatal_error_jmpbuf; +extern uint8_t running_status; +extern const char *morse_msg; +extern volatile uint32_t timeout_counter; + +#define TMS_PORT GPIOA_BASE +#define TMS_PIN GPIO3 + +#define TCK_PORT GPIOA_BASE +#define TCK_PIN GPIO2 + +#define TDI_PORT GPIOA_BASE +#define TDI_PIN GPIO5 + +#define TDO_PORT GPIOA_BASE +#define TDO_PIN GPIO4 + +#define SWO_PORT GPIOD_BASE +#define SWO_PIN GPIO6 + +#define SWDIO_PORT TMS_PORT +#define SWDIO_PIN TMS_PIN + +#define SWCLK_PORT TCK_PORT +#define SWCLK_PIN TCK_PIN + +#define SRST_PORT GPIOA_BASE +#define SRST_PIN GPIO6 + +#define TMS_SET_MODE() { \ + gpio_mode_setup(TMS_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, TMS_PIN); \ + gpio_set_output_config(TMS_PORT, GPIO_OTYPE_PP, GPIO_DRIVE_2MA, TMS_PIN); \ +} + +#define SWDIO_MODE_FLOAT() { \ + gpio_mode_setup(SWDIO_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SWDIO_PIN); \ +} + +#define SWDIO_MODE_DRIVE() { \ + gpio_mode_setup(SWDIO_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, SWDIO_PIN); \ + gpio_set_output_config(SWDIO_PORT, GPIO_OTYPE_PP, GPIO_DRIVE_2MA, SWDIO_PIN); \ +} + +extern usbd_driver lm4f_usb_driver; +#define USB_DRIVER lm4f_usb_driver +#define USB_IRQ NVIC_USB0_IRQ +#define USB_ISR usb0_isr + +#define IRQ_PRI_USB (2 << 4) + +#define USBUART UART0 +#define USBUART_CLK RCC_UART0 +#define USBUART_IRQ NVIC_UART0_IRQ +#define USBUART_ISR uart0_isr +#define UART_PIN_SETUP() do { \ + periph_clock_enable(RCC_GPIOA); \ + __asm__("nop"); __asm__("nop"); __asm__("nop"); \ + gpio_set_af(GPIOA_BASE, 0x1, GPIO0 | GPIO1); \ + gpio_mode_setup(GPIOA_BASE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0); \ + gpio_mode_setup(GPIOA_BASE, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO1); \ + } while (0) + +#define TRACEUART UART2 +#define TRACEUART_CLK RCC_UART2 +#define TRACEUART_IRQ NVIC_UART2_IRQ +#define TRACEUART_ISR uart2_isr + +/* Use newlib provided integer only stdio functions */ +#define sscanf siscanf +#define sprintf siprintf +#define vasprintf vasiprintf + +#define DEBUG(...) + +#define SET_RUN_STATE(state) {running_status = (state);} +#define SET_IDLE_STATE(state) {} +#define SET_ERROR_STATE(state) SET_IDLE_STATE(state) + +#define PLATFORM_SET_FATAL_ERROR_RECOVERY() {setjmp(fatal_error_jmpbuf);} +#define PLATFORM_FATAL_ERROR(error) { \ + if( running_status ) gdb_putpacketz("X1D"); \ + else gdb_putpacketz("EFF"); \ + running_status = 0; \ + target_list_free(); \ + morse("TARGET LOST.", 1); \ + longjmp(fatal_error_jmpbuf, (error)); \ +} + +#define PLATFORM_HAS_TRACESWO + +int platform_init(void); +void morse(const char *msg, char repeat); + +inline static void gpio_set_val(uint32_t port, uint8_t pin, uint8_t val) { + gpio_write(port, pin, val == 0 ? 0 : 0xff); +} + +inline static uint8_t gpio_get(uint32_t port, uint8_t pin) { + return !(gpio_read(port, pin) == 0); +} + +void platform_delay(uint32_t delay); +const char *platform_target_voltage(void); + +/* */ +void cdcacm_init(void); +/* Returns current usb configuration, or 0 if not configured. */ +int cdcacm_get_config(void); +int cdcacm_get_dtr(void); + +#define disconnect_usb() do { usbd_disconnect(usbdev,1); nvic_disable_irq(USB_IRQ);} while(0) +#define setup_vbus_irq() + +#endif diff --git a/src/platforms/tm4c/cdcacm.c b/src/platforms/tm4c/cdcacm.c new file mode 100644 index 0000000..041d85b --- /dev/null +++ b/src/platforms/tm4c/cdcacm.c @@ -0,0 +1,577 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2011 Black Sphere Technologies Ltd. + * Written by Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* This file implements a the USB Communications Device Class - Abstract + * Control Model (CDC-ACM) as defined in CDC PSTN subclass 1.2. + * A Device Firmware Upgrade (DFU 1.1) class interface is provided for + * field firmware upgrade. + * + * The device's unique id is used as the USB serial number string. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platform.h" +#include "gdb_if.h" +#if defined(PLATFORM_HAS_TRACESWO) +#include +#endif +#include + +#define DFU_IF_NO 4 + +usbd_device * usbdev; + +static char *get_dev_unique_id(char *serial_no); + +static int configured; +static int cdcacm_gdb_dtr = 1; + + +static const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0xEF, /* Miscellaneous Device */ + .bDeviceSubClass = 2, /* Common Class */ + .bDeviceProtocol = 1, /* Interface Association */ + .bMaxPacketSize0 = 64, + .idVendor = 0x1D50, + .idProduct = 0x6018, + .bcdDevice = 0x0100, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +/* This notification endpoint isn't implemented. According to CDC spec its + * optional, but its absence causes a NULL pointer dereference in Linux cdc_acm + * driver. */ +static const struct usb_endpoint_descriptor gdb_comm_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x82, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 16, + .bInterval = 255, +}}; + +static const struct usb_endpoint_descriptor gdb_data_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x01, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = CDCACM_PACKET_SIZE, + .bInterval = 1, +}, { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x81, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = CDCACM_PACKET_SIZE, + .bInterval = 1, +}}; + +static const struct { + struct usb_cdc_header_descriptor header; + struct usb_cdc_call_management_descriptor call_mgmt; + struct usb_cdc_acm_descriptor acm; + struct usb_cdc_union_descriptor cdc_union; +} __attribute__((packed)) gdb_cdcacm_functional_descriptors = { + .header = { + .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_HEADER, + .bcdCDC = 0x0110, + }, + .call_mgmt = { + .bFunctionLength = + sizeof(struct usb_cdc_call_management_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, + .bmCapabilities = 0, + .bDataInterface = 1, + }, + .acm = { + .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_ACM, + .bmCapabilities = 2, /* SET_LINE_CODING supported */ + }, + .cdc_union = { + .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_UNION, + .bControlInterface = 0, + .bSubordinateInterface0 = 1, + } +}; + +static const struct usb_interface_descriptor gdb_comm_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 4, + + .endpoint = gdb_comm_endp, + + .extra = &gdb_cdcacm_functional_descriptors, + .extralen = sizeof(gdb_cdcacm_functional_descriptors) +}}; + +static const struct usb_interface_descriptor gdb_data_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = 0, + + .endpoint = gdb_data_endp, +}}; + +static const struct usb_iface_assoc_descriptor gdb_assoc = { + .bLength = USB_DT_INTERFACE_ASSOCIATION_SIZE, + .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, + .bFirstInterface = 0, + .bInterfaceCount = 2, + .bFunctionClass = USB_CLASS_CDC, + .bFunctionSubClass = USB_CDC_SUBCLASS_ACM, + .bFunctionProtocol = USB_CDC_PROTOCOL_AT, + .iFunction = 0, +}; + +/* Serial ACM interface */ +static const struct usb_endpoint_descriptor uart_comm_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x84, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 16, + .bInterval = 255, +}}; + +static const struct usb_endpoint_descriptor uart_data_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x03, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = CDCACM_PACKET_SIZE, + .bInterval = 1, +}, { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x83, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = CDCACM_PACKET_SIZE, + .bInterval = 1, +}}; + +static const struct { + struct usb_cdc_header_descriptor header; + struct usb_cdc_call_management_descriptor call_mgmt; + struct usb_cdc_acm_descriptor acm; + struct usb_cdc_union_descriptor cdc_union; +} __attribute__((packed)) uart_cdcacm_functional_descriptors = { + .header = { + .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_HEADER, + .bcdCDC = 0x0110, + }, + .call_mgmt = { + .bFunctionLength = + sizeof(struct usb_cdc_call_management_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, + .bmCapabilities = 0, + .bDataInterface = 3, + }, + .acm = { + .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_ACM, + .bmCapabilities = 2, /* SET_LINE_CODING supported*/ + }, + .cdc_union = { + .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_UNION, + .bControlInterface = 2, + .bSubordinateInterface0 = 3, + } +}; + +static const struct usb_interface_descriptor uart_comm_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 2, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 5, + + .endpoint = uart_comm_endp, + + .extra = &uart_cdcacm_functional_descriptors, + .extralen = sizeof(uart_cdcacm_functional_descriptors) +}}; + +static const struct usb_interface_descriptor uart_data_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 3, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = 0, + + .endpoint = uart_data_endp, +}}; + +static const struct usb_iface_assoc_descriptor uart_assoc = { + .bLength = USB_DT_INTERFACE_ASSOCIATION_SIZE, + .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, + .bFirstInterface = 2, + .bInterfaceCount = 2, + .bFunctionClass = USB_CLASS_CDC, + .bFunctionSubClass = USB_CDC_SUBCLASS_ACM, + .bFunctionProtocol = USB_CDC_PROTOCOL_AT, + .iFunction = 0, +}; + +const struct usb_dfu_descriptor dfu_function = { + .bLength = sizeof(struct usb_dfu_descriptor), + .bDescriptorType = DFU_FUNCTIONAL, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeout = 255, + .wTransferSize = 1024, + .bcdDFUVersion = 0x011A, +}; + +const struct usb_interface_descriptor dfu_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = DFU_IF_NO, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = 0xFE, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 1, + .iInterface = 6, + + .extra = &dfu_function, + .extralen = sizeof(dfu_function), +}; + +static const struct usb_iface_assoc_descriptor dfu_assoc = { + .bLength = USB_DT_INTERFACE_ASSOCIATION_SIZE, + .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, + .bFirstInterface = 4, + .bInterfaceCount = 1, + .bFunctionClass = 0xFE, + .bFunctionSubClass = 1, + .bFunctionProtocol = 1, + .iFunction = 6, +}; + +#if defined(PLATFORM_HAS_TRACESWO) +static const struct usb_endpoint_descriptor trace_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x85, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 0, +}}; + +const struct usb_interface_descriptor trace_iface = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 5, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = 0xFF, + .bInterfaceSubClass = 0xFF, + .bInterfaceProtocol = 0xFF, + .iInterface = 7, + + .endpoint = trace_endp, +}; + +static const struct usb_iface_assoc_descriptor trace_assoc = { + .bLength = USB_DT_INTERFACE_ASSOCIATION_SIZE, + .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, + .bFirstInterface = 5, + .bInterfaceCount = 1, + .bFunctionClass = 0xFF, + .bFunctionSubClass = 0xFF, + .bFunctionProtocol = 0xFF, + .iFunction = 7, +}; +#endif + +static const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .iface_assoc = &gdb_assoc, + .altsetting = gdb_comm_iface, +}, { + .num_altsetting = 1, + .altsetting = gdb_data_iface, +}, { + .num_altsetting = 1, + .iface_assoc = &uart_assoc, + .altsetting = uart_comm_iface, +}, { + .num_altsetting = 1, + .altsetting = uart_data_iface, +}, { + .num_altsetting = 1, + .iface_assoc = &dfu_assoc, + .altsetting = &dfu_iface, +#if defined(PLATFORM_HAS_TRACESWO) +}, { + .num_altsetting = 1, + .iface_assoc = &trace_assoc, + .altsetting = &trace_iface, +#endif +}}; + +static const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, +#if defined(PLATFORM_HAS_TRACESWO) + .bNumInterfaces = 6, +#else + .bNumInterfaces = 5, +#endif + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0x80, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +char serial_no[9]; + +static const char *usb_strings[] = { + "Black Sphere Technologies", + BOARD_IDENT, + serial_no, + "Black Magic GDB Server", + "Black Magic UART Port", + DFU_IDENT, +#if defined(PLATFORM_HAS_TRACESWO) + "Black Magic Trace Capture", +#endif +}; + +static void dfu_detach_complete(usbd_device *dev, struct usb_setup_data *req) +{ + (void)dev; + (void)req; + + /* Disconnect USB cable */ + disconnect_usb(); + + /* Assert boot-request pin */ + //assert_boot_pin(); + + /* Reset core to enter bootloader */ + scb_reset_core(); +} + +static int cdcacm_control_request(usbd_device *dev, + struct usb_setup_data *req, uint8_t **buf, uint16_t *len, + void (**complete)(usbd_device *dev, struct usb_setup_data *req)) +{ + (void)dev; + (void)complete; + (void)buf; + (void)len; + + switch(req->bRequest) { + case USB_CDC_REQ_SET_CONTROL_LINE_STATE: + /* Ignore if not for GDB interface */ + if(req->wIndex != 0) + return 1; + + cdcacm_gdb_dtr = req->wValue & 1; + + return 1; + case USB_CDC_REQ_SET_LINE_CODING: + if(*len < sizeof(struct usb_cdc_line_coding)) + return 0; + + switch(req->wIndex) { + case 2: + usbuart_set_line_coding((struct usb_cdc_line_coding*)*buf); + case 0: + return 1; /* Ignore on GDB Port */ + default: + return 0; + } + case DFU_GETSTATUS: + if(req->wIndex == DFU_IF_NO) { + (*buf)[0] = DFU_STATUS_OK; + (*buf)[1] = 0; + (*buf)[2] = 0; + (*buf)[3] = 0; + (*buf)[4] = STATE_APP_IDLE; + (*buf)[5] = 0; /* iString not used here */ + *len = 6; + + return 1; + } + case DFU_DETACH: + if(req->wIndex == DFU_IF_NO) { + *complete = dfu_detach_complete; + return 1; + } + return 0; + } + return 0; +} + +int cdcacm_get_config(void) +{ + return configured; +} + +int cdcacm_get_dtr(void) +{ + return cdcacm_gdb_dtr; +} + +static void cdcacm_set_config(usbd_device *dev, uint16_t wValue) +{ + configured = wValue; + + /* GDB interface */ + usbd_ep_setup(dev, 0x01, USB_ENDPOINT_ATTR_BULK, + CDCACM_PACKET_SIZE, gdb_usb_out_cb); + usbd_ep_setup(dev, 0x81, USB_ENDPOINT_ATTR_BULK, + CDCACM_PACKET_SIZE, NULL); + usbd_ep_setup(dev, 0x82, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + + /* Serial interface */ + usbd_ep_setup(dev, 0x03, USB_ENDPOINT_ATTR_BULK, + CDCACM_PACKET_SIZE, usbuart_usb_out_cb); + usbd_ep_setup(dev, 0x83, USB_ENDPOINT_ATTR_BULK, + CDCACM_PACKET_SIZE, usbuart_usb_in_cb); + usbd_ep_setup(dev, 0x84, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + +#if defined(PLATFORM_HAS_TRACESWO) + /* Trace interface */ + usbd_ep_setup(dev, 0x85, USB_ENDPOINT_ATTR_BULK, + 64, trace_buf_drain); +#endif + + usbd_register_control_callback(dev, + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + cdcacm_control_request); + + /* Notify the host that DCD is asserted. + * Allows the use of /dev/tty* devices on *BSD/MacOS + */ + char buf[10]; + struct usb_cdc_notification *notif = (void*)buf; + /* We echo signals back to host as notification */ + notif->bmRequestType = 0xA1; + notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE; + notif->wValue = 0; + notif->wIndex = 0; + notif->wLength = 2; + buf[8] = 3; /* DCD | DSR */ + buf[9] = 0; + usbd_ep_write_packet(dev, 0x82, buf, 10); + notif->wIndex = 2; + usbd_ep_write_packet(dev, 0x84, buf, 10); +} + +/* We need a special large control buffer for this device: */ +uint8_t usbd_control_buffer[256]; + +void cdcacm_init(void) +{ + get_dev_unique_id(serial_no); + + periph_clock_enable(RCC_GPIOD); + __asm__("nop"); __asm__("nop"); __asm__("nop"); + gpio_mode_setup(GPIOD_BASE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4|GPIO5); + + usbdev = usbd_init(&USB_DRIVER, &dev, &config, usb_strings, + sizeof(usb_strings)/sizeof(char *), + usbd_control_buffer, sizeof(usbd_control_buffer)); + + usbd_register_set_config_callback(usbdev, cdcacm_set_config); + + usb_enable_interrupts(USB_INT_RESET|USB_INT_DISCON|USB_INT_RESUME|USB_INT_SUSPEND, + 0xff, 0xff); + nvic_set_priority(USB_IRQ, IRQ_PRI_USB); + nvic_enable_irq(USB_IRQ); + setup_vbus_irq(); +} + +void USB_ISR(void) +{ + usbd_poll(usbdev); +} + +static char *get_dev_unique_id(char *s) +{ + /* FIXME: Store a unique serial number somewhere and retreive here */ + uint32_t unique_id = 1; + int i; + + /* Fetch serial number from chip's unique ID */ + for(i = 0; i < 8; i++) { + s[7-i] = ((unique_id >> (4*i)) & 0xF) + '0'; + } + for(i = 0; i < 8; i++) + if(s[i] > '9') + s[i] += 'A' - '9' - 1; + s[8] = 0; + + return s; +} diff --git a/src/platforms/tm4c/gdb_if.c b/src/platforms/tm4c/gdb_if.c new file mode 100644 index 0000000..b14bbd3 --- /dev/null +++ b/src/platforms/tm4c/gdb_if.c @@ -0,0 +1,100 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2011 Black Sphere Technologies Ltd. + * Written by Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* This file implements a transparent channel over which the GDB Remote + * Serial Debugging protocol is implemented. This implementation for STM32 + * uses the USB CDC-ACM device bulk endpoints to implement the channel. + */ +#include "platform.h" +#include + +#include "gdb_if.h" + +static volatile uint32_t head_out, tail_out; +static volatile uint32_t count_in; +static volatile uint8_t buffer_out[16*CDCACM_PACKET_SIZE]; +static volatile uint8_t buffer_in[CDCACM_PACKET_SIZE]; + +void gdb_if_putchar(unsigned char c, int flush) +{ + buffer_in[count_in++] = c; + if(flush || (count_in == CDCACM_PACKET_SIZE)) { + /* Refuse to send if USB isn't configured, and + * don't bother if nobody's listening */ + if((cdcacm_get_config() != 1) || !cdcacm_get_dtr()) { + count_in = 0; + return; + } + while(usbd_ep_write_packet(usbdev, CDCACM_GDB_ENDPOINT, + (uint8_t *)buffer_in, count_in) <= 0); + count_in = 0; + } +} + +void gdb_usb_out_cb(usbd_device *dev, uint8_t ep) +{ + (void)ep; + static uint8_t buf[CDCACM_PACKET_SIZE]; + + usbd_ep_nak_set(dev, CDCACM_GDB_ENDPOINT, 1); + uint32_t count = usbd_ep_read_packet(dev, CDCACM_GDB_ENDPOINT, + (uint8_t *)buf, CDCACM_PACKET_SIZE); + + + uint32_t idx; + for (idx=0; idx ":"\n<- "); + + /* Don't turnaround if direction not changing */ + if(dir == olddir) return; + olddir = dir; + + if(dir) + SWDIO_MODE_FLOAT(); + gpio_set(SWCLK_PORT, SWCLK_PIN); + gpio_clear(SWCLK_PORT, SWCLK_PIN); + if(!dir) + SWDIO_MODE_DRIVE(); +} + +static uint8_t swdptap_bit_in(void) +{ + uint16_t ret; + + ret = gpio_get(SWDIO_PORT, SWDIO_PIN); + gpio_set(SWCLK_PORT, SWCLK_PIN); + gpio_clear(SWCLK_PORT, SWCLK_PIN); + + DEBUG("%d", ret?1:0); + + return ret != 0; +} + +static void swdptap_bit_out(uint8_t val) +{ + DEBUG("%d", val); + + gpio_set_val(SWDIO_PORT, SWDIO_PIN, val); + gpio_set(SWCLK_PORT, SWCLK_PIN); + gpio_clear(SWCLK_PORT, SWCLK_PIN); +} + +int +swdptap_init(void) +{ + swdptap_reset(); + swdptap_seq_out(0xE79E, 16); /* 0b0111100111100111 */ + swdptap_reset(); + swdptap_seq_out(0, 16); + + return 0; +} + +void +swdptap_reset(void) +{ + swdptap_turnaround(0); + /* 50 clocks with TMS high */ + for(int i = 0; i < 50; i++) swdptap_bit_out(1); +} + +uint32_t +swdptap_seq_in(int ticks) +{ + uint32_t index = 1; + uint32_t ret = 0; + + swdptap_turnaround(1); + + while(ticks--) { + if(swdptap_bit_in()) ret |= index; + index <<= 1; + } + + return ret; +} + +uint8_t +swdptap_seq_in_parity(uint32_t *ret, int ticks) +{ + uint32_t index = 1; + uint8_t parity = 0; + *ret = 0; + + swdptap_turnaround(1); + + while(ticks--) { + if(swdptap_bit_in()) { + *ret |= index; + parity ^= 1; + } + index <<= 1; + } + if(swdptap_bit_in()) parity ^= 1; + + return parity; +} + +void +swdptap_seq_out(uint32_t MS, int ticks) +{ + swdptap_turnaround(0); + + while(ticks--) { + swdptap_bit_out(MS & 1); + MS >>= 1; + } +} + +void +swdptap_seq_out_parity(uint32_t MS, int ticks) +{ + uint8_t parity = 0; + + swdptap_turnaround(0); + + while(ticks--) { + swdptap_bit_out(MS & 1); + parity ^= MS; + MS >>= 1; + } + swdptap_bit_out(parity & 1); +} diff --git a/src/platforms/tm4c/tm4c.ld b/src/platforms/tm4c/tm4c.ld new file mode 100644 index 0000000..8fe93a4 --- /dev/null +++ b/src/platforms/tm4c/tm4c.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the libopenstm32 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* Include the common ld script from libopenstm32. */ +INCLUDE libopencm3_lm4f.ld + diff --git a/src/platforms/tm4c/traceswo.c b/src/platforms/tm4c/traceswo.c new file mode 100644 index 0000000..eb63139 --- /dev/null +++ b/src/platforms/tm4c/traceswo.c @@ -0,0 +1,165 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2012 Black Sphere Technologies Ltd. + * Written by Gareth McMullin + * + * Copyright (C) 2014 Fredrik Ahlberg + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* This file implements capture of the TRACESWO output. + * + * ARM DDI 0403D - ARMv7M Architecture Reference Manual + * ARM DDI 0337I - Cortex-M3 Technical Reference Manual + * ARM DDI 0314H - CoreSight Components Technical Reference Manual + */ + +#include "general.h" + +#include +#include +#include + +#include + +#include + +#include +#include "platform.h" + +void traceswo_init(void) +{ + periph_clock_enable(RCC_GPIOD); + periph_clock_enable(TRACEUART_CLK); + __asm__("nop"); __asm__("nop"); __asm__("nop"); + + gpio_mode_setup(SWO_PORT, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SWO_PIN); + gpio_set_af(SWO_PORT, 1, SWO_PIN); /* U2RX */ + + uart_disable(TRACEUART); + + /* Setup UART parameters. */ + uart_clock_from_sysclk(TRACEUART); + uart_set_baudrate(TRACEUART, 800000); + uart_set_databits(TRACEUART, 8); + uart_set_stopbits(TRACEUART, 1); + uart_set_parity(TRACEUART, UART_PARITY_NONE); + + // Enable FIFO + uart_enable_fifo(TRACEUART); + + // Set FIFO interrupt trigger levels to 4/8 full for RX buffer and + // 7/8 empty (1/8 full) for TX buffer + uart_set_fifo_trigger_levels(TRACEUART, UART_FIFO_RX_TRIG_1_2, UART_FIFO_TX_TRIG_7_8); + + uart_clear_interrupt_flag(TRACEUART, UART_INT_RX | UART_INT_RT); + + /* Enable interrupts */ + uart_enable_interrupts(TRACEUART, UART_INT_RX | UART_INT_RT); + + /* Finally enable the USART. */ + uart_enable(TRACEUART); + + nvic_set_priority(TRACEUART_IRQ, 0); + nvic_enable_irq(TRACEUART_IRQ); + + /* Un-stall USB endpoint */ + usbd_ep_stall_set(usbdev, 0x85, 0); + + gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3); +} + +void traceswo_baud(unsigned int baud) +{ + uart_set_baudrate(TRACEUART, baud); + uart_set_databits(TRACEUART, 8); +} + +#define FIFO_SIZE 256 + +/* RX Fifo buffer */ +static volatile uint8_t buf_rx[FIFO_SIZE]; +/* Fifo in pointer, writes assumed to be atomic, should be only incremented within RX ISR */ +static volatile uint32_t buf_rx_in = 0; +/* Fifo out pointer, writes assumed to be atomic, should be only incremented outside RX ISR */ +static volatile uint32_t buf_rx_out = 0; + +void trace_buf_push(void) +{ + size_t len; + + if (buf_rx_in == buf_rx_out) { + return; + } else if (buf_rx_in > buf_rx_out) { + len = buf_rx_in - buf_rx_out; + } else { + len = FIFO_SIZE - buf_rx_out; + } + + if (len > 64) { + len = 64; + } + + if (usbd_ep_write_packet(usbdev, 0x85, (uint8_t *)&buf_rx[buf_rx_out], len) == len) { + buf_rx_out += len; + buf_rx_out %= FIFO_SIZE; + } +} + +void trace_buf_drain(usbd_device *dev, uint8_t ep) +{ + (void) dev; + (void) ep; + trace_buf_push(); +} + +void trace_tick(void) +{ + trace_buf_push(); +} + +void TRACEUART_ISR(void) +{ + uint32_t flush = uart_is_interrupt_source(TRACEUART, UART_INT_RT); + + while (!uart_is_rx_fifo_empty(TRACEUART)) { + uint32_t c = uart_recv(TRACEUART); + + /* If the next increment of rx_in would put it at the same point + * as rx_out, the FIFO is considered full. + */ + if (((buf_rx_in + 1) % FIFO_SIZE) != buf_rx_out) + { + /* insert into FIFO */ + buf_rx[buf_rx_in++] = c; + + /* wrap out pointer */ + if (buf_rx_in >= FIFO_SIZE) + { + buf_rx_in = 0; + } + } else { + flush = 1; + break; + } + } + + if (flush) { + /* advance fifo out pointer by amount written */ + trace_buf_push(); + } +} + diff --git a/src/platforms/tm4c/usbuart.c b/src/platforms/tm4c/usbuart.c new file mode 100644 index 0000000..bb769f0 --- /dev/null +++ b/src/platforms/tm4c/usbuart.c @@ -0,0 +1,182 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2012 Black Sphere Technologies Ltd. + * Written by Gareth McMullin + * + * Copyright (C) 2014 Fredrik Ahlberg + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define FIFO_SIZE 128 + +/* RX Fifo buffer */ +static uint8_t buf_rx[FIFO_SIZE]; +/* Fifo in pointer, writes assumed to be atomic, should be only incremented within RX ISR */ +static uint8_t buf_rx_in; +/* Fifo out pointer, writes assumed to be atomic, should be only incremented outside RX ISR */ +static uint8_t buf_rx_out; + +void usbuart_init(void) +{ + UART_PIN_SETUP(); + + periph_clock_enable(USBUART_CLK); + __asm__("nop"); __asm__("nop"); __asm__("nop"); + + uart_disable(USBUART); + + /* Setup UART parameters. */ + uart_clock_from_sysclk(USBUART); + uart_set_baudrate(USBUART, 38400); + uart_set_databits(USBUART, 8); + uart_set_stopbits(USBUART, 1); + uart_set_parity(USBUART, UART_PARITY_NONE); + + // Enable FIFO + uart_enable_fifo(USBUART); + + // Set FIFO interrupt trigger levels to 1/8 full for RX buffer and + // 7/8 empty (1/8 full) for TX buffer + uart_set_fifo_trigger_levels(USBUART, UART_FIFO_RX_TRIG_1_8, UART_FIFO_TX_TRIG_7_8); + + uart_clear_interrupt_flag(USBUART, UART_INT_RX | UART_INT_RT); + + /* Enable interrupts */ + uart_enable_interrupts(UART0, UART_INT_RX| UART_INT_RT); + + /* Finally enable the USART. */ + uart_enable(USBUART); + + //nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART); + nvic_enable_irq(USBUART_IRQ); +} + +void usbuart_set_line_coding(struct usb_cdc_line_coding *coding) +{ + uart_set_baudrate(USBUART, coding->dwDTERate); + uart_set_databits(USBUART, coding->bDataBits); + switch(coding->bCharFormat) { + case 0: + case 1: + uart_set_stopbits(USBUART, 1); + break; + case 2: + uart_set_stopbits(USBUART, 2); + break; + } + switch(coding->bParityType) { + case 0: + uart_set_parity(USBUART, UART_PARITY_NONE); + break; + case 1: + uart_set_parity(USBUART, UART_PARITY_ODD); + break; + case 2: + uart_set_parity(USBUART, UART_PARITY_EVEN); + break; + } +} + +void usbuart_usb_out_cb(usbd_device *dev, uint8_t ep) +{ + (void)ep; + + char buf[CDCACM_PACKET_SIZE]; + int len = usbd_ep_read_packet(dev, CDCACM_UART_ENDPOINT, + buf, CDCACM_PACKET_SIZE); + + for(int i = 0; i < len; i++) + uart_send_blocking(USBUART, buf[i]); +} + + +void usbuart_usb_in_cb(usbd_device *dev, uint8_t ep) +{ + (void) dev; + (void) ep; +} + +/* + * Read a character from the UART RX and stuff it in a software FIFO. + * Allowed to read from FIFO out pointer, but not write to it. + * Allowed to write to FIFO in pointer. + */ +void USBUART_ISR(void) +{ + int flush = uart_is_interrupt_source(USBUART, UART_INT_RT); + + while (!uart_is_rx_fifo_empty(USBUART)) { + char c = uart_recv(USBUART); + + /* If the next increment of rx_in would put it at the same point + * as rx_out, the FIFO is considered full. + */ + if (((buf_rx_in + 1) % FIFO_SIZE) != buf_rx_out) + { + /* insert into FIFO */ + buf_rx[buf_rx_in++] = c; + + /* wrap out pointer */ + if (buf_rx_in >= FIFO_SIZE) + { + buf_rx_in = 0; + } + } else { + flush = 1; + } + } + + if (flush) { + /* forcibly empty fifo if no USB endpoint */ + if (cdcacm_get_config() != 1) + { + buf_rx_out = buf_rx_in; + return; + } + + uint8_t packet_buf[CDCACM_PACKET_SIZE]; + uint8_t packet_size = 0; + uint8_t buf_out = buf_rx_out; + + /* copy from uart FIFO into local usb packet buffer */ + while (buf_rx_in != buf_out && packet_size < CDCACM_PACKET_SIZE) + { + packet_buf[packet_size++] = buf_rx[buf_out++]; + + /* wrap out pointer */ + if (buf_out >= FIFO_SIZE) + { + buf_out = 0; + } + + } + + /* advance fifo out pointer by amount written */ + buf_rx_out += usbd_ep_write_packet(usbdev, + CDCACM_UART_ENDPOINT, packet_buf, packet_size); + buf_rx_out %= FIFO_SIZE; + } +} + -- cgit v1.2.3 From da28970c3e164d4166cb8a3e0fe59c804299ed32 Mon Sep 17 00:00:00 2001 From: Marc Singer Date: Fri, 9 Jan 2015 17:53:18 -0800 Subject: Fix to move stubs into rodata. o Stubs were declared as globals which means they will be initialized data. No need for this. Now, stubs are static const and are only present in the program image. --- src/lmi.c | 2 +- src/nrf51.c | 2 +- src/stm32f1.c | 2 +- src/stm32f4.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/lmi.c') diff --git a/src/lmi.c b/src/lmi.c index a08819e..a251242 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -63,7 +63,7 @@ static const char tm4c123gh6pm_xml_memory_map[] = "" ""; -uint16_t lmi_flash_write_stub[] = { +static const uint16_t lmi_flash_write_stub[] = { // _start: 0x4809, // ldr r0, [pc, #36] // _flashbase 0x490b, // ldr r1, [pc, #44] // _addr diff --git a/src/nrf51.c b/src/nrf51.c index 52c9749..7305d29 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -98,7 +98,7 @@ static const char nrf51_xml_memory_map[] = "" #define NRF51_PAGE_SIZE 1024 -uint16_t nrf51_flash_write_stub[] = { +static const uint16_t nrf51_flash_write_stub[] = { // _start: 0x4808, // ldr r0, [pc, #32] ; (24 <_ready>) 0x4909, // ldr r1, [pc, #36] ; (28 <_addr>) diff --git a/src/stm32f1.c b/src/stm32f1.c index d02a26d..bce00d3 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -122,7 +122,7 @@ static const char stm32hd_xml_memory_map[] = "" #define DBGMCU_IDCODE 0xE0042000 #define DBGMCU_IDCODE_F0 0x40015800 -uint16_t stm32f1_flash_write_stub[] = { +static const uint16_t stm32f1_flash_write_stub[] = { // _start: 0x4809, // ldr r0, [pc, #36] // _flashbase 0x490a, // ldr r1, [pc, #40] // _addr diff --git a/src/stm32f4.c b/src/stm32f4.c index 4f27859..148c31b 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -122,7 +122,7 @@ static const char stm32f4_xml_memory_map[] = "" #define DBGMCU_IDCODE 0xE0042000 /* This routine is uses word access. Only usable on target voltage >2.7V */ -uint16_t stm32f4_flash_write_stub[] = { +static const uint16_t stm32f4_flash_write_stub[] = { // _start: 0x480a, // ldr r0, [pc, #40] // _flashbase 0x490b, // ldr r1, [pc, #44] // _addr -- cgit v1.2.3 From 4d4813de87721528fc9a06174dd1da5c245ae2f3 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 1 Mar 2015 22:16:04 -0800 Subject: Clean up includes everywhere. All source files include general.h first and before anything else. This inlcludes platform.h and platform_support.h No header file needs to include to include any of these, but should include any others needed for it's own declarations.--- src/adiv5.c | 5 ---- src/adiv5_jtagdp.c | 3 --- src/adiv5_swdp.c | 5 ---- src/arm7tdmi.c | 4 ---- src/command.c | 6 ----- src/cortexm.c | 7 ++---- src/crc32.c | 2 +- src/gdb_main.c | 11 --------- src/gdb_packet.c | 9 ++------ src/hex_utils.c | 4 +--- src/include/adiv5.h | 1 - src/include/arm7tdmi.h | 1 - src/include/command.h | 1 - src/include/cortexm.h | 20 ++++++++++++++++ src/include/crc32.h | 2 -- src/include/gdb_packet.h | 2 -- src/include/general.h | 12 +++++++--- src/include/jtag_scan.h | 2 -- src/include/jtagtap.h | 2 -- src/include/morse.h | 2 -- src/include/platform_support.h | 41 +++++++++++++++++++++++++++++++++ src/include/swdptap.h | 2 -- src/include/target.h | 2 -- src/jtag_scan.c | 7 ------ src/kinetis.c | 3 --- src/lmi.c | 3 --- src/lpc11xx.c | 21 +++++++++++++---- src/lpc43xx.c | 5 +--- src/main.c | 10 +++----- src/nrf51.c | 3 --- src/platforms/common/usbuart.h | 1 - src/platforms/f4discovery/platform.c | 22 +++++------------- src/platforms/f4discovery/platform.h | 14 ++--------- src/platforms/f4discovery/usbdfu.c | 6 ++--- src/platforms/launchpad-icdi/platform.c | 11 ++++----- src/platforms/launchpad-icdi/platform.h | 16 +------------ src/platforms/libftdi/jtagtap.c | 1 + src/platforms/libftdi/platform.c | 15 +++--------- src/platforms/libftdi/platform.h | 5 ---- src/platforms/libftdi/swdptap.c | 2 +- src/platforms/native/platform.c | 22 ++++-------------- src/platforms/native/platform.h | 22 ++---------------- src/platforms/stlink/platform.c | 22 ++++-------------- src/platforms/stlink/platform.h | 16 ++++--------- src/platforms/stm32/cdcacm.c | 2 +- src/platforms/stm32/dfu_f1.c | 5 ++-- src/platforms/stm32/dfu_f4.c | 6 ++--- src/platforms/stm32/dfucore.c | 2 +- src/platforms/stm32/gdb_if.c | 2 +- src/platforms/stm32/gpio.h | 10 ++++++++ src/platforms/stm32/jtagtap.c | 2 -- src/platforms/stm32/traceswo.c | 5 +--- src/platforms/stm32/usbuart.c | 2 +- src/platforms/swlink/platform.c | 21 ++++------------- src/platforms/swlink/platform.h | 16 ++----------- src/platforms/tm4c/cdcacm.c | 2 +- src/platforms/tm4c/gdb_if.c | 6 +++-- src/platforms/tm4c/jtagtap.c | 1 + src/platforms/tm4c/swdptap.c | 1 - src/platforms/tm4c/traceswo.c | 5 ---- src/platforms/tm4c/usbuart.c | 4 ++-- src/sam3x.c | 3 --- src/samd.c | 4 ---- src/stm32f1.c | 3 --- src/stm32f4.c | 3 --- src/stm32l1.c | 3 --- src/target.c | 2 -- 67 files changed, 167 insertions(+), 316 deletions(-) create mode 100644 src/include/platform_support.h (limited to 'src/lmi.c') diff --git a/src/adiv5.c b/src/adiv5.c index 6dcc919..361cd75 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -25,15 +25,10 @@ * Currently doesn't use ROM table for introspection, just assumes * the device is Cortex-M3. */ - -#include -#include - #include "general.h" #include "jtag_scan.h" #include "gdb_packet.h" #include "adiv5.h" - #include "target.h" #ifndef DO_RESET_SEQ diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index fd77a04..8f62a11 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -23,14 +23,11 @@ */ #include "general.h" -#include "platform.h" #include "adiv5.h" #include "jtag_scan.h" #include "jtagtap.h" #include "morse.h" -#include - #define JTAGDP_ACK_OK 0x02 #define JTAGDP_ACK_WAIT 0x01 diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index 6bafc91..9df362f 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -23,17 +23,12 @@ */ #include "general.h" -#include "platform.h" #include "adiv5.h" - #include "swdptap.h" #include "jtagtap.h" - #include "command.h" #include "morse.h" -#include - #define SWDP_ACK_OK 0x01 #define SWDP_ACK_WAIT 0x02 #define SWDP_ACK_FAULT 0x04 diff --git a/src/arm7tdmi.c b/src/arm7tdmi.c index 1c7b443..1721787 100644 --- a/src/arm7tdmi.c +++ b/src/arm7tdmi.c @@ -24,14 +24,10 @@ */ #include "general.h" -#include "platform.h" #include "target.h" #include "jtag_scan.h" #include "jtagtap.h" -#include -#include - /* TODO: * Skeleton target. * EmbeddedICE registers, halt/resume target. diff --git a/src/command.c b/src/command.c index 7c17864..f271085 100644 --- a/src/command.c +++ b/src/command.c @@ -22,18 +22,12 @@ * commands. */ -#include -#include - #include "general.h" - #include "command.h" #include "gdb_packet.h" - #include "jtag_scan.h" #include "target.h" #include "morse.h" - #include "adiv5.h" #ifdef PLATFORM_HAS_TRACESWO diff --git a/src/cortexm.c b/src/cortexm.c index 12914d3..a016342 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -28,11 +28,6 @@ * Issues: * There are way too many magic numbers used here. */ -#include -#include -#include -#include - #include "general.h" #include "jtagtap.h" #include "jtag_scan.h" @@ -42,6 +37,8 @@ #include "gdb_packet.h" #include "cortexm.h" +#include + static char cortexm_driver_str[] = "ARM Cortex-M"; static bool cortexm_vector_catch(target *t, int argc, char *argv[]); diff --git a/src/crc32.c b/src/crc32.c index 810a9dd..42d1d48 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -#include "platform.h" +#include "general.h" #include "target.h" #if !defined(STM32F1) && !defined(STM32F4) diff --git a/src/gdb_main.c b/src/gdb_main.c index 41ab84a..17ad9a5 100644 --- a/src/gdb_main.c +++ b/src/gdb_main.c @@ -24,26 +24,15 @@ * Originally written for GDB 6.8, updated and tested with GDB 7.2. */ -#include -#include -#include - -#include - -#include "platform.h" - #include "general.h" #include "hex_utils.h" #include "gdb_if.h" #include "gdb_packet.h" #include "gdb_main.h" - #include "jtagtap.h" #include "jtag_scan.h" #include "adiv5.h" - #include "target.h" - #include "command.h" #include "crc32.h" diff --git a/src/gdb_packet.c b/src/gdb_packet.c index d43be42..4dc934f 100644 --- a/src/gdb_packet.c +++ b/src/gdb_packet.c @@ -22,18 +22,13 @@ * reception and transmission as well as some convenience functions. */ -#define _GNU_SOURCE -#include -#include -#include - -#include - #include "general.h" #include "gdb_if.h" #include "gdb_packet.h" #include "hex_utils.h" +#include + int gdb_getpacket(unsigned char *packet, int size) { diff --git a/src/hex_utils.c b/src/hex_utils.c index e477281..45382ff 100644 --- a/src/hex_utils.c +++ b/src/hex_utils.c @@ -21,9 +21,7 @@ /* Convenience function to convert to/from ascii strings of hex digits. */ -#include -#include - +#include "general.h" #include "hex_utils.h" static char hexdigits[] = "0123456789abcdef"; diff --git a/src/include/adiv5.h b/src/include/adiv5.h index 0f17119..e0ce9cf 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -21,7 +21,6 @@ #ifndef __ADIV5_H #define __ADIV5_H -#include "general.h" #include "jtag_scan.h" #include "target.h" diff --git a/src/include/arm7tdmi.h b/src/include/arm7tdmi.h index ffcd6e9..fa7d586 100644 --- a/src/include/arm7tdmi.h +++ b/src/include/arm7tdmi.h @@ -21,7 +21,6 @@ #ifndef __ARM7TDMI_H #define __ARM7TDMI_H -#include "general.h" #include "jtag_scan.h" void arm7tdmi_jtag_handler(jtag_dev_t *dev); diff --git a/src/include/command.h b/src/include/command.h index 32b0d7b..3910bbb 100644 --- a/src/include/command.h +++ b/src/include/command.h @@ -21,7 +21,6 @@ #ifndef __COMMAND_H #define __COMMAND_H -#include "general.h" #include "target.h" int command_process(target *t, char *cmd); diff --git a/src/include/cortexm.h b/src/include/cortexm.h index f1fc07a..1fd77e6 100644 --- a/src/include/cortexm.h +++ b/src/include/cortexm.h @@ -1,6 +1,26 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2015 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #ifndef __CORTEXM_H #define __CORTEXM_H +#include "target.h" + /* Private peripheral bus base address */ #define CORTEXM_PPB_BASE 0xE0000000 diff --git a/src/include/crc32.h b/src/include/crc32.h index 6cc00ea..9966d8d 100644 --- a/src/include/crc32.h +++ b/src/include/crc32.h @@ -21,8 +21,6 @@ #ifndef __CRC32_H #define __CRC32_H -#include "platform.h" - uint32_t crc32_calc(uint32_t crc, uint8_t data); uint32_t generic_crc32(struct target_s *target, uint32_t base, int len); diff --git a/src/include/gdb_packet.h b/src/include/gdb_packet.h index 9f5430f..222b86d 100644 --- a/src/include/gdb_packet.h +++ b/src/include/gdb_packet.h @@ -21,8 +21,6 @@ #ifndef __GDB_PACKET_H #define __GDB_PACKET_H -#include - int gdb_getpacket(unsigned char *packet, int size); void gdb_putpacket(unsigned char *packet, int size); #define gdb_putpacketz(packet) gdb_putpacket((packet), strlen(packet)) diff --git a/src/include/general.h b/src/include/general.h index b0721ac..b4e9aeb 100644 --- a/src/include/general.h +++ b/src/include/general.h @@ -21,15 +21,21 @@ #ifndef __GENERAL_H #define __GENERAL_H +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include + #include "platform.h" +#include "platform_support.h" #ifndef DEBUG #include #define DEBUG printf #endif -#include -#include - #endif diff --git a/src/include/jtag_scan.h b/src/include/jtag_scan.h index b425b95..aa006e7 100644 --- a/src/include/jtag_scan.h +++ b/src/include/jtag_scan.h @@ -21,8 +21,6 @@ #ifndef __JTAG_SCAN_H #define __JTAG_SCAN_H -#include "general.h" - #define JTAG_MAX_DEVS 5 #define JTAG_MAX_IR_LEN 16 diff --git a/src/include/jtagtap.h b/src/include/jtagtap.h index fd13f2b..0072594 100644 --- a/src/include/jtagtap.h +++ b/src/include/jtagtap.h @@ -21,8 +21,6 @@ #ifndef __JTAGTAP_H #define __JTAGTAP_H -#include "general.h" - /* Note: Signal names are as for the device under test. */ int jtagtap_init(void); diff --git a/src/include/morse.h b/src/include/morse.h index ac53893..5ba39b1 100644 --- a/src/include/morse.h +++ b/src/include/morse.h @@ -21,8 +21,6 @@ #ifndef __MORSE_H #define __MORSE_H -#include - extern const char *morse_msg; void morse(const char *msg, char repeat); diff --git a/src/include/platform_support.h b/src/include/platform_support.h new file mode 100644 index 0000000..cc88ab6 --- /dev/null +++ b/src/include/platform_support.h @@ -0,0 +1,41 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2015 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __PLATFORM_SUPPORT_H +#define __PLATFORM_SUPPORT_H + +#ifndef __GENERAL_H +# error "Include 'general.h' instead" +#endif + +#if defined(LIBFTDI) +void platform_init(int argc, char **argv); +#else +void platform_init(void); +#endif + +const char *platform_target_voltage(void); +int platform_hwversion(void); +void platform_delay(uint32_t delay); +void platform_srst_set_val(bool assert); +bool platform_target_get_power(void); +void platform_target_set_power(bool power); + +#endif + diff --git a/src/include/swdptap.h b/src/include/swdptap.h index 5bb0545..3263a1d 100644 --- a/src/include/swdptap.h +++ b/src/include/swdptap.h @@ -21,8 +21,6 @@ #ifndef __SWDPTAP_H #define __SWDPTAP_H -#include "general.h" - int swdptap_init(void); void swdptap_reset(void); diff --git a/src/include/target.h b/src/include/target.h index 50f1ebe..0e6d9c2 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -25,8 +25,6 @@ #ifndef __TARGET_H #define __TARGET_H -#include "general.h" - typedef struct target_s target; /* The destroy callback function will be called by target_list_free() just diff --git a/src/jtag_scan.c b/src/jtag_scan.c index 257e6c4..208a1db 100644 --- a/src/jtag_scan.c +++ b/src/jtag_scan.c @@ -22,19 +22,12 @@ * to detect devices on the scan chain and read their IDCODEs. * It depends on the low-level function provided by the platform's jtagtap.c. */ -#include -#include -#include - -#include #include "general.h" #include "jtagtap.h" #include "morse.h" #include "jtag_scan.h" - #include "gdb_packet.h" - #include "adiv5.h" #include "arm7tdmi.h" diff --git a/src/kinetis.c b/src/kinetis.c index 393bb18..4b7cf31 100644 --- a/src/kinetis.c +++ b/src/kinetis.c @@ -22,9 +22,6 @@ * the XML memory map and Flash memory programming. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/lmi.c b/src/lmi.c index a251242..8d409d0 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -27,9 +27,6 @@ * Flash erase is very slow. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/lpc11xx.c b/src/lpc11xx.c index ef26e78..d9e918e 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -1,8 +1,19 @@ - -#include -#include -#include - +/* + * This file is part of the Black Magic Debug project. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/lpc43xx.c b/src/lpc43xx.c index bfb96f7..3940fed 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -17,11 +17,8 @@ * along with this program. If not, see . */ -#include -#include -#include -#include "command.h" #include "general.h" +#include "command.h" #include "adiv5.h" #include "target.h" #include "gdb_packet.h" diff --git a/src/main.c b/src/main.c index 809d4bf..60db15c 100644 --- a/src/main.c +++ b/src/main.c @@ -22,26 +22,22 @@ * protocol loop. */ -#include -#include -#include - +#include "general.h" #include "gdb_if.h" #include "gdb_main.h" #include "jtagtap.h" #include "jtag_scan.h" - #include "target.h" int main(int argc, char **argv) { #if defined(LIBFTDI) - assert(platform_init(argc, argv) == 0); + platform_init(argc, argv); #else (void) argc; (void) argv; - assert(platform_init() == 0); + platform_init(); #endif PLATFORM_SET_FATAL_ERROR_RECOVERY(); diff --git a/src/nrf51.c b/src/nrf51.c index 7305d29..6c1a8b9 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -21,9 +21,6 @@ * the device, providing the XML memory map and Flash memory programming. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/platforms/common/usbuart.h b/src/platforms/common/usbuart.h index 39f7dcd..51f5702 100644 --- a/src/platforms/common/usbuart.h +++ b/src/platforms/common/usbuart.h @@ -22,7 +22,6 @@ #include #include -#include "general.h" void usbuart_init(void); diff --git a/src/platforms/f4discovery/platform.c b/src/platforms/f4discovery/platform.c index e051564..cf6cdf3 100644 --- a/src/platforms/f4discovery/platform.c +++ b/src/platforms/f4discovery/platform.c @@ -22,7 +22,11 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" +#include "morse.h" + #include #include #include @@ -32,16 +36,12 @@ #include #include -#include "jtag_scan.h" -#include "usbuart.h" -#include "morse.h" - uint8_t running_status; volatile uint32_t timeout_counter; jmp_buf fatal_error_jmpbuf; -int platform_init(void) +void platform_init(void) { /* Check the USER button*/ rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN); @@ -86,17 +86,7 @@ int platform_init(void) systick_counter_enable(); usbuart_init(); - cdcacm_init(); - - // Set recovery point - if (setjmp(fatal_error_jmpbuf)) { - return 0; // Do nothing on failure - } - - jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/f4discovery/platform.h b/src/platforms/f4discovery/platform.h index 140e8d1..f58205d 100644 --- a/src/platforms/f4discovery/platform.h +++ b/src/platforms/f4discovery/platform.h @@ -24,19 +24,12 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include -#include -#include -#include -#include - -#include -#include - #include "gdb_packet.h" #include "gpio.h" #include "morse.h" +#include + #define PLATFORM_HAS_TRACESWO #define BOARD_IDENT "Black Magic Probe (F4Discovery), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade) for F4Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -173,9 +166,6 @@ extern jmp_buf fatal_error_jmpbuf; longjmp(fatal_error_jmpbuf, (error)); \ } -int platform_init(void); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); static inline int platform_hwversion(void) { return 0; diff --git a/src/platforms/f4discovery/usbdfu.c b/src/platforms/f4discovery/usbdfu.c index 7070ade..6a40295 100644 --- a/src/platforms/f4discovery/usbdfu.c +++ b/src/platforms/f4discovery/usbdfu.c @@ -17,14 +17,14 @@ * along with this program. If not, see . */ -#include +#include "general.h" +#include "usbdfu.h" + #include #include #include #include -#include "usbdfu.h" - void dfu_detach(void) { /* USB device must detach, we just reset... */ diff --git a/src/platforms/launchpad-icdi/platform.c b/src/platforms/launchpad-icdi/platform.c index 1e66e12..0e3fb85 100644 --- a/src/platforms/launchpad-icdi/platform.c +++ b/src/platforms/launchpad-icdi/platform.c @@ -1,5 +1,6 @@ -#include "platform.h" +#include "general.h" #include "gdb_if.h" +#include "cdcacm.h" #include "usbuart.h" #include @@ -26,14 +27,14 @@ void sys_tick_handler(void) trace_tick(); } -int +void platform_init(void) { int i; for(i=0; i<1000000; i++); rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLL_DIV_80MHZ); - + // Enable all JTAG ports and set pins to output periph_clock_enable(RCC_GPIOA); periph_clock_enable(RCC_GPIOB); @@ -59,10 +60,6 @@ platform_init(void) usbuart_init(); cdcacm_init(); - - //jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/launchpad-icdi/platform.h b/src/platforms/launchpad-icdi/platform.h index 8c343a8..5f686f4 100644 --- a/src/platforms/launchpad-icdi/platform.h +++ b/src/platforms/launchpad-icdi/platform.h @@ -1,16 +1,13 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include +#include "gdb_packet.h" #include -#include #include #include -#include "gdb_packet.h" - #define CDCACM_PACKET_SIZE 64 #define BOARD_IDENT "Black Magic Probe (Launchpad ICDI), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade) for Launchpad, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -110,8 +107,6 @@ extern usbd_driver lm4f_usb_driver; #define PLATFORM_HAS_TRACESWO -int platform_init(void); - inline static void gpio_set_val(uint32_t port, uint8_t pin, uint8_t val) { gpio_write(port, pin, val == 0 ? 0 : 0xff); } @@ -120,15 +115,6 @@ inline static uint8_t gpio_get(uint32_t port, uint8_t pin) { return !(gpio_read(port, pin) == 0); } -void platform_delay(uint32_t delay); -const char *platform_target_voltage(void); - -/* */ -void cdcacm_init(void); -/* Returns current usb configuration, or 0 if not configured. */ -int cdcacm_get_config(void); -int cdcacm_get_dtr(void); - #define disconnect_usb() do { usbd_disconnect(usbdev,1); nvic_disable_irq(USB_IRQ);} while(0) #define setup_vbus_irq() diff --git a/src/platforms/libftdi/jtagtap.c b/src/platforms/libftdi/jtagtap.c index 91f6ae2..c9bc876 100644 --- a/src/platforms/libftdi/jtagtap.c +++ b/src/platforms/libftdi/jtagtap.c @@ -69,6 +69,7 @@ void jtagtap_reset(void) void jtagtap_srst(bool assert) { + (void)assert; platform_buffer_flush(); //ftdi_write_data(ftdic, "\x80\x88\xAB", 3); //usleep(1000); diff --git a/src/platforms/libftdi/platform.c b/src/platforms/libftdi/platform.c index 723efa3..e53f011 100644 --- a/src/platforms/libftdi/platform.c +++ b/src/platforms/libftdi/platform.c @@ -17,14 +17,10 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#include "platform.h" +#include "general.h" #include "gdb_if.h" -#include "jtag_scan.h" -#include -#include #include -#include struct ftdi_context *ftdic; @@ -121,7 +117,7 @@ static struct cable_desc_s { }, }; -int platform_init(int argc, char **argv) +void platform_init(int argc, char **argv) { int err; int c; @@ -149,7 +145,7 @@ int platform_init(int argc, char **argv) if (index == sizeof(cable_desc)/sizeof(cable_desc[0])){ fprintf(stderr, "No cable matching %s found\n",cablename); - return -1; + exit(-1); } if (cable_desc[index].dbus_data) @@ -212,12 +208,7 @@ int platform_init(int argc, char **argv) } assert(ftdi_write_data(ftdic, ftdi_init, 9) == 9); - assert(gdb_if_init() == 0); - - jtag_scan(NULL); - - return 0; } void platform_buffer_flush(void) diff --git a/src/platforms/libftdi/platform.h b/src/platforms/libftdi/platform.h index a95a3f4..135b2e3 100644 --- a/src/platforms/libftdi/platform.h +++ b/src/platforms/libftdi/platform.h @@ -21,7 +21,6 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include #include #ifndef WIN32 @@ -42,10 +41,6 @@ extern struct ftdi_context *ftdic; -int platform_init(int argc, char **argv); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); - void platform_buffer_flush(void); int platform_buffer_write(const uint8_t *data, int size); int platform_buffer_read(uint8_t *data, int size); diff --git a/src/platforms/libftdi/swdptap.c b/src/platforms/libftdi/swdptap.c index ef350de..eb6e65e 100644 --- a/src/platforms/libftdi/swdptap.c +++ b/src/platforms/libftdi/swdptap.c @@ -26,7 +26,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "swdptap.h" static void swdptap_turnaround(uint8_t dir); diff --git a/src/platforms/native/platform.c b/src/platforms/native/platform.c index 3f61f5f..9b39238 100644 --- a/src/platforms/native/platform.c +++ b/src/platforms/native/platform.c @@ -22,7 +22,10 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" +#include "morse.h" #include #include @@ -33,11 +36,6 @@ #include #include -#include "jtag_scan.h" -#include "cdcacm.h" -#include "usbuart.h" -#include "morse.h" - uint8_t running_status; volatile uint32_t timeout_counter; @@ -62,7 +60,7 @@ int platform_hwversion(void) return hwversion; } -int platform_init(void) +void platform_init(void) { rcc_clock_setup_in_hse_8mhz_out_72mhz(); @@ -136,16 +134,6 @@ int platform_init(void) cdcacm_init(); usbuart_init(); - - /* Set recovery point */ - if (setjmp(fatal_error_jmpbuf)) { - /* Do nothing on failure */ - return 0; - } - - jtag_scan(NULL); - - return 0; } void platform_srst_set_val(bool assert) diff --git a/src/platforms/native/platform.h b/src/platforms/native/platform.h index 321c3f3..5688e60 100644 --- a/src/platforms/native/platform.h +++ b/src/platforms/native/platform.h @@ -24,20 +24,12 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include -#include -#include - -#include -#include - -#include -#include - #include "gdb_packet.h" #include "gpio.h" #include "morse.h" +#include + #define PLATFORM_HAS_TRACESWO #define PLATFORM_HAS_POWER_SWITCH #define BOARD_IDENT "Black Magic Probe" @@ -173,13 +165,6 @@ extern jmp_buf fatal_error_jmpbuf; longjmp(fatal_error_jmpbuf, (error)); \ } while (0) -int platform_init(void); -const char *platform_target_voltage(void); -int platform_hwversion(void); -void platform_set_timeout(uint32_t ms); -bool platform_timeout_expired(void); -void platform_delay(uint32_t delay); - /* Use newlib provided integer only stdio functions */ #define sscanf siscanf #define sprintf siprintf @@ -188,9 +173,6 @@ void platform_delay(uint32_t delay); #define disconnect_usb() gpio_set_mode(USB_PU_PORT, GPIO_MODE_INPUT, 0, USB_PU_PIN); void assert_boot_pin(void); void setup_vbus_irq(void); -void platform_srst_set_val(bool assert); -bool platform_target_get_power(void); -void platform_target_set_power(bool power); #endif diff --git a/src/platforms/stlink/platform.c b/src/platforms/stlink/platform.c index 6ef8c77..6194d92 100644 --- a/src/platforms/stlink/platform.c +++ b/src/platforms/stlink/platform.c @@ -22,7 +22,10 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" + #include #include #include @@ -31,11 +34,6 @@ #include #include -#include "jtag_scan.h" -#include - -#include - uint8_t running_status; volatile uint32_t timeout_counter; @@ -68,7 +66,7 @@ int platform_hwversion(void) return hwversion; } -int platform_init(void) +void platform_init(void) { rcc_clock_setup_in_hse_8mhz_out_72mhz(); @@ -119,16 +117,6 @@ int platform_init(void) SCB_VTOR = 0x2000; /* Relocate interrupt vector table here */ cdcacm_init(); - - /* Set recovery point */ - if (setjmp(fatal_error_jmpbuf)) { - /* Do nothing on failure */ - return 0; - } - - jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/stlink/platform.h b/src/platforms/stlink/platform.h index a33ca06..5768817 100644 --- a/src/platforms/stlink/platform.h +++ b/src/platforms/stlink/platform.h @@ -24,18 +24,14 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include +#include "gdb_packet.h" +#include "gpio.h" + #include #include - -#include #include #include -#include - -#include "gdb_packet.h" -#include "gpio.h" #define BOARD_IDENT "Black Magic Probe (STLINK), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade) for STLink/Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -151,11 +147,6 @@ extern uint16_t led_idle_run; longjmp(fatal_error_jmpbuf, (error)); \ } while (0) -int platform_init(void); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); -void platform_srst_set_val(bool assert); - /* Use newlib provided integer only stdio functions */ #define sscanf siscanf #define sprintf siprintf @@ -163,6 +154,7 @@ void platform_srst_set_val(bool assert); void disconnect_usb(void); void assert_boot_pin(void); +void setup_vbus_irq(void); #endif diff --git a/src/platforms/stm32/cdcacm.c b/src/platforms/stm32/cdcacm.c index 074b534..577925a 100644 --- a/src/platforms/stm32/cdcacm.c +++ b/src/platforms/stm32/cdcacm.c @@ -33,7 +33,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "gdb_if.h" #include "cdcacm.h" #if defined(PLATFORM_HAS_TRACESWO) diff --git a/src/platforms/stm32/dfu_f1.c b/src/platforms/stm32/dfu_f1.c index bb1e274..abbdbe6 100644 --- a/src/platforms/stm32/dfu_f1.c +++ b/src/platforms/stm32/dfu_f1.c @@ -16,12 +16,11 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -#include "platform.h" +#include "general.h" +#include "usbdfu.h" #include #include -#include "usbdfu.h" #define FLASH_OBP_RDP 0x1FFFF800 #define FLASH_OBP_WRP10 0x1FFFF808 diff --git a/src/platforms/stm32/dfu_f4.c b/src/platforms/stm32/dfu_f4.c index 1065938..2ececa0 100644 --- a/src/platforms/stm32/dfu_f4.c +++ b/src/platforms/stm32/dfu_f4.c @@ -16,8 +16,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -#include "platform.h" +#include "general.h" +#include "usbdfu.h" #if defined(STM32F2) # include @@ -26,8 +26,6 @@ #endif #include -#include "usbdfu.h" - static uint32_t sector_addr[] = { 0x8000000, 0x8004000, 0x8008000, 0x800c000, 0x8010000, 0x8020000, 0x8040000, 0x8060000, diff --git a/src/platforms/stm32/dfucore.c b/src/platforms/stm32/dfucore.c index 77cef4e..7b733d7 100644 --- a/src/platforms/stm32/dfucore.c +++ b/src/platforms/stm32/dfucore.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include "platform.h" +#include "general.h" #include #if defined(STM32F1) diff --git a/src/platforms/stm32/gdb_if.c b/src/platforms/stm32/gdb_if.c index 6cc9084..286c66b 100644 --- a/src/platforms/stm32/gdb_if.c +++ b/src/platforms/stm32/gdb_if.c @@ -22,7 +22,7 @@ * Serial Debugging protocol is implemented. This implementation for STM32 * uses the USB CDC-ACM device bulk endpoints to implement the channel. */ -#include "platform.h" +#include "general.h" #include "cdcacm.h" #include "gdb_if.h" diff --git a/src/platforms/stm32/gpio.h b/src/platforms/stm32/gpio.h index 035f3c9..ee8275e 100644 --- a/src/platforms/stm32/gpio.h +++ b/src/platforms/stm32/gpio.h @@ -20,6 +20,16 @@ #ifndef __GPIO_H #define __GPIO_H +#include + +#ifndef STM32F4 +# include +# include +#else +# include +# include +#endif + #define INLINE_GPIO #define gpio_set_val(port, pin, val) do { \ diff --git a/src/platforms/stm32/jtagtap.c b/src/platforms/stm32/jtagtap.c index 2d09b84..3c45a81 100644 --- a/src/platforms/stm32/jtagtap.c +++ b/src/platforms/stm32/jtagtap.c @@ -23,9 +23,7 @@ #include #include "general.h" - #include "jtagtap.h" -#include "platform.h" int jtagtap_init(void) { diff --git a/src/platforms/stm32/traceswo.c b/src/platforms/stm32/traceswo.c index 29bae8f..a2e704d 100644 --- a/src/platforms/stm32/traceswo.c +++ b/src/platforms/stm32/traceswo.c @@ -32,15 +32,12 @@ * The core can then process the buffer to extract the frame. */ #include "general.h" +#include "cdcacm.h" #include #include #include -#include -#include "platform.h" -#include "cdcacm.h" - void traceswo_init(void) { TRACE_TIM_CLK_EN(); diff --git a/src/platforms/stm32/usbuart.c b/src/platforms/stm32/usbuart.c index 970a609..cce2904 100644 --- a/src/platforms/stm32/usbuart.c +++ b/src/platforms/stm32/usbuart.c @@ -27,7 +27,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "cdcacm.h" #define USBUART_TIMER_FREQ_HZ 1000000U /* 1us per tick */ diff --git a/src/platforms/swlink/platform.c b/src/platforms/swlink/platform.c index 853cbc9..168ba2a 100644 --- a/src/platforms/swlink/platform.c +++ b/src/platforms/swlink/platform.c @@ -22,7 +22,10 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" + #include #include #include @@ -31,17 +34,12 @@ #include #include -#include "jtag_scan.h" -#include - -#include - uint8_t running_status; volatile uint32_t timeout_counter; jmp_buf fatal_error_jmpbuf; -int platform_init(void) +void platform_init(void) { uint32_t data; rcc_clock_setup_in_hse_8mhz_out_72mhz(); @@ -98,15 +96,6 @@ int platform_init(void) SCB_VTOR = 0x2000; // Relocate interrupt vector table here cdcacm_init(); - - // Set recovery point - if (setjmp(fatal_error_jmpbuf)) { - return 0; // Do nothing on failure - } - - jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/swlink/platform.h b/src/platforms/swlink/platform.h index 26cb7a6..dec5548 100644 --- a/src/platforms/swlink/platform.h +++ b/src/platforms/swlink/platform.h @@ -24,19 +24,11 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include -#include -#include - -#include -#include - -#include -#include - #include "gdb_packet.h" #include "gpio.h" +#include + #define BOARD_IDENT "Black Magic Probe (SWLINK), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade), STM8S Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_UPD "Black Magic (DFU Upgrade), STM8S Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -149,10 +141,6 @@ extern jmp_buf fatal_error_jmpbuf; longjmp(fatal_error_jmpbuf, (error)); \ } -int platform_init(void); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); - /* Use newlib provided integer only stdio functions */ #define sscanf siscanf #define sprintf siprintf diff --git a/src/platforms/tm4c/cdcacm.c b/src/platforms/tm4c/cdcacm.c index 041d85b..2677ad5 100644 --- a/src/platforms/tm4c/cdcacm.c +++ b/src/platforms/tm4c/cdcacm.c @@ -35,7 +35,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "gdb_if.h" #if defined(PLATFORM_HAS_TRACESWO) #include diff --git a/src/platforms/tm4c/gdb_if.c b/src/platforms/tm4c/gdb_if.c index b14bbd3..7119638 100644 --- a/src/platforms/tm4c/gdb_if.c +++ b/src/platforms/tm4c/gdb_if.c @@ -22,10 +22,12 @@ * Serial Debugging protocol is implemented. This implementation for STM32 * uses the USB CDC-ACM device bulk endpoints to implement the channel. */ -#include "platform.h" -#include +#include "general.h" #include "gdb_if.h" +#include "cdcacm.h" + +#include static volatile uint32_t head_out, tail_out; static volatile uint32_t count_in; diff --git a/src/platforms/tm4c/jtagtap.c b/src/platforms/tm4c/jtagtap.c index f340b1e..e0bdd68 100644 --- a/src/platforms/tm4c/jtagtap.c +++ b/src/platforms/tm4c/jtagtap.c @@ -1,3 +1,4 @@ +#include "general.h" #include "jtagtap.h" int diff --git a/src/platforms/tm4c/swdptap.c b/src/platforms/tm4c/swdptap.c index 7004598..058f6ba 100644 --- a/src/platforms/tm4c/swdptap.c +++ b/src/platforms/tm4c/swdptap.c @@ -1,5 +1,4 @@ #include "general.h" -#include "platform.h" #include "swdptap.h" static void swdptap_turnaround(uint8_t dir) diff --git a/src/platforms/tm4c/traceswo.c b/src/platforms/tm4c/traceswo.c index eb63139..03c6d66 100644 --- a/src/platforms/tm4c/traceswo.c +++ b/src/platforms/tm4c/traceswo.c @@ -32,14 +32,9 @@ #include #include #include - #include - #include -#include -#include "platform.h" - void traceswo_init(void) { periph_clock_enable(RCC_GPIOD); diff --git a/src/platforms/tm4c/usbuart.c b/src/platforms/tm4c/usbuart.c index bb769f0..da82198 100644 --- a/src/platforms/tm4c/usbuart.c +++ b/src/platforms/tm4c/usbuart.c @@ -19,6 +19,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ +#include "general.h" +#include "cdcacm.h" #include #include @@ -27,8 +29,6 @@ #include #include -#include - #define FIFO_SIZE 128 /* RX Fifo buffer */ diff --git a/src/sam3x.c b/src/sam3x.c index e6b8f2e..ef99290 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -22,9 +22,6 @@ * the device, providing the XML memory map and Flash memory programming. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/samd.c b/src/samd.c index b043c50..1a7a553 100644 --- a/src/samd.c +++ b/src/samd.c @@ -32,10 +32,6 @@ * particularly Sections 12. DSU and 20. NVMCTRL */ -#include -#include -#include - #include "general.h" #include "jtagtap.h" #include "adiv5.h" diff --git a/src/stm32f1.c b/src/stm32f1.c index bce00d3..017196a 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -29,9 +29,6 @@ * Programming manual - STM32F10xxx Flash memory microcontrollers */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/stm32f4.c b/src/stm32f4.c index 148c31b..bc3572f 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -30,9 +30,6 @@ * manual */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/stm32l1.c b/src/stm32l1.c index 0472885..227f67c 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -29,9 +29,6 @@ * Flash and EEPROM programming */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/target.c b/src/target.c index 2a68f23..4299a45 100644 --- a/src/target.c +++ b/src/target.c @@ -21,8 +21,6 @@ #include "general.h" #include "target.h" -#include - target *target_list = NULL; bool connect_assert_srst; -- cgit v1.2.3 From 6f5b1873d7b986fe7b3bc1f267bae9f7649630a5 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 14 Mar 2015 15:18:22 -0700 Subject: Use size_t for sizes in flash functions. Fix all sign compare warnings. --- src/Makefile | 1 - src/cortexm.c | 4 ++-- src/include/target.h | 4 ++-- src/kinetis.c | 8 ++++---- src/lmi.c | 8 ++++---- src/lpc11xx.c | 12 ++++++------ src/lpc43xx.c | 10 +++++----- src/nrf51.c | 8 ++++---- src/platforms/libftdi/platform.c | 2 +- src/sam3x.c | 12 ++++++------ src/samd.c | 8 ++++---- src/stm32f1.c | 17 +++++++++-------- src/stm32f4.c | 8 ++++---- src/stm32l0.c | 34 +++++++++++++++++----------------- src/stm32l1.c | 9 +++++---- 15 files changed, 73 insertions(+), 72 deletions(-) (limited to 'src/lmi.c') diff --git a/src/Makefile b/src/Makefile index 7ea7865..80e86fe 100644 --- a/src/Makefile +++ b/src/Makefile @@ -10,7 +10,6 @@ endif BUILDDATE := `date +"%Y%m%d"` CFLAGS += -Wall -Wextra -Wno-char-subscripts\ - -Wno-sign-compare \ -O2 -std=gnu99 -g3 -DBUILDDATE=\"$(BUILDDATE)\"\ -I. -Iinclude -Iplatforms/common -I$(PLATFORM_DIR) \ -DVERSION_SUFFIX=\"`../scripts/setlocalversion`\" -MD diff --git a/src/cortexm.c b/src/cortexm.c index b3b657f..b1d3569 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -757,13 +757,13 @@ static bool cortexm_vector_catch(target *t, int argc, char *argv[]) const char *vectors[] = {"reset", NULL, NULL, NULL, "mm", "nocp", "chk", "stat", "bus", "int", "hard"}; uint32_t tmp = 0; - unsigned i, j; + unsigned i; if ((argc < 3) || ((argv[1][0] != 'e') && (argv[1][0] != 'd'))) { gdb_out("usage: monitor vector_catch (enable|disable) " "(hard|int|bus|stat|chk|nocp|mm|reset)\n"); } else { - for (j = 0; j < argc; j++) + for (int j = 0; j < argc; j++) for (i = 0; i < sizeof(vectors) / sizeof(char*); i++) { if (vectors[i] && !strcmp(vectors[i], argv[j])) tmp |= 1 << i; diff --git a/src/include/target.h b/src/include/target.h index a2369e3..5db79a7 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -180,9 +180,9 @@ struct target_s { /* Flash memory access functions */ const char *xml_mem_map; - int (*flash_erase)(struct target_s *target, uint32_t addr, int len); + int (*flash_erase)(struct target_s *target, uint32_t addr, size_t len); int (*flash_write)(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); /* Host I/O support */ void (*hostio_reply)(target *t, int32_t retcode, uint32_t errcode); diff --git a/src/kinetis.c b/src/kinetis.c index 4b7cf31..b260d2a 100644 --- a/src/kinetis.c +++ b/src/kinetis.c @@ -54,9 +54,9 @@ #define KL25_PAGESIZE 0x400 -static int kl25_flash_erase(struct target_s *target, uint32_t addr, int len); +static int kl25_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int kl25_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static const char kl25_xml_memory_map[] = "" /* ">2)+2]; data[0] = dest; diff --git a/src/lpc11xx.c b/src/lpc11xx.c index d9e918e..b6309c2 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -63,9 +63,9 @@ static const char lpc8xx_driver[] = "lpc8xx"; static const char lpc11xx_driver[] = "lpc11xx"; static void lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned param_len); static int lpc11xx_flash_prepare(struct target_s *target, uint32_t addr, int len); -static int lpc11xx_flash_erase(struct target_s *target, uint32_t addr, int len); +static int lpc11xx_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, - int len); + size_t len); /* * Note that this memory map is actually for the largest of the lpc11xx devices; @@ -220,7 +220,7 @@ lpc11xx_flash_prepare(struct target_s *target, uint32_t addr, int len) } static int -lpc11xx_flash_erase(struct target_s *target, uint32_t addr, int len) +lpc11xx_flash_erase(struct target_s *target, uint32_t addr, size_t len) { if (addr % flash_page_size(target)) @@ -249,7 +249,7 @@ lpc11xx_flash_erase(struct target_s *target, uint32_t addr, int len) } static int -lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, int len) +lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { unsigned first_chunk = dest / IAP_PGM_CHUNKSIZE; unsigned last_chunk = (dest + len - 1) / IAP_PGM_CHUNKSIZE; @@ -258,7 +258,7 @@ lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, for (chunk = first_chunk; chunk <= last_chunk; chunk++) { - DEBUG("chunk %u len %d\n", chunk, len); + DEBUG("chunk %u len %zu\n", chunk, len); /* first and last chunk may require special handling */ if ((chunk == first_chunk) || (chunk == last_chunk)) { @@ -266,7 +266,7 @@ lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, memset(flash_pgm.data, 0xff, sizeof(flash_pgm.data)); /* copy as much as fits */ - int copylen = IAP_PGM_CHUNKSIZE - chunk_offset; + size_t copylen = IAP_PGM_CHUNKSIZE - chunk_offset; if (copylen > len) copylen = len; memcpy(&flash_pgm.data[chunk_offset], src, copylen); diff --git a/src/lpc43xx.c b/src/lpc43xx.c index 3940fed..eca7338 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -127,9 +127,9 @@ static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, unsigned param_len); static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len); -static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, int len); +static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int lpc43xx_flash_write(struct target_s *target, - uint32_t dest, const uint8_t *src, int len); + uint32_t dest, const uint8_t *src, size_t len); static void lpc43xx_set_internal_clock(struct target_s *target); static void lpc43xx_wdt_set_period(struct target_s *target); static void lpc43xx_wdt_pet(struct target_s *target); @@ -384,7 +384,7 @@ static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len return 0; } -static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, int len) +static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t len) { struct flash_program flash_pgm; @@ -433,7 +433,7 @@ static void lpc43xx_set_internal_clock(struct target_s *target) } static int lpc43xx_flash_write(struct target_s *target, - uint32_t dest, const uint8_t *src, int len) + uint32_t dest, const uint8_t *src, size_t len) { unsigned first_chunk = dest / IAP_PGM_CHUNKSIZE; unsigned last_chunk = (dest + len - 1) / IAP_PGM_CHUNKSIZE; @@ -455,7 +455,7 @@ static int lpc43xx_flash_write(struct target_s *target, memset(flash_pgm.data, 0xff, sizeof(flash_pgm.data)); /* copy as much as fits */ - int copylen = IAP_PGM_CHUNKSIZE - chunk_offset; + size_t copylen = IAP_PGM_CHUNKSIZE - chunk_offset; if (copylen > len) copylen = len; diff --git a/src/nrf51.c b/src/nrf51.c index 6c1a8b9..55c9a58 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -27,9 +27,9 @@ #include "command.h" #include "gdb_packet.h" -static int nrf51_flash_erase(struct target_s *target, uint32_t addr, int len); +static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int nrf51_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static bool nrf51_cmd_erase_all(target *t); static bool nrf51_cmd_read_hwid(target *t); @@ -163,7 +163,7 @@ bool nrf51_probe(struct target_s *target) return false; } -static int nrf51_flash_erase(struct target_s *target, uint32_t addr, int len) +static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); @@ -210,7 +210,7 @@ static int nrf51_flash_erase(struct target_s *target, uint32_t addr, int len) } static int nrf51_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) + const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; diff --git a/src/platforms/libftdi/platform.c b/src/platforms/libftdi/platform.c index e53f011..634090d 100644 --- a/src/platforms/libftdi/platform.c +++ b/src/platforms/libftdi/platform.c @@ -121,7 +121,7 @@ void platform_init(int argc, char **argv) { int err; int c; - int index = 0; + unsigned index = 0; char *serial = NULL; char * cablename = "ftdi"; uint8_t ftdi_init[9] = {TCK_DIVISOR, 0x01, 0x00, SET_BITS_LOW, 0,0, diff --git a/src/sam3x.c b/src/sam3x.c index 902f267..7141cb5 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -28,9 +28,9 @@ #include "command.h" #include "gdb_packet.h" -static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len); +static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int sam3x_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static bool sam3x_cmd_gpnvm_get(target *t); static bool sam3x_cmd_gpnvm_set(target *t, int argc, char *argv[]); @@ -285,7 +285,7 @@ sam3x_flash_base(struct target_s *target, uint32_t addr, uint32_t *offset) return SAM3N_EEFC_BASE; } -static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len) +static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) { uint32_t offset; uint32_t base = sam3x_flash_base(target, addr, &offset); @@ -341,7 +341,7 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len) } static int sam3x_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) + const uint8_t *src, size_t len) { unsigned page_size; if (strcmp(target->driver, "Atmel SAM4S") == 0) { @@ -359,7 +359,7 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, for (unsigned chunk = first_chunk; chunk <= last_chunk; chunk++) { - DEBUG("chunk %u len %d\n", chunk, len); + DEBUG("chunk %u len %zu\n", chunk, len); /* first and last chunk may require special handling */ if ((chunk == first_chunk) || (chunk == last_chunk)) { @@ -367,7 +367,7 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, memset(buf, 0xff, sizeof(buf)); /* copy as much as fits */ - int copylen = page_size - offset; + size_t copylen = page_size - offset; if (copylen > len) copylen = len; memcpy(&buf[offset], src, copylen); diff --git a/src/samd.c b/src/samd.c index 1a7a553..6f73956 100644 --- a/src/samd.c +++ b/src/samd.c @@ -40,9 +40,9 @@ #include "gdb_packet.h" #include "cortexm.h" -static int samd_flash_erase(struct target_s *target, uint32_t addr, int len); +static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int samd_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static bool samd_cmd_erase_all(target *t); static bool samd_cmd_lock_flash(target *t); @@ -479,7 +479,7 @@ static void samd_unlock_current_address(struct target_s *target) /** * Erase flash row by row */ -static int samd_flash_erase(struct target_s *target, uint32_t addr, int len) +static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); @@ -515,7 +515,7 @@ static int samd_flash_erase(struct target_s *target, uint32_t addr, int len) * Write flash page by page */ static int samd_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) + const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); diff --git a/src/stm32f1.c b/src/stm32f1.c index 017196a..405bc1a 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -45,12 +45,12 @@ const struct command_s stm32f1_cmd_list[] = { }; -static int stm32md_flash_erase(struct target_s *target, uint32_t addr, int len); -static int stm32hd_flash_erase(struct target_s *target, uint32_t addr, int len); -static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, int len, +static int stm32md_flash_erase(struct target_s *target, uint32_t addr, size_t len); +static int stm32hd_flash_erase(struct target_s *target, uint32_t addr, size_t len); +static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, size_t len, uint32_t pagesize); static int stm32f1_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static const char stm32f1_driver_str[] = "STM32, Medium density."; static const char stm32hd_driver_str[] = "STM32, High density."; @@ -229,7 +229,8 @@ static void stm32f1_flash_unlock(ADIv5_AP_t *ap) adiv5_ap_mem_write(ap, FLASH_KEYR, KEY2); } -static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, int len, uint32_t pagesize) +static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, + size_t len, uint32_t pagesize) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; @@ -264,18 +265,18 @@ static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, int len, return 0; } -static int stm32hd_flash_erase(struct target_s *target, uint32_t addr, int len) +static int stm32hd_flash_erase(struct target_s *target, uint32_t addr, size_t len) { return stm32f1_flash_erase(target, addr, len, 0x800); } -static int stm32md_flash_erase(struct target_s *target, uint32_t addr, int len) +static int stm32md_flash_erase(struct target_s *target, uint32_t addr, size_t len) { return stm32f1_flash_erase(target, addr, len, 0x400); } static int stm32f1_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) + const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; diff --git a/src/stm32f4.c b/src/stm32f4.c index bc3572f..fac097a 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -46,9 +46,9 @@ const struct command_s stm32f4_cmd_list[] = { }; -static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len); +static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int stm32f4_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static const char stm32f4_driver_str[] = "STM32F4xx"; @@ -189,7 +189,7 @@ static void stm32f4_flash_unlock(ADIv5_AP_t *ap) } } -static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len) +static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; @@ -237,7 +237,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len) } static int stm32f4_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) + const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; diff --git a/src/stm32l0.c b/src/stm32l0.c index 0de028f..2e30035 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -125,32 +125,32 @@ static int inhibit_stubs; /* Local option to force non-stub flash IO */ static int stm32lx_nvm_erase(struct target_s* target, - uint32_t addr, int len); + uint32_t addr, size_t len); static int stm32lx_nvm_write(struct target_s* target, uint32_t destination, const uint8_t* source, - int size); + size_t size); static int stm32lx_nvm_prog_erase(struct target_s* target, - uint32_t addr, int len); + uint32_t addr, size_t len); static int stm32lx_nvm_prog_write(struct target_s* target, uint32_t destination, const uint8_t* source, - int size); + size_t size); static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, - uint32_t addr, int len); + uint32_t addr, size_t len); static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, uint32_t destination, const uint8_t* source, - int size); + size_t size); static int stm32lx_nvm_data_erase(struct target_s* target, - uint32_t addr, int len); + uint32_t addr, size_t len); static int stm32lx_nvm_data_write(struct target_s* target, uint32_t destination, const uint8_t* source, - int size); + size_t size); static bool stm32lx_cmd_option (target* t, int argc, char** argv); static bool stm32lx_cmd_eeprom (target* t, int argc, char** argv); @@ -371,7 +371,7 @@ static bool stm32lx_nvm_opt_unlock(ADIv5_AP_t* ap, uint32_t nvm) when the MCU hasn't entered a fault state(see NOTES). The flash array is erased for all pages from addr to addr+len inclusive. */ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, - uint32_t addr, int size) + uint32_t addr, size_t size) { struct stm32lx_nvm_stub_info info; const uint32_t nvm = stm32lx_nvm_phys(target); @@ -417,7 +417,7 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, uint32_t destination, const uint8_t* source, - int size) + size_t size) { struct stm32lx_nvm_stub_info info; const uint32_t nvm = stm32lx_nvm_phys(target); @@ -491,7 +491,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, /** Erase a region of NVM for STM32Lx. This is the lead function and it will invoke an implementation, stubbed or not depending on the options and the range of addresses. */ -static int stm32lx_nvm_erase(struct target_s* target, uint32_t addr, int size) +static int stm32lx_nvm_erase(struct target_s* target, uint32_t addr, size_t size) { if (addr >= STM32Lx_NVM_EEPROM_PHYS) return stm32lx_nvm_data_erase(target, addr, size); @@ -515,7 +515,7 @@ static int stm32lx_nvm_erase(struct target_s* target, uint32_t addr, int size) static int stm32lx_nvm_write(struct target_s* target, uint32_t destination, const uint8_t* source, - int size) + size_t size) { if (destination >= STM32Lx_NVM_EEPROM_PHYS) return stm32lx_nvm_data_write(target, destination, source, @@ -556,7 +556,7 @@ static int stm32lx_nvm_write(struct target_s* target, flash array is erased for all pages from addr to addr+len inclusive. NVM register file address chosen from target. */ static int stm32lx_nvm_prog_erase(struct target_s* target, - uint32_t addr, int len) + uint32_t addr, size_t len) { ADIv5_AP_t* ap = adiv5_target_ap(target); const size_t page_size = stm32lx_nvm_prog_page_size(target); @@ -617,7 +617,7 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, static int stm32lx_nvm_prog_write(struct target_s* target, uint32_t destination, const uint8_t* source_8, - int size) + size_t size) { ADIv5_AP_t* ap = adiv5_target_ap(target); const uint32_t nvm = stm32lx_nvm_phys(target); @@ -705,7 +705,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, addr+len, inclusive, on a word boundary. NVM register file address chosen from target. */ static int stm32lx_nvm_data_erase(struct target_s* target, - uint32_t addr, int len) + uint32_t addr, size_t len) { ADIv5_AP_t* ap = adiv5_target_ap(target); const size_t page_size = stm32lx_nvm_data_page_size(target); @@ -763,7 +763,7 @@ static int stm32lx_nvm_data_erase(struct target_s* target, static int stm32lx_nvm_data_write(struct target_s* target, uint32_t destination, const uint8_t* source_8, - int size) + size_t size) { ADIv5_AP_t* ap = adiv5_target_ap(target); const uint32_t nvm = stm32lx_nvm_phys(target); @@ -933,7 +933,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) goto usage; /* Report the current option values */ - for(int i = 0; i < opt_size; i += sizeof(uint32_t)) { + for(unsigned i = 0; i < opt_size; i += sizeof(uint32_t)) { uint32_t addr = STM32Lx_NVM_OPT_PHYS + i; uint32_t val = adiv5_ap_mem_read(ap, addr); gdb_outf("0x%08x: 0x%04x 0x%04x %s\n", diff --git a/src/stm32l1.c b/src/stm32l1.c index 227f67c..86298e5 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -35,9 +35,10 @@ #include "command.h" #include "gdb_packet.h" -static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, int len); +static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, + size_t len); static int stm32l1_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + const uint8_t *src, size_t len); static const char stm32l1_driver_str[] = "STM32L1xx"; @@ -112,7 +113,7 @@ static void stm32l1_flash_unlock(ADIv5_AP_t *ap) adiv5_ap_mem_write(ap, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY2); } -static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, int len) +static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; @@ -150,7 +151,7 @@ static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, int len) } static int stm32l1_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) + const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; -- cgit v1.2.3 From 2e785e56fa4e77549878eac88f2c4891af043e64 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 14 Mar 2015 18:03:04 -0700 Subject: adiv5: Encode APnDP into register definition. Clean up magic numbers in adiv5 calls. Removed old adiv5_dp_write_ap and adiv5_dp_read_ap.--- src/adiv5.c | 90 +++++++++++++++++++---------------------------------- src/adiv5_jtagdp.c | 31 +++++++++--------- src/adiv5_swdp.c | 28 +++++++++++------ src/cortexm.c | 35 ++++++++++++--------- src/include/adiv5.h | 57 +++++++++++++++++---------------- src/lmi.c | 11 ++++--- src/samd.c | 4 +-- 7 files changed, 123 insertions(+), 133 deletions(-) (limited to 'src/lmi.c') diff --git a/src/adiv5.c b/src/adiv5.c index 361cd75..aee8471 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -160,23 +160,6 @@ void adiv5_dp_init(ADIv5_DP_t *dp) adiv5_dp_unref(dp); } -void adiv5_dp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) -{ - adiv5_dp_low_access(dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, addr, value); -} - -uint32_t adiv5_dp_read_ap(ADIv5_DP_t *dp, uint8_t addr) -{ - uint32_t ret; - - adiv5_dp_low_access(dp, ADIV5_LOW_AP, ADIV5_LOW_READ, addr, 0); - ret = adiv5_dp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, - ADIV5_DP_RDBUFF, 0); - - return ret; -} - - static int ap_check_error(struct target_s *target) { @@ -194,26 +177,24 @@ ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); while(--len) { - *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); src += 4; /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); } } - *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_DP, ADIV5_LOW_READ, - ADIV5_DP_RDBUFF, 0); + *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, + ADIV5_DP_RDBUFF, 0); return 0; } @@ -229,12 +210,10 @@ ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); while(--len) { - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); @@ -242,13 +221,13 @@ ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); } } - tmp = adiv5_dp_low_access(ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); return 0; @@ -263,25 +242,23 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len) adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); while(--len) { - tmp = adiv5_dp_low_access(ap->dp, 1, 1, ADIV5_AP_DRW, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); *dest++ = (tmp >> ((src & 0x3) << 3) & 0xFF); src++; /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); } } - tmp = adiv5_dp_low_access(ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); *dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF); return 0; @@ -298,16 +275,15 @@ ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src, adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, dest); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); while(len--) { - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, *src++); dest += 4; /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { odest = dest; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } @@ -325,17 +301,16 @@ ap_mem_write_halfwords(struct target_s *target, uint32_t dest, const uint16_t *s adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, dest); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); while(len--) { uint32_t tmp = (uint32_t)*src++ << ((dest & 2) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, tmp); dest += 2; /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { odest = dest; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } @@ -350,17 +325,16 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, dest); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); while(len--) { uint32_t tmp = (uint32_t)*src++ << ((dest++ & 3) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, tmp); /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { odest = dest; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } @@ -429,19 +403,19 @@ void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value) adiv5_ap_write(ap, ADIV5_AP_DRW, v); } -void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value) +void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value) { adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, ((uint32_t)ap->apsel << 24)|(addr & 0xF0)); - adiv5_dp_write_ap(ap->dp, addr, value); + adiv5_dp_write(ap->dp, addr, value); } -uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint8_t addr) +uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr) { uint32_t ret; adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, ((uint32_t)ap->apsel << 24)|(addr & 0xF0)); - ret = adiv5_dp_read_ap(ap->dp, addr); + ret = adiv5_dp_read(ap->dp, addr); return ret; } diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index 8f62a11..eb60caa 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -36,13 +36,13 @@ #define IR_DPACC 0xA #define IR_APACC 0xB -static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value); -static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr); +static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); +static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr); static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp); -static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value); +static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value); void adiv5_jtag_dp_handler(jtag_dev_t *dev) @@ -60,35 +60,36 @@ void adiv5_jtag_dp_handler(jtag_dev_t *dev) adiv5_dp_init(dp); } -static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) +static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) { - adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, addr, value); + adiv5_jtagdp_low_access(dp, ADIV5_LOW_WRITE, addr, value); } -static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr) +static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr) { - adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, addr, 0); - return adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, + adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, addr, 0); + return adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); } static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp) { - adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, - ADIV5_DP_CTRLSTAT, 0); - return adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, + adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_CTRLSTAT, 0); + return adiv5_jtagdp_low_access(dp, ADIV5_LOW_WRITE, ADIV5_DP_CTRLSTAT, 0xF0000032) & 0x32; } -static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value) +static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value) { + bool APnDP = addr & ADIV5_APnDP; + addr &= 0xff; uint64_t request, response; uint8_t ack; request = ((uint64_t)value << 3) | ((addr >> 1) & 0x06) | (RnW?1:0); - jtag_dev_write_ir(dp->dev, APnDP?IR_APACC:IR_DPACC); + jtag_dev_write_ir(dp->dev, APnDP ? IR_APACC : IR_DPACC); int tries = 1000; do { diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index 9df362f..3e775cc 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -33,13 +33,13 @@ #define SWDP_ACK_WAIT 0x02 #define SWDP_ACK_FAULT 0x04 -static void adiv5_swdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value); -static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint8_t addr); +static void adiv5_swdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); +static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr); static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp); -static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value); +static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value); int adiv5_swdp_scan(void) @@ -78,14 +78,20 @@ int adiv5_swdp_scan(void) return target_list?1:0; } -static void adiv5_swdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) +static void adiv5_swdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) { - adiv5_swdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, addr, value); + adiv5_swdp_low_access(dp, ADIV5_LOW_WRITE, addr, value); } -static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint8_t addr) +static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr) { - return adiv5_swdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, addr, 0); + if (addr & ADIV5_APnDP) { + adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0); + return adiv5_dp_low_access(dp, ADIV5_LOW_READ, + ADIV5_DP_RDBUFF, 0); + } else { + return adiv5_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0); + } } static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp) @@ -111,9 +117,11 @@ static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp) return err; } -static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value) +static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value) { + bool APnDP = addr & ADIV5_APnDP; + addr &= 0xff; uint8_t request = 0x81; uint32_t response; uint8_t ack; diff --git a/src/cortexm.c b/src/cortexm.c index b1d3569..da48f8e 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -359,20 +359,23 @@ cortexm_regs_read(struct target_s *target, void *data) /* Map the banked data registers (0x10-0x1c) to the * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */ - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_TAR, CORTEXM_DHCSR); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR); /* Walk the regnum_cortex_m array, reading the registers it * calls out. */ adiv5_ap_write(ap, ADIV5_AP_DB(1), regnum_cortex_m[0]); /* Required to switch banks */ - *regs++ = adiv5_dp_read_ap(ap->dp, ADIV5_AP_DB(2)); + *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), regnum_cortex_m[i]); - *regs++ = adiv5_dp_read_ap(ap->dp, ADIV5_AP_DB(2)); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), + regnum_cortex_m[i]); + *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); } if (target->target_options & TOPT_FLAVOUR_V7MF) for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), regnum_cortex_mf[i]); - *regs++ = adiv5_dp_read_ap(ap->dp, ADIV5_AP_DB(2)); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(1), + regnum_cortex_mf[i]); + *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); } return 0; @@ -391,22 +394,26 @@ cortexm_regs_write(struct target_s *target, const void *data) /* Map the banked data registers (0x10-0x1c) to the * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */ - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_TAR, CORTEXM_DHCSR); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR); /* Walk the regnum_cortex_m array, writing the registers it * calls out. */ adiv5_ap_write(ap, ADIV5_AP_DB(2), *regs++); /* Required to switch banks */ - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), 0x10000 | regnum_cortex_m[0]); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), + 0x10000 | regnum_cortex_m[0]); for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(2), *regs++); - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), - 0x10000 | regnum_cortex_m[i]); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(2), *regs++); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), + 0x10000 | regnum_cortex_m[i]); } if (target->target_options & TOPT_FLAVOUR_V7MF) for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(2), *regs++); - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), - 0x10000 | regnum_cortex_mf[i]); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(2), *regs++); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(1), + 0x10000 | regnum_cortex_mf[i]); } return 0; diff --git a/src/include/adiv5.h b/src/include/adiv5.h index e0ce9cf..cfdb4e5 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -24,12 +24,16 @@ #include "jtag_scan.h" #include "target.h" +#define ADIV5_APnDP 0x100 +#define ADIV5_DP_REG(x) (x) +#define ADIV5_AP_REG(x) (ADIV5_APnDP | (x)) + /* ADIv5 DP Register addresses */ -#define ADIV5_DP_IDCODE 0x0 -#define ADIV5_DP_ABORT 0x0 -#define ADIV5_DP_CTRLSTAT 0x4 -#define ADIV5_DP_SELECT 0x8 -#define ADIV5_DP_RDBUFF 0xC +#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0) +#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0) +#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4) +#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8) +#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xC) /* AP Abort Register (ABORT) */ /* Bits 31:5 - Reserved */ @@ -63,15 +67,15 @@ /* ADIv5 MEM-AP Registers */ -#define ADIV5_AP_CSW 0x00 -#define ADIV5_AP_TAR 0x04 +#define ADIV5_AP_CSW ADIV5_AP_REG(0x00) +#define ADIV5_AP_TAR ADIV5_AP_REG(0x04) /* 0x08 - Reserved */ -#define ADIV5_AP_DRW 0x0C -#define ADIV5_AP_DB(x) (0x10 + (4*(x))) +#define ADIV5_AP_DRW ADIV5_AP_REG(0x0C) +#define ADIV5_AP_DB(x) ADIV5_AP_REG(0x10 + (4*(x))) /* 0x20:0xF0 - Reserved */ -#define ADIV5_AP_CFG 0xF4 -#define ADIV5_AP_BASE 0xF8 -#define ADIV5_AP_IDR 0xFC +#define ADIV5_AP_CFG ADIV5_AP_REG(0xF4) +#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8) +#define ADIV5_AP_IDR ADIV5_AP_REG(0xFC) /* AP Control and Status Word (CSW) */ #define ADIV5_AP_CSW_DBGSWENABLE (1u << 31) @@ -93,11 +97,9 @@ #define ADIV5_AP_CSW_SIZE_WORD (2u << 0) #define ADIV5_AP_CSW_SIZE_MASK (7u << 0) -/* Constants to make RnW and APnDP parameters more clear in code */ +/* Constants to make RnW parameters more clear in code */ #define ADIV5_LOW_WRITE 0 #define ADIV5_LOW_READ 1 -#define ADIV5_LOW_DP 0 -#define ADIV5_LOW_AP 1 /* Try to keep this somewhat absract for later adding SW-DP */ typedef struct ADIv5_DP_s { @@ -107,13 +109,13 @@ typedef struct ADIv5_DP_s { bool allow_timeout; - void (*dp_write)(struct ADIv5_DP_s *dp, uint8_t addr, uint32_t value); - uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint8_t addr); + void (*dp_write)(struct ADIv5_DP_s *dp, uint16_t addr, uint32_t value); + uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr); uint32_t (*error)(struct ADIv5_DP_s *dp); - uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value); + uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW, + uint16_t addr, uint32_t value); union { jtag_dev_t *dev; @@ -121,12 +123,12 @@ typedef struct ADIv5_DP_s { }; } ADIv5_DP_t; -static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) +static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) { dp->dp_write(dp, addr, value); } -static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint8_t addr) +static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr) { return dp->dp_read(dp, addr); } @@ -136,10 +138,10 @@ static inline uint32_t adiv5_dp_error(ADIv5_DP_t *dp) return dp->error(dp); } -static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t APnDP, - uint8_t RnW, uint8_t addr, uint32_t value) +static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW, + uint16_t addr, uint32_t value) { - return dp->low_access(dp, APnDP, RnW, addr, value); + return dp->low_access(dp, RnW, addr, value); } typedef struct ADIv5_AP_s { @@ -164,9 +166,6 @@ void adiv5_ap_ref(ADIv5_AP_t *ap); void adiv5_dp_unref(ADIv5_DP_t *dp); void adiv5_ap_unref(ADIv5_AP_t *ap); -void adiv5_dp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value); -uint32_t adiv5_dp_read_ap(ADIv5_DP_t *dp, uint8_t addr); - uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr); void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value); uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr); @@ -174,8 +173,8 @@ void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value); uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr); void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value); -void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value); -uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint8_t addr); +void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value); +uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr); void adiv5_jtag_dp_handler(jtag_dev_t *dev); int adiv5_swdp_scan(void); diff --git a/src/lmi.c b/src/lmi.c index 0f16db4..9359458 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -131,17 +131,18 @@ int lmi_flash_erase(struct target_s *target, uint32_t addr, size_t len) adiv5_ap_write(ap, 0x00, 0xA2000052); /* select Flash Control */ - adiv5_dp_low_access(ap->dp, 1, 0, 0x04, 0x400FD000); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, 0x04, 0x400FD000); while(len) { /* write address to FMA */ - adiv5_ap_write(ap, 0x10, addr); /* Required to switch banks */ + adiv5_ap_write(ap, ADIV5_AP_DB(0), addr); /* Required to switch banks */ /* set ERASE bit in FMC */ - adiv5_dp_low_access(ap->dp, 1, 0, 0x08, 0xA4420002); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(2), 0xA4420002); /* Read FMC to poll for ERASE bit */ - adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DB(2), 0); do { - tmp = adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, + ADIV5_AP_DB(2), 0); } while (tmp & 2); len -= 0x400; diff --git a/src/samd.c b/src/samd.c index 6f73956..2719763 100644 --- a/src/samd.c +++ b/src/samd.c @@ -553,7 +553,7 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, /* Partial, manual page write */ for (; addr <= MINIMUM(end, end_of_this_page); addr += 4, i++) { - adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); + adiv5_dp_write(ap->dp, ADIV5_AP_DRW, data[i]); } /* Unlock */ @@ -578,7 +578,7 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, /* Full, automatic page write */ for (; addr < page + SAMD_PAGE_SIZE; addr += 4, i++) { - adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); + adiv5_dp_write(ap->dp, ADIV5_AP_DRW, data[i]); } } -- cgit v1.2.3 From ee3af96a736139b71678a0e590865f9ffafc2f35 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 15 Mar 2015 14:31:57 -0700 Subject: Consolidate target_mem_read* and target_mem_write* methods. There are now only mem_read and mem_write, that must handle all alignments. These methods return void, errors must be checked with target_check_error.--- src/adiv5.c | 224 ++++++++++++++++++--------------------------------- src/arm7tdmi.c | 8 +- src/cortexm.c | 9 +-- src/crc32.c | 9 +-- src/gdb_main.c | 19 +---- src/include/target.h | 39 ++------- src/lmi.c | 4 +- src/lpc11xx.c | 4 +- src/lpc43xx.c | 24 +++--- src/nrf51.c | 4 +- src/sam3x.c | 4 +- src/stm32f1.c | 4 +- src/stm32f4.c | 4 +- src/stm32l0.c | 27 +++---- src/stm32l1.c | 6 +- 15 files changed, 137 insertions(+), 252 deletions(-) (limited to 'src/lmi.c') diff --git a/src/adiv5.c b/src/adiv5.c index aee8471..8f99a9d 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -1,7 +1,7 @@ /* * This file is part of the Black Magic Debug project. * - * Copyright (C) 2011 Black Sphere Technologies Ltd. + * Copyright (C) 2015 Black Sphere Technologies Ltd. * Written by Gareth McMullin * * This program is free software: you can redistribute it and/or modify @@ -39,12 +39,10 @@ static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP"; static int ap_check_error(struct target_s *target); -static int ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len); -static int ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src, int len); -static int ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int len); -static int ap_mem_write_halfwords(struct target_s *target, uint32_t dest, const uint16_t *src, int len); -static int ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len); -static int ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, int len); +static void ap_mem_read(struct target_s *target, void *dest, uint32_t src, + size_t len); +static void ap_mem_write(struct target_s *target, uint32_t dest, + const void *src, size_t len); void adiv5_dp_ref(ADIv5_DP_t *dp) { @@ -147,12 +145,8 @@ void adiv5_dp_init(ADIv5_DP_t *dp) t->driver = adiv5_driver_str; t->check_error = ap_check_error; - t->mem_read_words = ap_mem_read_words; - t->mem_write_words = ap_mem_write_words; - t->mem_read_halfwords = ap_mem_read_halfwords; - t->mem_write_halfwords = ap_mem_write_halfwords; - t->mem_read_bytes = ap_mem_read_bytes; - t->mem_write_bytes = ap_mem_write_bytes; + t->mem_read = ap_mem_read; + t->mem_write = ap_mem_write; /* The rest sould only be added after checking ROM table */ cortexm_probe(t); @@ -167,88 +161,69 @@ ap_check_error(struct target_s *target) return adiv5_dp_error(ap->dp); } -static int -ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len) +enum align { + ALIGN_BYTE = 0, + ALIGN_HALFWORD = 1, + ALIGN_WORD = 2 +}; +#define ALIGNOF(x) (((x) & 3) == 0 ? ALIGN_WORD : \ + (((x) & 1) == 0 ? ALIGN_HALFWORD : ALIGN_BYTE)) +#undef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) + +/* Program the CSW and TAR for sequencial access at a given width */ +static void ap_mem_access_setup(ADIv5_AP_t *ap, uint32_t addr, enum align align) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t osrc = src; - - len >>= 2; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - while(--len) { - *dest++ = adiv5_dp_low_access(ap->dp, - ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - src += 4; - /* Check for 10 bit address overflow */ - if ((src ^ osrc) & 0xfffffc00) { - osrc = src; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - } - + uint32_t csw = ap->csw | ADIV5_AP_CSW_ADDRINC_SINGLE; + + switch (align) { + case ALIGN_BYTE: + csw |= ADIV5_AP_CSW_SIZE_BYTE; + break; + case ALIGN_HALFWORD: + csw |= ADIV5_AP_CSW_SIZE_HALFWORD; + break; + case ALIGN_WORD: + csw |= ADIV5_AP_CSW_SIZE_WORD; + break; } - *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, - ADIV5_DP_RDBUFF, 0); - - return 0; + adiv5_ap_write(ap, ADIV5_AP_CSW, csw); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, addr); } -static int -ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int len) +/* Extract read data from data lane based on align and src address */ +static void * extract(void *dest, uint32_t src, uint32_t val, enum align align) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t tmp; - uint32_t osrc = src; - - len >>= 1; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - while(--len) { - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); - *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); - - src += 2; - /* Check for 10 bit address overflow */ - if ((src ^ osrc) & 0xfffffc00) { - osrc = src; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - } + switch (align) { + case ALIGN_BYTE: + *(uint8_t *)dest = (val >> ((src & 0x3) << 3) & 0xFF); + break; + case ALIGN_HALFWORD: + *(uint16_t *)dest = (val >> ((src & 0x2) << 3) & 0xFFFF); + break; + case ALIGN_WORD: + *(uint32_t *)dest = val; + break; } - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); - *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); - - return 0; + return (uint8_t *)dest + (1 << align); } -static int -ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len) +static void +ap_mem_read(struct target_s *target, void *dest, uint32_t src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t tmp; uint32_t osrc = src; + enum align align = MIN(ALIGNOF(src), ALIGNOF(len)); - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + len >>= align; + ap_mem_access_setup(ap, src, align); adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - while(--len) { + while (--len) { tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - *dest++ = (tmp >> ((src & 0x3) << 3) & 0xFF); + dest = extract(dest, src, tmp, align); - src++; + src += (1 << align); /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; @@ -259,77 +234,35 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len) } } tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); - *dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF); - - return 0; + extract(dest, src, tmp, align); } - -static int -ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src, int len) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t odest = dest; - - len >>= 2; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - while(len--) { - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, - ADIV5_AP_DRW, *src++); - dest += 4; - /* Check for 10 bit address overflow */ - if ((dest ^ odest) & 0xfffffc00) { - odest = dest; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - } - } - - return 0; -} - -static int -ap_mem_write_halfwords(struct target_s *target, uint32_t dest, const uint16_t *src, int len) +static void +ap_mem_write(struct target_s *target, uint32_t dest, const void *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t odest = dest; - - len >>= 1; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - while(len--) { - uint32_t tmp = (uint32_t)*src++ << ((dest & 2) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, - ADIV5_AP_DRW, tmp); - dest += 2; - /* Check for 10 bit address overflow */ - if ((dest ^ odest) & 0xfffffc00) { - odest = dest; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); + enum align align = MIN(ALIGNOF(dest), ALIGNOF(len)); + + len >>= align; + ap_mem_access_setup(ap, dest, align); + while (len--) { + uint32_t tmp = 0; + /* Pack data into correct data lane */ + switch (align) { + case ALIGN_BYTE: + tmp = ((uint32_t)*(uint8_t *)src) << ((dest & 3) << 3); + break; + case ALIGN_HALFWORD: + tmp = ((uint32_t)*(uint16_t *)src) << ((dest & 2) << 3); + break; + case ALIGN_WORD: + tmp = *(uint32_t *)src; + break; } - } - return 0; -} - -static int -ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, int len) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t odest = dest; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - while(len--) { - uint32_t tmp = (uint32_t)*src++ << ((dest++ & 3) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, - ADIV5_AP_DRW, tmp); + src = (uint8_t *)src + (1 << align); + dest += (1 << align); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, tmp); /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { @@ -338,11 +271,8 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } - return 0; } - - uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr) { adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | diff --git a/src/arm7tdmi.c b/src/arm7tdmi.c index 1721787..afd623c 100644 --- a/src/arm7tdmi.c +++ b/src/arm7tdmi.c @@ -123,12 +123,8 @@ void arm7tdmi_jtag_handler(jtag_dev_t *dev) t->attach = arm7_attach; t->detach = (void *)do_nothing; t->check_error = (void *)do_nothing; - t->mem_read_words = (void *)do_nothing; - t->mem_write_words = (void *)do_nothing; - t->mem_read_halfwords = (void *)do_nothing; - t->mem_write_halfwords = (void *)do_nothing; - t->mem_read_bytes = (void *)do_nothing; - t->mem_write_bytes = (void *)do_nothing; + t->mem_read = (void *)do_nothing; + t->mem_write = (void *)do_nothing; t->regs_size = 16 * sizeof(uint32_t); t->regs_read = (void *)arm7_regs_read; t->regs_write = (void *)arm7_regs_write; diff --git a/src/cortexm.c b/src/cortexm.c index da48f8e..fcc6a9d 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -502,7 +502,7 @@ cortexm_halt_wait(struct target_s *target) * call. */ uint32_t pc = cortexm_pc_read(target); uint16_t bkpt_instr; - target_mem_read_bytes(target, (uint8_t *)&bkpt_instr, pc, 2); + target_mem_read(target, &bkpt_instr, pc, 2); if (bkpt_instr == 0xBEAB) { int n = cortexm_hostio_request(target); if (n > 0) { @@ -571,7 +571,7 @@ static int cortexm_fault_unwind(struct target_s *target) bool fpca = !(retcode & (1<<4)); /* Read stack for pre-exception registers */ uint32_t sp = spsel ? regs[REG_PSP] : regs[REG_MSP]; - target_mem_read_words(target, stack, sp, sizeof(stack)); + target_mem_read(target, stack, sp, sizeof(stack)); if (target_check_error(target)) return 0; regs[REG_LR] = stack[5]; /* restore LR to pre-exception state */ @@ -840,7 +840,7 @@ static int cortexm_hostio_request(target *t) uint32_t params[4]; target_regs_read(t, arm_regs); - target_mem_read_words(t, params, arm_regs[1], sizeof(params)); + target_mem_read(t, params, arm_regs[1], sizeof(params)); priv->syscall = arm_regs[0]; DEBUG("syscall 0x%x (%x %x %x %x)\n", priv->syscall, @@ -860,8 +860,7 @@ static int cortexm_hostio_request(target *t) uint32_t pflag = flags[params[1] >> 1]; char filename[4]; - target_mem_read_bytes(t, (uint8_t *)filename, - params[0], sizeof(filename)); + target_mem_read(t, filename, params[0], sizeof(filename)); /* handle requests for console i/o */ if (!strcmp(filename, ":tt")) { if (pflag == FILEIO_O_RDONLY) diff --git a/src/crc32.c b/src/crc32.c index 42d1d48..fffc04c 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -100,8 +100,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) uint8_t byte; while (len--) { - if (target_mem_read_bytes(target, &byte, base, 1) != 0) - return -1; + target_mem_read(target, &byte, base, 1); crc = crc32_calc(crc, byte); base++; @@ -119,8 +118,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) CRC_CR |= CRC_CR_RESET; while (len > 3) { - if (target_mem_read_words(target, &data, base, 4) != 0) - return -1; + target_mem_read(target, &data, base, 4); CRC_DR = __builtin_bswap32(data); base += 4; @@ -130,8 +128,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) crc = CRC_DR; while (len--) { - if (target_mem_read_bytes(target, (uint8_t *)&data, base++, 1) != 0) - return -1; + target_mem_read(target, &data, base++, 1); crc ^= data << 24; for (i = 0; i < 8; i++) { diff --git a/src/gdb_main.c b/src/gdb_main.c index ab4fc8a..7bb788b 100644 --- a/src/gdb_main.c +++ b/src/gdb_main.c @@ -88,12 +88,7 @@ gdb_main(void) sscanf(pbuf, "m%" SCNx32 ",%" SCNx32, &addr, &len); DEBUG("m packet: addr = %" PRIx32 ", len = %" PRIx32 "\n", addr, len); uint8_t mem[len]; - if(((addr & 3) == 0) && ((len & 3) == 0)) - target_mem_read_words(cur_target, (void*)mem, addr, len); - else if(((addr & 1) == 0) && ((len & 1) == 0)) - target_mem_read_halfwords(cur_target, (void*)mem, addr, len); - else - target_mem_read_bytes(cur_target, (void*)mem, addr, len); + target_mem_read(cur_target, mem, addr, len); if(target_check_error(cur_target)) gdb_putpacketz("E01"); else @@ -116,12 +111,7 @@ gdb_main(void) DEBUG("M packet: addr = %" PRIx32 ", len = %" PRIx32 "\n", addr, len); uint8_t mem[len]; unhexify(mem, pbuf + hex, len); - if(((addr & 3) == 0) && ((len & 3) == 0)) - target_mem_write_words(cur_target, addr, (void*)mem, len); - else if(((addr & 1) == 0) && ((len & 1) == 0)) - target_mem_write_halfwords(cur_target, addr, (void*)mem, len); - else - target_mem_write_bytes(cur_target, addr, (void*)mem, len); + target_mem_write(cur_target, addr, mem, len); if(target_check_error(cur_target)) gdb_putpacketz("E01"); else @@ -244,10 +234,7 @@ gdb_main(void) ERROR_IF_NO_TARGET(); sscanf(pbuf, "X%" SCNx32 ",%" SCNx32 ":%n", &addr, &len, &bin); DEBUG("X packet: addr = %" PRIx32 ", len = %" PRIx32 "\n", addr, len); - if(((addr & 3) == 0) && ((len & 3) == 0)) - target_mem_write_words(cur_target, addr, (void*)pbuf+bin, len); - else - target_mem_write_bytes(cur_target, addr, (void*)pbuf+bin, len); + target_mem_write(cur_target, addr, pbuf+bin, len); if(target_check_error(cur_target)) gdb_putpacketz("E01"); else diff --git a/src/include/target.h b/src/include/target.h index 5db79a7..b48e054 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -48,24 +48,11 @@ target *target_attach(target *t, target_destroy_callback destroy_cb); (target)->check_error(target) /* Memory access functions */ -#define target_mem_read_words(target, dest, src, len) \ - (target)->mem_read_words((target), (dest), (src), (len)) - -#define target_mem_write_words(target, dest, src, len) \ - (target)->mem_write_words((target), (dest), (src), (len)) - -#define target_mem_read_halfwords(target, dest, src, len) \ - (target)->mem_read_halfwords((target), (dest), (src), (len)) - -#define target_mem_write_halfwords(target, dest, src, len) \ - (target)->mem_write_halfwords((target), (dest), (src), (len)) - -#define target_mem_read_bytes(target, dest, src, len) \ - (target)->mem_read_bytes((target), (dest), (src), (len)) - -#define target_mem_write_bytes(target, dest, src, len) \ - (target)->mem_write_bytes((target), (dest), (src), (len)) +#define target_mem_read(target, dest, src, len) \ + (target)->mem_read((target), (dest), (src), (len)) +#define target_mem_write(target, dest, src, len) \ + (target)->mem_write((target), (dest), (src), (len)) /* Register access functions */ #define target_regs_read(target, data) \ @@ -135,20 +122,10 @@ struct target_s { int (*check_error)(struct target_s *target); /* Memory access functions */ - int (*mem_read_words)(struct target_s *target, uint32_t *dest, uint32_t src, - int len); - int (*mem_write_words)(struct target_s *target, uint32_t dest, - const uint32_t *src, int len); - - int (*mem_read_halfwords)(struct target_s *target, uint16_t *dest, uint32_t src, - int len); - int (*mem_write_halfwords)(struct target_s *target, uint32_t dest, - const uint16_t *src, int len); - - int (*mem_read_bytes)(struct target_s *target, uint8_t *dest, uint32_t src, - int len); - int (*mem_write_bytes)(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + void (*mem_read)(struct target_s *target, void *dest, uint32_t src, + size_t len); + void (*mem_write)(struct target_s *target, uint32_t dest, + const void *src, size_t len); /* Register access functions */ int regs_size; diff --git a/src/lmi.c b/src/lmi.c index 9359458..8c5e143 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -159,9 +159,9 @@ int lmi_flash_write(struct target_s *target, uint32_t dest, data[1] = len >> 2; memcpy(&data[2], src, len); DEBUG("Sending stub\n"); - target_mem_write_words(target, 0x20000000, (void*)lmi_flash_write_stub, 0x30); + target_mem_write(target, 0x20000000, (void*)lmi_flash_write_stub, 0x30); DEBUG("Sending data\n"); - target_mem_write_words(target, 0x20000030, data, len + 8); + target_mem_write(target, 0x20000030, data, len + 8); DEBUG("Running stub\n"); target_pc_write(target, 0x20000000); target_halt_resume(target, 0); diff --git a/src/lpc11xx.c b/src/lpc11xx.c index b6309c2..eca3daf 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -170,7 +170,7 @@ lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned par /* fill out the remainder of the parameters and copy the structure to RAM */ param->opcodes[0] = 0xbe00; param->opcodes[1] = 0x0000; - target_mem_write_words(target, IAP_RAM_BASE, (void *)param, param_len); + target_mem_write(target, IAP_RAM_BASE, param, param_len); /* set up for the call to the IAP ROM */ target_regs_read(target, regs); @@ -191,7 +191,7 @@ lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned par while (!target_halt_wait(target)); /* copy back just the parameters structure */ - target_mem_read_words(target, (void *)param, IAP_RAM_BASE, sizeof(struct flash_param)); + target_mem_read(target, param, IAP_RAM_BASE, sizeof(struct flash_param)); } static int flash_page_size(struct target_s *target) diff --git a/src/lpc43xx.c b/src/lpc43xx.c index eca7338..0ae9418 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -224,7 +224,7 @@ static bool lpc43xx_cmd_reset(target *target, int argc, const char *argv[]) static const uint32_t reset_val = 0x05FA0004; /* System reset on target */ - target_mem_write_words(target, AIRCR, &reset_val, sizeof(reset_val)); + target_mem_write(target, AIRCR, &reset_val, sizeof(reset_val)); return true; } @@ -340,12 +340,12 @@ static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, /* Pet WDT before each IAP call, if it is on */ lpc43xx_wdt_pet(target); - target_mem_read_words(target, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry)); + target_mem_read(target, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry)); /* fill out the remainder of the parameters and copy the structure to RAM */ param->opcode = ARM_THUMB_BREAKPOINT; /* breakpoint */ param->pad0 = 0x0000; /* pad */ - target_mem_write_words(target, IAP_RAM_BASE, (void *)param, param_len); + target_mem_write(target, IAP_RAM_BASE, param, param_len); /* set up for the call to the IAP ROM */ target_regs_read(target, regs); @@ -362,7 +362,7 @@ static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, while (!target_halt_wait(target)); /* copy back just the parameters structure */ - target_mem_read_words(target, (void *)param, IAP_RAM_BASE, sizeof(struct flash_param)); + target_mem_read(target, param, IAP_RAM_BASE, sizeof(struct flash_param)); } static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len) @@ -429,7 +429,7 @@ static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t le static void lpc43xx_set_internal_clock(struct target_s *target) { const uint32_t val2 = (1 << 11) | (1 << 24); - target_mem_write_words(target, 0x40050000 + 0x06C, &val2, sizeof(val2)); + target_mem_write(target, 0x40050000 + 0x06C, &val2, sizeof(val2)); } static int lpc43xx_flash_write(struct target_s *target, @@ -477,9 +477,9 @@ static int lpc43xx_flash_write(struct target_s *target, } /* copy buffer into target memory */ - target_mem_write_words(target, + target_mem_write(target, IAP_RAM_BASE + offsetof(struct flash_program, data), - (uint32_t*)flash_pgm.data, sizeof(flash_pgm.data)); + flash_pgm.data, sizeof(flash_pgm.data)); /* set the destination address and program */ flash_pgm.p.command = IAP_CMD_PROGRAM; @@ -541,7 +541,7 @@ static void lpc43xx_wdt_set_period(struct target_s *target) { uint32_t wdt_mode = 0; /* Check if WDT is on */ - target_mem_read_words(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); + target_mem_read(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); /* If WDT on, we can't disable it, but we may be able to set a long period */ if (wdt_mode && !(wdt_mode & LPC43XX_WDT_PROTECT)) @@ -549,7 +549,7 @@ static void lpc43xx_wdt_set_period(struct target_s *target) const uint32_t wdt_period = LPC43XX_WDT_PERIOD_MAX; - target_mem_write_words(target, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period)); + target_mem_write(target, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period)); } } @@ -557,7 +557,7 @@ static void lpc43xx_wdt_pet(struct target_s *target) { uint32_t wdt_mode = 0; /* Check if WDT is on */ - target_mem_read_words(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); + target_mem_read(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); /* If WDT on, pet */ if (wdt_mode) @@ -566,7 +566,7 @@ static void lpc43xx_wdt_pet(struct target_s *target) const uint32_t feed2 = 0x55;; - target_mem_write_words(target, LPC43XX_WDT_FEED, &feed1, sizeof(feed1)); - target_mem_write_words(target, LPC43XX_WDT_FEED, &feed2, sizeof(feed2)); + target_mem_write(target, LPC43XX_WDT_FEED, &feed1, sizeof(feed1)); + target_mem_write(target, LPC43XX_WDT_FEED, &feed2, sizeof(feed2)); } } diff --git a/src/nrf51.c b/src/nrf51.c index 55c9a58..a4396bb 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -233,8 +233,8 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, return -1; /* Write stub and data to target ram and set PC */ - target_mem_write_words(target, 0x20000000, (void*)nrf51_flash_write_stub, 0x28); - target_mem_write_words(target, 0x20000028, data, len + 8); + target_mem_write(target, 0x20000000, nrf51_flash_write_stub, 0x28); + target_mem_write(target, 0x20000028, data, len + 8); target_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/sam3x.c b/src/sam3x.c index 7141cb5..211fc92 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -326,7 +326,7 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) memset(buf, 0xff, sizeof(buf)); /* Only do this once, since it doesn't change. */ - target_mem_write_words(target, addr, (void*)buf, SAM3_PAGE_SIZE); + target_mem_write(target, addr, buf, SAM3_PAGE_SIZE); while (len) { if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_EWP, chunk)) @@ -384,7 +384,7 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, src += page_size; } - target_mem_write_words(target, dest, (void*)buf, page_size); + target_mem_write(target, dest, buf, page_size); if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_WP, chunk)) return -1; } diff --git a/src/stm32f1.c b/src/stm32f1.c index 405bc1a..ca55fad 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -293,8 +293,8 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Write stub and data to target ram and set PC */ - target_mem_write_words(target, 0x20000000, (void*)stm32f1_flash_write_stub, 0x2C); - target_mem_write_words(target, 0x2000002C, data, sizeof(data)); + target_mem_write(target, 0x20000000, stm32f1_flash_write_stub, 0x2C); + target_mem_write(target, 0x2000002C, data, sizeof(data)); target_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/stm32f4.c b/src/stm32f4.c index fac097a..58d1328 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -253,8 +253,8 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Write stub and data to target ram and set PC */ - target_mem_write_words(target, 0x20000000, (void*)stm32f4_flash_write_stub, 0x30); - target_mem_write_words(target, 0x20000030, data, sizeof(data)); + target_mem_write(target, 0x20000000, stm32f4_flash_write_stub, 0x30); + target_mem_write(target, 0x20000030, data, sizeof(data)); target_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/stm32l0.c b/src/stm32l0.c index 2e30035..028f2a1 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -380,17 +380,17 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, info.page_size = stm32lx_nvm_prog_page_size(target); /* Load the stub */ - target_mem_write_words(target, STM32Lx_STUB_PHYS, - (void*) &stm32l0_nvm_prog_erase_stub[0], - sizeof(stm32l0_nvm_prog_erase_stub)); + target_mem_write(target, STM32Lx_STUB_PHYS, + &stm32l0_nvm_prog_erase_stub[0], + sizeof(stm32l0_nvm_prog_erase_stub)); /* Setup parameters */ info.destination = addr; info.size = size; /* Copy parameters */ - target_mem_write_words(target, STM32Lx_STUB_INFO_PHYS, - (void*) &info, sizeof(info)); + target_mem_write(target, STM32Lx_STUB_INFO_PHYS, + &info, sizeof(info)); /* Execute stub */ target_pc_write(target, STM32Lx_STUB_PHYS); @@ -434,9 +434,9 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, info.page_size = page_size; /* Load the stub */ - target_mem_write_words(target, STM32Lx_STUB_PHYS, - (void*) &stm32l0_nvm_prog_write_stub[0], - sizeof(stm32l0_nvm_prog_write_stub)); + target_mem_write(target, STM32Lx_STUB_PHYS, + &stm32l0_nvm_prog_write_stub[0], + sizeof(stm32l0_nvm_prog_write_stub)); while (size > 0) { @@ -458,8 +458,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, info.size = cb; /* Copy data to write to flash */ - target_mem_write_words(target, info.source, (void*) source, - info.size); + target_mem_write(target, info.source, source, info.size); /* Move pointers early */ destination += cb; @@ -467,8 +466,8 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, size -= cb; /* Copy parameters */ - target_mem_write_words(target, STM32Lx_STUB_INFO_PHYS, - (void*) &info, sizeof(info)); + target_mem_write(target, STM32Lx_STUB_INFO_PHYS, + &info, sizeof(info)); /* Execute stub */ target_pc_write(target, STM32Lx_STUB_PHYS); @@ -661,7 +660,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, c = size; size -= c; - target_mem_write_words(target, destination, source, c); + target_mem_write(target, destination, source, c); source += c/4; destination += c; } @@ -673,7 +672,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, size_t c = size & ~(half_page_size - 1); size -= c; - target_mem_write_words(target, destination, source, c); + target_mem_write(target, destination, source, c); source += c/4; destination += c; } diff --git a/src/stm32l1.c b/src/stm32l1.c index 86298e5..c72cccd 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -176,7 +176,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, if(xlen > len) xlen = len & ~3; - target_mem_write_words(target, dest, (uint32_t*)src, xlen); + target_mem_write(target, dest, src, xlen); src += xlen; dest += xlen; len -= xlen; @@ -192,7 +192,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, if(target_check_error(target)) return -1; - target_mem_write_words(target, dest, (uint32_t*)src, len & ~127); + target_mem_write(target, dest, src, len & ~127); src += len & ~127; dest += len & ~127; len -= len & ~127; @@ -208,7 +208,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, /* Handle non-full page at the end */ if(len >= 4) { - target_mem_write_words(target, dest, (uint32_t*)src, len & ~3); + target_mem_write(target, dest, src, len & ~3); src += len & ~3; dest += len & ~3; len -= len & ~3; -- cgit v1.2.3 From 2bf54f9a72bd9ee57e668f09075b65486e418216 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 15 Mar 2015 16:02:09 -0700 Subject: Replace adiv5_ap_mem* functions with inline wrappers to target mem*. --- src/adiv5.c | 60 ---------------------- src/cortexm.c | 100 ++++++++++++++++++------------------- src/crc32.c | 6 +-- src/include/adiv5.h | 7 --- src/include/target.h | 38 +++++++++++++- src/kinetis.c | 15 +++--- src/lmi.c | 2 +- src/lpc11xx.c | 2 +- src/lpc43xx.c | 4 +- src/nrf51.c | 60 ++++++++-------------- src/sam3x.c | 49 ++++++++---------- src/samd.c | 134 +++++++++++++++++++++---------------------------- src/stm32f1.c | 73 ++++++++++++--------------- src/stm32f4.c | 56 +++++++++------------ src/stm32l0.c | 138 ++++++++++++++++++++++++--------------------------- src/stm32l1.c | 40 +++++++-------- 16 files changed, 336 insertions(+), 448 deletions(-) (limited to 'src/lmi.c') diff --git a/src/adiv5.c b/src/adiv5.c index 8f99a9d..2179ca6 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -273,66 +273,6 @@ ap_mem_write(struct target_s *target, uint32_t dest, const void *src, size_t len } } -uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - return adiv5_ap_read(ap, ADIV5_AP_DRW); -} - -void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_ap_write(ap, ADIV5_AP_DRW, value); -} - -uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - uint32_t v = adiv5_ap_read(ap, ADIV5_AP_DRW); - if (addr & 2) - return v >> 16; - else - return v & 0xFFFF; -} - -void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value) -{ - uint32_t v = value; - if (addr & 2) - v <<= 16; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_ap_write(ap, ADIV5_AP_DRW, v); -} - -uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - uint32_t v = adiv5_ap_read(ap, ADIV5_AP_DRW); - - return v >> ((addr & 3) * 8); -} - -void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value) -{ - uint32_t v = value << ((addr & 3) * 8); - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_ap_write(ap, ADIV5_AP_DRW, v); -} - void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value) { adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, diff --git a/src/cortexm.c b/src/cortexm.c index fcc6a9d..4bfb4d9 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -228,16 +228,16 @@ cortexm_probe(struct target_s *target) target_add_commands(target, cortexm_cmd_list, cortexm_driver_str); /* Probe for FP extension */ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t cpacr = adiv5_ap_mem_read(ap, CORTEXM_CPACR); + uint32_t cpacr = target_mem_read32(target, CORTEXM_CPACR); cpacr |= 0x00F00000; /* CP10 = 0b11, CP11 = 0b11 */ - adiv5_ap_mem_write(ap, CORTEXM_CPACR, cpacr); - if (adiv5_ap_mem_read(ap, CORTEXM_CPACR) == cpacr) { + target_mem_write32(target, CORTEXM_CPACR, cpacr); + if (target_mem_read32(target, CORTEXM_CPACR) == cpacr) { target->target_options |= TOPT_FLAVOUR_V7MF; target->regs_size += sizeof(regnum_cortex_mf); target->tdesc = tdesc_cortex_mf; } + ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = calloc(1, sizeof(*priv)); ap->priv = priv; ap->priv_free = free; @@ -284,35 +284,35 @@ bool cortexm_attach(struct target_s *target) return false; /* Request halt on reset */ - adiv5_ap_mem_write(ap, CORTEXM_DEMCR, priv->demcr); + target_mem_write32(target, CORTEXM_DEMCR, priv->demcr); /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); /* size the break/watchpoint units */ priv->hw_breakpoint_max = CORTEXM_MAX_BREAKPOINTS; - r = adiv5_ap_mem_read(ap, CORTEXM_FPB_CTRL); + r = target_mem_read32(target, CORTEXM_FPB_CTRL); if (((r >> 4) & 0xf) < priv->hw_breakpoint_max) /* only look at NUM_COMP1 */ priv->hw_breakpoint_max = (r >> 4) & 0xf; priv->hw_watchpoint_max = CORTEXM_MAX_WATCHPOINTS; - r = adiv5_ap_mem_read(ap, CORTEXM_DWT_CTRL); + r = target_mem_read32(target, CORTEXM_DWT_CTRL); if ((r >> 28) > priv->hw_watchpoint_max) priv->hw_watchpoint_max = r >> 28; /* Clear any stale breakpoints */ for(i = 0; i < priv->hw_breakpoint_max; i++) { - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); + target_mem_write32(target, CORTEXM_FPB_COMP(i), 0); priv->hw_breakpoint[i] = 0; } /* Clear any stale watchpoints */ for(i = 0; i < priv->hw_watchpoint_max; i++) { - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0); priv->hw_watchpoint[i].type = 0; } /* Flash Patch Control Register: set ENABLE */ - adiv5_ap_mem_write(ap, CORTEXM_FPB_CTRL, + target_mem_write32(target, CORTEXM_FPB_CTRL, CORTEXM_FPB_CTRL_KEY | CORTEXM_FPB_CTRL_ENABLE); target->set_hw_bp = cortexm_set_hw_bp; target->clear_hw_bp = cortexm_clear_hw_bp; @@ -336,14 +336,14 @@ void cortexm_detach(struct target_s *target) /* Clear any stale breakpoints */ for(i = 0; i < priv->hw_breakpoint_max; i++) - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); + target_mem_write32(target, CORTEXM_FPB_COMP(i), 0); /* Clear any stale watchpoints */ for(i = 0; i < priv->hw_watchpoint_max; i++) - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0); /* Disable debug */ - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); + target_mem_write32(target, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); } static int @@ -422,10 +422,8 @@ cortexm_regs_write(struct target_s *target, const void *data) static uint32_t cortexm_pc_read(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - adiv5_ap_mem_write(ap, CORTEXM_DCRSR, 0x0F); - return adiv5_ap_mem_read(ap, CORTEXM_DCRDR); + target_mem_write32(target, CORTEXM_DCRSR, 0x0F); + return target_mem_read32(target, CORTEXM_DCRDR); return 0; } @@ -433,10 +431,8 @@ cortexm_pc_read(struct target_s *target) static int cortexm_pc_write(struct target_s *target, const uint32_t val) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - adiv5_ap_mem_write(ap, CORTEXM_DCRDR, val); - adiv5_ap_mem_write(ap, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); + target_mem_write32(target, CORTEXM_DCRDR, val); + target_mem_write32(target, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); return 0; } @@ -446,26 +442,24 @@ cortexm_pc_write(struct target_s *target, const uint32_t val) static void cortexm_reset(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - jtagtap_srst(true); jtagtap_srst(false); /* Read DHCSR here to clear S_RESET_ST bit before reset */ - adiv5_ap_mem_read(ap, CORTEXM_DHCSR); + target_mem_read32(target, CORTEXM_DHCSR); /* Request system reset from NVIC: SRST doesn't work correctly */ /* This could be VECTRESET: 0x05FA0001 (reset only core) * or SYSRESETREQ: 0x05FA0004 (system reset) */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, - CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); + target_mem_write32(target, CORTEXM_AIRCR, + CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); /* Poll for release from reset */ - while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); + while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); } static void @@ -474,8 +468,9 @@ cortexm_halt_request(struct target_s *target) ADIv5_AP_t *ap = adiv5_target_ap(target); ap->dp->allow_timeout = false; - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, - CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN); + target_mem_write32(target, CORTEXM_DHCSR, + CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | + CORTEXM_DHCSR_C_DEBUGEN); } static int @@ -483,14 +478,14 @@ cortexm_halt_wait(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = ap->priv; - if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) + if (!(target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) return 0; ap->dp->allow_timeout = false; /* We've halted. Let's find out why. */ - uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR); - adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */ + uint32_t dfsr = target_mem_read32(target, CORTEXM_DFSR); + target_mem_write32(target, CORTEXM_DFSR, dfsr); /* write back to reset */ if ((dfsr & CORTEXM_DFSR_VCATCH) && cortexm_fault_unwind(target)) return SIGSEGV; @@ -502,7 +497,7 @@ cortexm_halt_wait(struct target_s *target) * call. */ uint32_t pc = cortexm_pc_read(target); uint16_t bkpt_instr; - target_mem_read(target, &bkpt_instr, pc, 2); + bkpt_instr = target_mem_read16(target, pc); if (bkpt_instr == 0xBEAB) { int n = cortexm_hostio_request(target); if (n > 0) { @@ -535,27 +530,26 @@ void cortexm_halt_resume(struct target_s *target, bool step) /* Disable interrupts while single stepping... */ if(step != priv->stepping) { - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT); + target_mem_write32(target, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT); priv->stepping = step; } if (priv->on_bkpt) { uint32_t pc = cortexm_pc_read(target); - if ((adiv5_ap_mem_read_halfword(ap, pc) & 0xFF00) == 0xBE00) + if ((target_mem_read16(target, pc) & 0xFF00) == 0xBE00) cortexm_pc_write(target, pc + 2); } - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr); + target_mem_write32(target, CORTEXM_DHCSR, dhcsr); ap->dp->allow_timeout = true; } static int cortexm_fault_unwind(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t hfsr = adiv5_ap_mem_read(ap, CORTEXM_HFSR); - uint32_t cfsr = adiv5_ap_mem_read(ap, CORTEXM_CFSR); - adiv5_ap_mem_write(ap, CORTEXM_HFSR, hfsr);/* write back to reset */ - adiv5_ap_mem_write(ap, CORTEXM_CFSR, cfsr);/* write back to reset */ + uint32_t hfsr = target_mem_read32(target, CORTEXM_HFSR); + uint32_t cfsr = target_mem_read32(target, CORTEXM_CFSR); + target_mem_write32(target, CORTEXM_HFSR, hfsr);/* write back to reset */ + target_mem_write32(target, CORTEXM_CFSR, cfsr);/* write back to reset */ /* We check for FORCED in the HardFault Status Register or * for a configurable fault to avoid catching core resets */ if((hfsr & CORTEXM_HFSR_FORCED) || cfsr) { @@ -598,7 +592,7 @@ static int cortexm_fault_unwind(struct target_s *target) /* Reset exception state to allow resuming from restored * state. */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, + target_mem_write32(target, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_VECTCLRACTIVE); /* Write pre-exception registers back to core */ @@ -630,7 +624,7 @@ cortexm_set_hw_bp(struct target_s *target, uint32_t addr) priv->hw_breakpoint[i] = addr | 1; - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), val); + target_mem_write32(target, CORTEXM_FPB_COMP(i), val); return 0; } @@ -649,7 +643,7 @@ cortexm_clear_hw_bp(struct target_s *target, uint32_t addr) priv->hw_breakpoint[i] = 0; - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); + target_mem_write32(target, CORTEXM_FPB_COMP(i), 0); return 0; } @@ -683,7 +677,7 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t for(i = 0; i < priv->hw_watchpoint_max; i++) if((priv->hw_watchpoint[i].type == 0) && - ((adiv5_ap_mem_read(ap, CORTEXM_DWT_FUNC(i)) & 0xF) == 0)) + ((target_mem_read32(target, CORTEXM_DWT_FUNC(i)) & 0xF) == 0)) break; if(i == priv->hw_watchpoint_max) return -2; @@ -692,9 +686,9 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t priv->hw_watchpoint[i].addr = addr; priv->hw_watchpoint[i].size = len; - adiv5_ap_mem_write(ap, CORTEXM_DWT_COMP(i), addr); - adiv5_ap_mem_write(ap, CORTEXM_DWT_MASK(i), len); - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), type | + target_mem_write32(target, CORTEXM_DWT_COMP(i), addr); + target_mem_write32(target, CORTEXM_DWT_MASK(i), len); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), type | ((target->target_options & TOPT_FLAVOUR_V6M) ? 0: CORTEXM_DWT_FUNC_DATAVSIZE_WORD)); return 0; @@ -732,7 +726,7 @@ cortexm_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_ priv->hw_watchpoint[i].type = 0; - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0); return 0; } @@ -747,7 +741,7 @@ cortexm_check_hw_wp(struct target_s *target, uint32_t *addr) for(i = 0; i < priv->hw_watchpoint_max; i++) /* if SET and MATCHED then break */ if(priv->hw_watchpoint[i].type && - (adiv5_ap_mem_read(ap, CORTEXM_DWT_FUNC(i)) & + (target_mem_read32(target, CORTEXM_DWT_FUNC(i)) & CORTEXM_DWT_FUNC_MATCHED)) break; @@ -781,7 +775,7 @@ static bool cortexm_vector_catch(target *t, int argc, char *argv[]) else priv->demcr &= ~tmp; - adiv5_ap_mem_write(ap, CORTEXM_DEMCR, priv->demcr); + target_mem_write32(t, CORTEXM_DEMCR, priv->demcr); } gdb_out("Catching vectors: "); diff --git a/src/crc32.c b/src/crc32.c index fffc04c..e8a046d 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -100,7 +100,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) uint8_t byte; while (len--) { - target_mem_read(target, &byte, base, 1); + byte = target_mem_read8(target, base); crc = crc32_calc(crc, byte); base++; @@ -118,7 +118,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) CRC_CR |= CRC_CR_RESET; while (len > 3) { - target_mem_read(target, &data, base, 4); + data = target_mem_read32(target, base); CRC_DR = __builtin_bswap32(data); base += 4; @@ -128,7 +128,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) crc = CRC_DR; while (len--) { - target_mem_read(target, &data, base++, 1); + data = target_mem_read8(target, base++); crc ^= data << 24; for (i = 0; i < 8; i++) { diff --git a/src/include/adiv5.h b/src/include/adiv5.h index cfdb4e5..4bc3905 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -166,13 +166,6 @@ void adiv5_ap_ref(ADIv5_AP_t *ap); void adiv5_dp_unref(ADIv5_DP_t *dp); void adiv5_ap_unref(ADIv5_AP_t *ap); -uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr); -void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value); -uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr); -void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value); -uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr); -void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value); - void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value); uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr); diff --git a/src/include/target.h b/src/include/target.h index b48e054..b6ea67d 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -111,7 +111,6 @@ target *target_attach(target *t, target_destroy_callback destroy_cb); #define target_hostio_reply(target, recode, errcode) \ (target)->hostio_reply((target), (retcode), (errcode)) - struct target_s { /* Notify controlling debugger if target is lost */ target_destroy_callback destroy_callback; @@ -187,6 +186,43 @@ target *target_new(unsigned size); void target_list_free(void); void target_add_commands(target *t, const struct command_s *cmds, const char *name); +static inline uint32_t target_mem_read32(target *t, uint32_t addr) +{ + uint32_t ret; + target_mem_read(t, &ret, addr, sizeof(ret)); + return ret; +} + +static inline void target_mem_write32(target *t, uint32_t addr, uint32_t value) +{ + target_mem_write(t, addr, &value, sizeof(value)); +} + +static inline uint16_t target_mem_read16(target *t, uint32_t addr) +{ + uint16_t ret; + target_mem_read(t, &ret, addr, sizeof(ret)); + return ret; +} + +static inline void target_mem_write16(target *t, uint32_t addr, uint16_t value) +{ + target_mem_write(t, addr, &value, sizeof(value)); +} + +static inline uint8_t target_mem_read8(target *t, uint32_t addr) +{ + uint8_t ret; + target_mem_read(t, &ret, addr, sizeof(ret)); + return ret; +} + +static inline void target_mem_write8(target *t, uint32_t addr, uint8_t value) +{ + target_mem_write(t, addr, &value, sizeof(value)); +} + + /* Probe for various targets. * Actual functions implemented in their respective drivers. */ diff --git a/src/kinetis.c b/src/kinetis.c index b260d2a..9f27d9b 100644 --- a/src/kinetis.c +++ b/src/kinetis.c @@ -72,7 +72,7 @@ static const char kl25_xml_memory_map[] = "" bool kinetis_probe(struct target_s *t) { - uint32_t sdid = adiv5_ap_mem_read(adiv5_target_ap(t), SIM_SDID); + uint32_t sdid = target_mem_read32(t, SIM_SDID); switch (sdid >> 20) { case 0x251: t->driver = "KL25"; @@ -87,12 +87,11 @@ bool kinetis_probe(struct target_s *t) static bool kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[8]) { - ADIv5_AP_t *ap = adiv5_target_ap(t); uint8_t fstat; /* Wait for CCIF to be high */ do { - fstat = adiv5_ap_mem_read_byte(ap, FTFA_FSTAT); + fstat = target_mem_read8(t, FTFA_FSTAT); /* Check ACCERR and FPVIOL are zero in FSTAT */ if (fstat & (FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL)) return false; @@ -101,18 +100,18 @@ kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[ /* Write command to FCCOB */ addr &= 0xffffff; addr |= (uint32_t)cmd << 24; - adiv5_ap_mem_write(ap, FTFA_FCCOB(0), addr); + target_mem_write32(t, FTFA_FCCOB(0), addr); if (data) { - adiv5_ap_mem_write(ap, FTFA_FCCOB(4), *(uint32_t*)&data[0]); - adiv5_ap_mem_write(ap, FTFA_FCCOB(8), *(uint32_t*)&data[4]); + target_mem_write32(t, FTFA_FCCOB(4), *(uint32_t*)&data[0]); + target_mem_write32(t, FTFA_FCCOB(8), *(uint32_t*)&data[4]); } /* Enable execution by clearing CCIF */ - adiv5_ap_mem_write_byte(ap, FTFA_FSTAT, FTFA_FSTAT_CCIF); + target_mem_write8(t, FTFA_FSTAT, FTFA_FSTAT_CCIF); /* Wait for execution to complete */ do { - fstat = adiv5_ap_mem_read_byte(ap, FTFA_FSTAT); + fstat = target_mem_read8(t, FTFA_FSTAT); /* Check ACCERR and FPVIOL are zero in FSTAT */ if (fstat & (FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL)) return false; diff --git a/src/lmi.c b/src/lmi.c index 8c5e143..d9aa613 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -100,7 +100,7 @@ static const uint16_t lmi_flash_write_stub[] = { bool lmi_probe(struct target_s *target) { - uint32_t did1 = adiv5_ap_mem_read(adiv5_target_ap(target), 0x400FE004); + uint32_t did1 = target_mem_read32(target, 0x400FE004); switch (did1 >> 16) { case 0x1049: /* LM3S3748 */ target->driver = lmi_driver_str; diff --git a/src/lpc11xx.c b/src/lpc11xx.c index eca3daf..6224464 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -108,7 +108,7 @@ lpc11xx_probe(struct target_s *target) uint32_t idcode; /* read the device ID register */ - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), 0x400483F4); + idcode = target_mem_read32(target, 0x400483F4); switch (idcode) { diff --git a/src/lpc43xx.c b/src/lpc43xx.c index 0ae9418..29e202a 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -170,8 +170,8 @@ bool lpc43xx_probe(struct target_s *target) { uint32_t chipid, cpuid; - chipid = adiv5_ap_mem_read(adiv5_target_ap(target), LPC43XX_CHIPID); - cpuid = adiv5_ap_mem_read(adiv5_target_ap(target), ARM_CPUID); + chipid = target_mem_read32(target, LPC43XX_CHIPID); + cpuid = target_mem_read32(target, ARM_CPUID); switch(chipid) { case 0x4906002B: /* Parts with on-chip flash */ diff --git a/src/nrf51.c b/src/nrf51.c index a4396bb..ed0137c 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -136,9 +136,7 @@ static const uint16_t nrf51_flash_write_stub[] = { bool nrf51_probe(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - target->idcode = adiv5_ap_mem_read(ap, NRF51_FICR_CONFIGID) & 0xFFFF; + target->idcode = target_mem_read32(target, NRF51_FICR_CONFIGID) & 0xFFFF; switch (target->idcode) { case 0x001D: @@ -165,32 +163,29 @@ bool nrf51_probe(struct target_s *target) static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - - ADIv5_AP_t *ap = adiv5_target_ap(target); - addr &= ~(NRF51_PAGE_SIZE - 1); len &= ~(NRF51_PAGE_SIZE - 1); /* Enable erase */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; while (len) { if (addr == NRF51_UICR) { // Special Case /* Write to the ERASE_UICR register to erase */ - adiv5_ap_mem_write(ap, NRF51_NVMC_ERASEUICR, 0x1); + target_mem_write32(target, NRF51_NVMC_ERASEUICR, 0x1); } else { // Standard Flash Page /* Write address of first word in page to erase it */ - adiv5_ap_mem_write(ap, NRF51_NVMC_ERASEPAGE, addr); + target_mem_write32(target, NRF51_NVMC_ERASEPAGE, addr); } /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -199,10 +194,10 @@ static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) } /* Return to read-only */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -212,7 +207,6 @@ static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) static int nrf51_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; uint32_t data[2 + words]; @@ -225,10 +219,10 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Enable write */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -244,30 +238,28 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, while(!target_halt_wait(target)); /* Return to read-only */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); return 0; } static bool nrf51_cmd_erase_all(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_out("erase..\n"); /* Enable erase */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); + target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) if(target_check_error(t)) return false; /* Erase all */ - adiv5_ap_mem_write(ap, NRF51_NVMC_ERASEALL, 1); + target_mem_write32(t, NRF51_NVMC_ERASEALL, 1); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) if(target_check_error(t)) return false; @@ -276,28 +268,22 @@ static bool nrf51_cmd_erase_all(target *t) static bool nrf51_cmd_read_hwid(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t hwid = adiv5_ap_mem_read(ap, NRF51_FICR_CONFIGID) & 0xFFFF; + uint32_t hwid = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF; gdb_outf("Hardware ID: 0x%04X\n", hwid); return true; } static bool nrf51_cmd_read_fwid(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t fwid = (adiv5_ap_mem_read(ap, NRF51_FICR_CONFIGID) >> 16) & 0xFFFF; + uint32_t fwid = (target_mem_read32(t, NRF51_FICR_CONFIGID) >> 16) & 0xFFFF; gdb_outf("Firmware ID: 0x%04X\n", fwid); return true; } static bool nrf51_cmd_read_deviceid(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t deviceid_low = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEID_LOW); - uint32_t deviceid_high = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEID_HIGH); + uint32_t deviceid_low = target_mem_read32(t, NRF51_FICR_DEVICEID_LOW); + uint32_t deviceid_high = target_mem_read32(t, NRF51_FICR_DEVICEID_HIGH); gdb_outf("Device ID: 0x%08X%08X\n", deviceid_high, deviceid_low); @@ -305,11 +291,9 @@ static bool nrf51_cmd_read_deviceid(target *t) } static bool nrf51_cmd_read_deviceaddr(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t addr_type = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEADDRTYPE); - uint32_t addr_low = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEADDR_LOW); - uint32_t addr_high = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEADDR_HIGH) & 0xFFFF; + uint32_t addr_type = target_mem_read32(t, NRF51_FICR_DEVICEADDRTYPE); + uint32_t addr_low = target_mem_read32(t, NRF51_FICR_DEVICEADDR_LOW); + uint32_t addr_high = target_mem_read32(t, NRF51_FICR_DEVICEADDR_HIGH) & 0xFFFF; if ((addr_type & 1) == 0) { gdb_outf("Publicly Listed Address: 0x%04X%08X\n", addr_high, addr_low); diff --git a/src/sam3x.c b/src/sam3x.c index 211fc92..b9e59a0 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -148,9 +148,7 @@ static const char sam4s_xml_memory_map[] = "" bool sam3x_probe(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - target->idcode = adiv5_ap_mem_read(ap, SAM3X_CHIPID_CIDR); + target->idcode = target_mem_read32(target, SAM3X_CHIPID_CIDR); /* FIXME: Check for all variants with similar flash interface */ switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { @@ -165,7 +163,7 @@ bool sam3x_probe(struct target_s *target) return true; } - target->idcode = adiv5_ap_mem_read(ap, SAM3N_CHIPID_CIDR); + target->idcode = target_mem_read32(target, SAM3N_CHIPID_CIDR); switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3: @@ -177,21 +175,21 @@ bool sam3x_probe(struct target_s *target) target_add_commands(target, sam3x_cmd_list, "SAM3N"); return true; } - - target->idcode = adiv5_ap_mem_read(ap, SAM3S_CHIPID_CIDR); - switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { - case CHIPID_CIDR_ARCH_SAM3SxA | CHIPID_CIDR_EPROC_CM3: - case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3: - case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3: - target->driver = "Atmel SAM3S"; - target->xml_mem_map = sam3n_xml_memory_map; - target->flash_erase = sam3x_flash_erase; - target->flash_write = sam3x_flash_write; - target_add_commands(target, sam3x_cmd_list, "SAM3S"); - return true; - } - - target->idcode = adiv5_ap_mem_read(ap, SAM4S_CHIPID_CIDR); + + target->idcode = target_mem_read32(target, SAM3S_CHIPID_CIDR); + switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + case CHIPID_CIDR_ARCH_SAM3SxA | CHIPID_CIDR_EPROC_CM3: + case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3: + case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3: + target->driver = "Atmel SAM3S"; + target->xml_mem_map = sam3n_xml_memory_map; + target->flash_erase = sam3x_flash_erase; + target->flash_write = sam3x_flash_write; + target_add_commands(target, sam3x_cmd_list, "SAM3S"); + return true; + } + + target->idcode = target_mem_read32(target, SAM4S_CHIPID_CIDR); switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM4SxA | CHIPID_CIDR_EPROC_CM4: case CHIPID_CIDR_ARCH_SAM4SxB | CHIPID_CIDR_EPROC_CM4: @@ -210,18 +208,16 @@ bool sam3x_probe(struct target_s *target) static int sam3x_flash_cmd(struct target_s *target, uint32_t base, uint8_t cmd, uint16_t arg) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - DEBUG("%s: base = 0x%08x cmd = 0x%02X, arg = 0x%06X\n", __func__, base, cmd, arg); - adiv5_ap_mem_write(ap, EEFC_FCR(base), - EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8)); + target_mem_write32(target, EEFC_FCR(base), + EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8)); - while(!(adiv5_ap_mem_read(ap, EEFC_FSR(base)) & EEFC_FSR_FRDY)) + while (!(target_mem_read32(target, EEFC_FSR(base)) & EEFC_FSR_FRDY)) if(target_check_error(target)) return -1; - uint32_t sr = adiv5_ap_mem_read(ap, EEFC_FSR(base)); + uint32_t sr = target_mem_read32(target, EEFC_FSR(base)); return sr & EEFC_FSR_ERROR; } @@ -394,11 +390,10 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, static bool sam3x_cmd_gpnvm_get(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t base = sam3x_flash_base(t, 0, NULL); sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_GGPB, 0); - gdb_outf("GPNVM: 0x%08X\n", adiv5_ap_mem_read(ap, EEFC_FRR(base))); + gdb_outf("GPNVM: 0x%08X\n", target_mem_read32(t, EEFC_FRR(base))); return true; } diff --git a/src/samd.c b/src/samd.c index 2719763..68f5bc4 100644 --- a/src/samd.c +++ b/src/samd.c @@ -167,13 +167,12 @@ static const char samd_xml_memory_map[] = "" */ uint64_t samd_read_pid(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint64_t pid = 0; uint8_t i, j; /* Five PID registers to read LSB first */ for (i = 0, j = 0; i < 5; i++, j += 8) - pid |= (adiv5_ap_mem_read(ap, SAMD_DSU_PID(i)) & 0xFF) << j; + pid |= (target_mem_read32(target, SAMD_DSU_PID(i)) & 0xFF) << j; return pid; } @@ -182,13 +181,12 @@ uint64_t samd_read_pid(struct target_s *target) */ uint32_t samd_read_cid(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint64_t cid = 0; uint8_t i, j; /* Four CID registers to read LSB first */ for (i = 0, j = 0; i < 4; i++, j += 8) - cid |= (adiv5_ap_mem_read(ap, SAMD_DSU_CID(i)) & 0xFF) << j; + cid |= (target_mem_read32(target, SAMD_DSU_CID(i)) & 0xFF) << j; return cid; } @@ -200,8 +198,6 @@ uint32_t samd_read_cid(struct target_s *target) static void samd_reset(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - /** * SRST is not asserted here as it appears to reset the adiv5 * logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR. @@ -219,28 +215,28 @@ samd_reset(struct target_s *target) */ /* Read DHCSR here to clear S_RESET_ST bit before reset */ - adiv5_ap_mem_read(ap, CORTEXM_DHCSR); + target_mem_read32(target, CORTEXM_DHCSR); /* Request system reset from NVIC: SRST doesn't work correctly */ /* This could be VECTRESET: 0x05FA0001 (reset only core) * or SYSRESETREQ: 0x05FA0004 (system reset) */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, + target_mem_write32(target, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + target_mem_write32(target, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } /* Poll for release from reset */ - while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); + while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); /* Clear any target errors */ target_check_error(target); @@ -255,16 +251,15 @@ samd_reset(struct target_s *target) static void samd20_revB_detach(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); cortexm_detach(target); /* ---- Additional ---- */ /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, - SAMD_STATUSA_CRSTEXT); + target_mem_write32(target, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); } } @@ -277,16 +272,15 @@ samd20_revB_detach(struct target_s *target) static void samd20_revB_halt_resume(struct target_s *target, bool step) { - ADIv5_AP_t *ap = adiv5_target_ap(target); cortexm_halt_resume(target, step); /* ---- Additional ---- */ /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, - SAMD_STATUSA_CRSTEXT); + target_mem_write32(target, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); } } @@ -376,7 +370,6 @@ struct samd_descr samd_parse_device_id(uint32_t did) char variant_string[40]; bool samd_probe(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t cid = samd_read_cid(target); uint32_t pid = samd_read_pid(target); @@ -385,12 +378,13 @@ bool samd_probe(struct target_s *target) (pid & SAMD_PID_MASK) == SAMD_PID_CONST_VALUE) { /* Read the Device ID */ - uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID); + uint32_t did = target_mem_read32(target, SAMD_DSU_DID); /* If the Device ID matches */ if ((did & SAMD_DID_MASK) == SAMD_DID_CONST_VALUE) { - uint32_t ctrlstat = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT); + uint32_t ctrlstat = target_mem_read32(target, + SAMD_DSU_CTRLSTAT); struct samd_descr samd = samd_parse_device_id(did); /* Protected? */ @@ -442,11 +436,11 @@ bool samd_probe(struct target_s *target) if (!connect_assert_srst) { /* We'll have to release the target from * extended reset to make attach possible */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + target_mem_write32(target, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } } @@ -463,17 +457,15 @@ bool samd_probe(struct target_s *target) */ static void samd_lock_current_address(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - /* Issue the unlock command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK); + target_mem_write32(target, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK); } static void samd_unlock_current_address(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - /* Issue the unlock command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK); + target_mem_write32(target, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK); } /** @@ -481,23 +473,22 @@ static void samd_unlock_current_address(struct target_s *target) */ static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - addr &= ~(SAMD_ROW_SIZE - 1); len &= ~(SAMD_ROW_SIZE - 1); while (len) { /* Write address of first word in row to erase it */ /* Must be shifted right for 16-bit address, see Datasheet ยง20.8.8 Address */ - adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, addr >> 1); + target_mem_write32(target, SAMD_NVMC_ADDRESS, addr >> 1); /* Unlock */ samd_unlock_current_address(target); /* Issue the erase command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW); + target_mem_write32(target, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW); /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -518,7 +509,6 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); - /* Find the size of our 32-bit data buffer */ uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; @@ -560,11 +550,11 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, samd_unlock_current_address(target); /* Issue the write page command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, + target_mem_write32(target, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE); } else { /* Write first word to set address */ - adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++; + target_mem_write32(target, addr, data[i]); addr += 4; i++; /* Unlock */ samd_unlock_current_address(target); @@ -583,7 +573,7 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, } /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -599,18 +589,16 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, */ static bool samd_cmd_erase_all(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Clear the DSU status bits */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + target_mem_write32(t, SAMD_DSU_CTRLSTAT, (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)); /* Erase all */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE); /* Poll for DSU Ready */ uint32_t status; - while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) & + while (((status = target_mem_read32(t, SAMD_DSU_CTRLSTAT)) & (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0) if(target_check_error(t)) return false; @@ -641,20 +629,19 @@ static bool samd_cmd_erase_all(target *t) */ static bool samd_set_flashlock(target *t, uint16_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t high = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH); - uint32_t low = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW); + uint32_t high = target_mem_read32(t, SAMD_NVM_USER_ROW_HIGH); + uint32_t low = target_mem_read32(t, SAMD_NVM_USER_ROW_LOW); /* Write address of a word in the row to erase it */ /* Must be shifted right for 16-bit address, see Datasheet ยง20.8.8 Address */ - adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, SAMD_NVM_USER_ROW_LOW >> 1); + target_mem_write32(t, SAMD_NVMC_ADDRESS, SAMD_NVM_USER_ROW_LOW >> 1); /* Issue the erase command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEAUXROW); + target_mem_write32(t, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEAUXROW); /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(t)) return -1; @@ -662,12 +649,12 @@ static bool samd_set_flashlock(target *t, uint16_t value) high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000); /* Write back */ - adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_LOW, low); - adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_HIGH, high); + target_mem_write32(t, SAMD_NVM_USER_ROW_LOW, low); + target_mem_write32(t, SAMD_NVM_USER_ROW_HIGH, high); /* Issue the page write command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, - SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE); + target_mem_write32(t, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE); return true; } @@ -681,11 +668,9 @@ static bool samd_cmd_unlock_flash(target *t) } static bool samd_cmd_read_userrow(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_outf("User Row: 0x%08x%08x\n", - adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH), - adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW)); + target_mem_read32(t, SAMD_NVM_USER_ROW_HIGH), + target_mem_read32(t, SAMD_NVM_USER_ROW_LOW)); return true; } @@ -694,12 +679,10 @@ static bool samd_cmd_read_userrow(target *t) */ static bool samd_cmd_serial(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_outf("Serial Number: 0x"); for (uint32_t i = 0; i < 4; i++) { - gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD_NVM_SERIAL(i))); + gdb_outf("%08x", target_mem_read32(t, SAMD_NVM_SERIAL(i))); } gdb_outf("\n"); @@ -711,10 +694,8 @@ static bool samd_cmd_serial(target *t) */ static uint32_t samd_flash_size(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Read the Device ID */ - uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID); + uint32_t did = target_mem_read32(t, SAMD_DSU_DID); /* Mask off the device select bits */ uint8_t devsel = did & SAMD_DID_DEVSEL_MASK; @@ -727,21 +708,19 @@ static uint32_t samd_flash_size(target *t) */ static bool samd_cmd_mbist(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Write the memory parameters to the DSU */ - adiv5_ap_mem_write(ap, SAMD_DSU_ADDRESS, 0); - adiv5_ap_mem_write(ap, SAMD_DSU_LENGTH, samd_flash_size(t)); + target_mem_write32(t, SAMD_DSU_ADDRESS, 0); + target_mem_write32(t, SAMD_DSU_LENGTH, samd_flash_size(t)); /* Clear the fail bit */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_FAIL); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_FAIL); /* Write the MBIST command */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_MBIST); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_CTRL_MBIST); /* Poll for DSU Ready */ uint32_t status; - while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) & + while (((status = target_mem_read32(t, SAMD_DSU_CTRLSTAT)) & (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0) if(target_check_error(t)) return false; @@ -755,7 +734,7 @@ static bool samd_cmd_mbist(target *t) /* Test the fail bit in Status A */ if (status & SAMD_STATUSA_FAIL) { gdb_outf("MBIST Fail @ 0x%08x\n", - adiv5_ap_mem_read(ap, SAMD_DSU_ADDRESS)); + target_mem_read32(t, SAMD_DSU_ADDRESS)); } else { gdb_outf("MBIST Passed!\n"); } @@ -767,13 +746,12 @@ static bool samd_cmd_mbist(target *t) */ static bool samd_cmd_ssb(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Issue the ssb command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB); + target_mem_write32(t, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB); /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(t)) return -1; diff --git a/src/stm32f1.c b/src/stm32f1.c index ca55fad..a746d5d 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -158,8 +158,7 @@ static const uint16_t stm32f1_flash_write_stub[] = { bool stm32f1_probe(struct target_s *target) { - - target->idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE) & 0xfff; + target->idcode = target_mem_read32(target, DBGMCU_IDCODE) & 0xfff; switch(target->idcode) { case 0x410: /* Medium density */ case 0x412: /* Low denisty */ @@ -189,7 +188,7 @@ bool stm32f1_probe(struct target_s *target) return true; } - target->idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE_F0) & 0xfff; + target->idcode = target_mem_read32(target, DBGMCU_IDCODE_F0) & 0xfff; switch(target->idcode) { case 0x444: /* STM32F03 RM0091 Rev.7 */ case 0x445: /* STM32F04 RM0091 Rev.7 */ @@ -223,33 +222,32 @@ bool stm32f1_probe(struct target_s *target) return false; } -static void stm32f1_flash_unlock(ADIv5_AP_t *ap) +static void stm32f1_flash_unlock(target *t) { - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY1); - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY2); + target_mem_write32(t, FLASH_KEYR, KEY1); + target_mem_write32(t, FLASH_KEYR, KEY2); } static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, size_t len, uint32_t pagesize) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; addr &= ~(pagesize - 1); len = (len + pagesize - 1) & ~(pagesize - 1); - stm32f1_flash_unlock(ap); + stm32f1_flash_unlock(target); while(len) { /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_PER); + target_mem_write32(target, FLASH_CR, FLASH_CR_PER); /* write address to FMA */ - adiv5_ap_mem_write(ap, FLASH_AR, addr); + target_mem_write32(target, FLASH_AR, addr); /* Flash page erase start instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_PER); + target_mem_write32(target, FLASH_CR, FLASH_CR_STRT | FLASH_CR_PER); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(target, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(target)) return -1; @@ -258,7 +256,7 @@ static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, } /* Check for error */ - sr = adiv5_ap_mem_read(ap, FLASH_SR); + sr = target_mem_read32(target, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return -1; @@ -278,7 +276,6 @@ static int stm32md_flash_erase(struct target_s *target, uint32_t addr, size_t le static int stm32f1_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; if (words > 256) @@ -304,7 +301,7 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, while(!target_halt_wait(target)); /* Check for error */ - if (adiv5_ap_mem_read(ap, FLASH_SR) & SR_ERROR_MASK) + if (target_mem_read32(target, FLASH_SR) & SR_ERROR_MASK) return -1; return 0; @@ -312,21 +309,19 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, static bool stm32f1_cmd_erase_mass(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - stm32f1_flash_unlock(ap); + stm32f1_flash_unlock(t); /* Flash mass erase start instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_MER); - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; /* Check for error */ - uint16_t sr = adiv5_ap_mem_read(ap, FLASH_SR); + uint16_t sr = target_mem_read32(t, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return false; @@ -335,14 +330,12 @@ static bool stm32f1_cmd_erase_mass(target *t) static bool stm32f1_option_erase(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Erase option bytes instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_OPTER | FLASH_CR_OPTWRE); - adiv5_ap_mem_write(ap, FLASH_CR, - FLASH_CR_STRT | FLASH_CR_OPTER | FLASH_CR_OPTWRE); + target_mem_write32(t, FLASH_CR, FLASH_CR_OPTER | FLASH_CR_OPTWRE); + target_mem_write32(t, FLASH_CR, + FLASH_CR_STRT | FLASH_CR_OPTER | FLASH_CR_OPTWRE); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; return true; @@ -350,15 +343,13 @@ static bool stm32f1_option_erase(target *t) static bool stm32f1_option_write_erased(target *t, uint32_t addr, uint16_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - if (value == 0xffff) return true; /* Erase option bytes instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_OPTPG | FLASH_CR_OPTWRE); - adiv5_ap_mem_write_halfword(ap, addr, value); + target_mem_write32(t, FLASH_CR, FLASH_CR_OPTPG | FLASH_CR_OPTWRE); + target_mem_write16(t, addr, value); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; return true; @@ -366,7 +357,6 @@ static bool stm32f1_option_write_erased(target *t, uint32_t addr, uint16_t value static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); uint16_t opt_val[8]; int i, index; @@ -375,7 +365,7 @@ static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value) return false; /* Retrieve old values */ for (i = 0; i < 16; i = i +4) { - uint32_t val = adiv5_ap_mem_read(ap, FLASH_OBP_RDP + i); + uint32_t val = target_mem_read32(t, FLASH_OBP_RDP + i); opt_val[i/2] = val & 0xffff; opt_val[i/2 +1] = val >> 16; } @@ -398,7 +388,6 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) { uint32_t addr, val; uint32_t flash_obp_rdp_key; - ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t rdprt; switch(t->idcode) { @@ -409,10 +398,10 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) break; default: flash_obp_rdp_key = FLASH_OBP_RDP_KEY; } - rdprt = (adiv5_ap_mem_read(ap, FLASH_OBR) & FLASH_OBR_RDPRT); - stm32f1_flash_unlock(ap); - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, KEY1); - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, KEY2); + rdprt = target_mem_read32(t, FLASH_OBR) & FLASH_OBR_RDPRT; + stm32f1_flash_unlock(t); + target_mem_write32(t, FLASH_OPTKEYR, KEY1); + target_mem_write32(t, FLASH_OPTKEYR, KEY2); if ((argc == 2) && !strcmp(argv[1], "erase")) { stm32f1_option_erase(t); @@ -432,7 +421,7 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) if (0 && flash_obp_rdp_key == FLASH_OBP_RDP_KEY_F3) { /* Reload option bytes on F0 and F3*/ - val = adiv5_ap_mem_read(ap, FLASH_CR); + val = target_mem_read32(t, FLASH_CR); val |= FLASH_CR_OBL_LAUNCH; stm32f1_option_write(t, FLASH_CR, val); val &= ~FLASH_CR_OBL_LAUNCH; @@ -441,7 +430,7 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) for (int i = 0; i < 0xf; i += 4) { addr = 0x1ffff800 + i; - val = adiv5_ap_mem_read(ap, addr); + val = target_mem_read32(t, addr); gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF); gdb_outf("0x%08X: 0x%04X\n", addr + 2, val >> 16); } diff --git a/src/stm32f4.c b/src/stm32f4.c index 58d1328..2a8bc21 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -162,7 +162,7 @@ bool stm32f4_probe(struct target_s *target) { uint32_t idcode; - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE); + idcode = target_mem_read32(target, DBGMCU_IDCODE); switch(idcode & 0xFFF) { case 0x411: /* Documented to be 0x413! This is what I read... */ case 0x413: /* F407VGT6 */ @@ -180,25 +180,24 @@ bool stm32f4_probe(struct target_s *target) return false; } -static void stm32f4_flash_unlock(ADIv5_AP_t *ap) +static void stm32f4_flash_unlock(target *t) { - if (adiv5_ap_mem_read(ap, FLASH_CR) & FLASH_CR_LOCK) { + if (target_mem_read32(t, FLASH_CR) & FLASH_CR_LOCK) { /* Enable FPEC controller access */ - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY1); - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY2); + target_mem_write32(t, FLASH_KEYR, KEY1); + target_mem_write32(t, FLASH_KEYR, KEY2); } } static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; uint32_t cr; uint32_t pagesize; addr &= 0x07FFC000; - stm32f4_flash_unlock(ap); + stm32f4_flash_unlock(target); while(len) { if (addr < 0x10000) { /* Sector 0..3 */ @@ -215,12 +214,12 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le } cr |= FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER; /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, cr); + target_mem_write32(target, FLASH_CR, cr); /* write address to FMA */ - adiv5_ap_mem_write(ap, FLASH_CR, cr | FLASH_CR_STRT); + target_mem_write32(target, FLASH_CR, cr | FLASH_CR_STRT); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while(target_mem_read32(target, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(target)) return -1; @@ -229,7 +228,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le } /* Check for error */ - sr = adiv5_ap_mem_read(ap, FLASH_SR); + sr = target_mem_read32(target, FLASH_SR); if(sr & SR_ERROR_MASK) return -1; @@ -239,7 +238,6 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le static int stm32f4_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; uint32_t data[2 + words]; @@ -264,7 +262,7 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest, while(!target_halt_wait(target)); /* Check for error */ - sr = adiv5_ap_mem_read(ap, FLASH_SR); + sr = target_mem_read32(target, FLASH_SR); if(sr & SR_ERROR_MASK) return -1; @@ -276,17 +274,15 @@ static bool stm32f4_cmd_erase_mass(target *t) const char spinner[] = "|/-\\"; int spinindex = 0; - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_out("Erasing flash... This may take a few seconds. "); - stm32f4_flash_unlock(ap); + stm32f4_flash_unlock(t); /* Flash mass erase start instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_MER); - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) { + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) { gdb_outf("\b%c", spinner[spinindex++ % 4]); if(target_check_error(t)) { gdb_out("\n"); @@ -296,7 +292,7 @@ static bool stm32f4_cmd_erase_mass(target *t) gdb_out("\n"); /* Check for error */ - uint16_t sr = adiv5_ap_mem_read(ap, FLASH_SR); + uint16_t sr = target_mem_read32(t, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return false; @@ -305,23 +301,21 @@ static bool stm32f4_cmd_erase_mass(target *t) static bool stm32f4_option_write(target *t, uint32_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, OPTKEY1); - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, OPTKEY2); + target_mem_write32(t, FLASH_OPTKEYR, OPTKEY1); + target_mem_write32(t, FLASH_OPTKEYR, OPTKEY2); value &= ~FLASH_OPTCR_RESERVED; - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return -1; /* WRITE option bytes instruction */ - adiv5_ap_mem_write(ap, FLASH_OPTCR, value); - adiv5_ap_mem_write(ap, FLASH_OPTCR, value | FLASH_OPTCR_OPTSTRT); + target_mem_write32(t, FLASH_OPTCR, value); + target_mem_write32(t, FLASH_OPTCR, value | FLASH_OPTCR_OPTSTRT); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; - adiv5_ap_mem_write(ap, FLASH_OPTCR, value | FLASH_OPTCR_OPTLOCK); + target_mem_write32(t, FLASH_OPTCR, value | FLASH_OPTCR_OPTLOCK); return true; } @@ -329,8 +323,6 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[]) { uint32_t addr, val; - ADIv5_AP_t *ap = adiv5_target_ap(t); - if ((argc == 2) && !strcmp(argv[1], "erase")) { stm32f4_option_write(t, 0x0fffaaed); } @@ -344,7 +336,7 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[]) for (int i = 0; i < 0xf; i += 8) { addr = 0x1fffC000 + i; - val = adiv5_ap_mem_read(ap, addr); + val = target_mem_read32(t, addr); gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF); } return true; diff --git a/src/stm32l0.c b/src/stm32l0.c index 028f2a1..28088a8 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -72,13 +72,13 @@ to regain control of the target after the option byte reload. stm32l0_option_write(t, 0x1ff80000, 0xffff0000); - adiv5_ap_mem_write(ap, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); + target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); stm32l0_option_write(t, 0x1ff80000, 0xff5500aa); - adiv5_ap_mem_write(ap, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); + target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); uint32_t sr; do { - sr = adiv5_ap_mem_read(ap, STM32L0_NVM_SR); + sr = target_mem_read32(target, STM32L0_NVM_SR); } while (sr & STM32L0_NVM_SR_BSY); o Errors. We probably should clear SR errors immediately after @@ -288,7 +288,7 @@ bool stm32l0_probe(struct target_s* target) #if defined(CONFIG_STM32L1) - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), + idcode = target_mem_read32(target, STM32L1_DBGMCU_IDCODE_PHYS) & 0xfff; switch (idcode) { case 0x416: /* CAT. 1 device */ @@ -306,7 +306,7 @@ bool stm32l0_probe(struct target_s* target) } #endif - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), + idcode = target_mem_read32(target, STM32L0_DBGMCU_IDCODE_PHYS) & 0xfff; switch (idcode) { default: @@ -327,42 +327,42 @@ bool stm32l0_probe(struct target_s* target) /** Lock the NVM control registers preventing writes or erases. */ -static void stm32lx_nvm_lock(ADIv5_AP_t* ap, uint32_t nvm) +static void stm32lx_nvm_lock(target *t, uint32_t nvm) { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); } /** Unlock the NVM control registers for modifying program or data flash. Returns true if the unlock succeeds. */ -static bool stm32lx_nvm_prog_data_unlock(ADIv5_AP_t* ap, uint32_t nvm) +static bool stm32lx_nvm_prog_data_unlock(target* t, uint32_t nvm) { /* Always lock first because that's the only way to know that the unlock can succeed on the STM32L0's. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY2); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); + target_mem_write32(t, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY1); + target_mem_write32(t, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY2); - return !(adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)) + return !(target_mem_read32(t, STM32Lx_NVM_PECR(nvm)) & STM32Lx_NVM_PECR_PRGLOCK); } /** Unlock the NVM control registers for modifying option bytes. Returns true if the unlock succeeds. */ -static bool stm32lx_nvm_opt_unlock(ADIv5_AP_t* ap, uint32_t nvm) +static bool stm32lx_nvm_opt_unlock(target *t, uint32_t nvm) { /* Always lock first because that's the only way to know that the unlock can succeed on the STM32L0's. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); - adiv5_ap_mem_write(ap, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY2); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); + target_mem_write32(t, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY1); + target_mem_write32(t, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY2); - return !(adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)) + return !(target_mem_read32(t, STM32Lx_NVM_PECR(nvm)) & STM32Lx_NVM_PECR_OPTLOCK); } @@ -400,8 +400,7 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, while (!target_halt_wait(target)) ; { - ADIv5_AP_t* ap = adiv5_target_ap(target); - if (adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)) + if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_ERR_M) return -1; } @@ -477,8 +476,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, while (!target_halt_wait(target)) ; - if (adiv5_ap_mem_read(adiv5_target_ap(target), - STM32Lx_NVM_SR(nvm)) + if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_ERR_M) return -1; } @@ -557,7 +555,6 @@ static int stm32lx_nvm_write(struct target_s* target, static int stm32lx_nvm_prog_erase(struct target_s* target, uint32_t addr, size_t len) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const size_t page_size = stm32lx_nvm_prog_page_size(target); const uint32_t nvm = stm32lx_nvm_phys(target); @@ -565,15 +562,15 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, len += (addr & 3); addr &= ~3; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_PROG); { - uint32_t pecr = adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)); + uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); if ((pecr & (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) != (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) return -1; @@ -581,22 +578,22 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, /* Clear errors. Note that this only works when we wait for the NVM block to complete the last operation. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); + target_mem_write32(target, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); while (len > 0) { /* Write first word of page to 0 */ - adiv5_ap_mem_write(ap, addr, 0); + target_mem_write32(target, addr, 0); len -= page_size; addr += page_size; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) return -1; if (sr & STM32Lx_NVM_SR_BSY) @@ -618,7 +615,6 @@ static int stm32lx_nvm_prog_write(struct target_s* target, const uint8_t* source_8, size_t size) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const uint32_t nvm = stm32lx_nvm_phys(target); const bool is_stm32l1 = stm32lx_is_stm32l1(target); @@ -629,7 +625,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, if ((destination & 3) || (size & 3)) return -1; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; const size_t half_page_size = stm32lx_nvm_prog_page_size(target)/2; @@ -639,7 +635,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, /* Wait for BSY to clear because we cannot write the PECR until the previous operation completes on STM32Lxxx. */ - while (adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)) + while (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_BSY) if (target_check_error(target)) { return -1; @@ -649,7 +645,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, // than a half page to write if (size < half_page_size || (destination & (half_page_size - 1))) { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), is_stm32l1 ? 0 : STM32Lx_NVM_PECR_PROG); @@ -666,7 +662,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, } // Or we are writing a half-page(s) else { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_FPRG); @@ -679,11 +675,11 @@ static int stm32lx_nvm_prog_write(struct target_s* target, } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) { return -1; } @@ -706,7 +702,6 @@ static int stm32lx_nvm_prog_write(struct target_s* target, static int stm32lx_nvm_data_erase(struct target_s* target, uint32_t addr, size_t len) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const size_t page_size = stm32lx_nvm_data_page_size(target); const uint32_t nvm = stm32lx_nvm_phys(target); @@ -714,15 +709,15 @@ static int stm32lx_nvm_data_erase(struct target_s* target, len += (addr & 3); addr &= ~3; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; /* Flash data erase instruction */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA); { - uint32_t pecr = adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)); + uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); if ((pecr & (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) != (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) return -1; @@ -730,18 +725,18 @@ static int stm32lx_nvm_data_erase(struct target_s* target, while (len > 0) { /* Write first word of page to 0 */ - adiv5_ap_mem_write(ap, addr, 0); + target_mem_write32(target, addr, 0); len -= page_size; addr += page_size; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) return -1; if (sr & STM32Lx_NVM_SR_BSY) @@ -764,22 +759,21 @@ static int stm32lx_nvm_data_write(struct target_s* target, const uint8_t* source_8, size_t size) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const uint32_t nvm = stm32lx_nvm_phys(target); const bool is_stm32l1 = stm32lx_is_stm32l1(target); uint32_t* source = (uint32_t*) source_8; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA); while (size) { size -= 4; uint32_t v = *source++; - adiv5_ap_mem_write(ap, destination, v); + target_mem_write32(target, destination, v); destination += 4; if (target_check_error(target)) @@ -787,11 +781,11 @@ static int stm32lx_nvm_data_write(struct target_s* target, } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) return -1; if (sr & STM32Lx_NVM_SR_BSY) @@ -813,16 +807,15 @@ static int stm32lx_nvm_data_write(struct target_s* target, The return value is true if the write succeeded. */ static bool stm32lx_option_write(target *t, uint32_t address, uint32_t value) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); /* Erase and program option in one go. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_FIX); - adiv5_ap_mem_write(ap, address, value); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_FIX); + target_mem_write32(t, address, value); uint32_t sr; do { - sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); } while (sr & STM32Lx_NVM_SR_BSY); return !(sr & STM32Lx_NVM_SR_ERR_M); @@ -839,29 +832,28 @@ static bool stm32lx_option_write(target *t, uint32_t address, uint32_t value) static bool stm32lx_eeprom_write(target *t, uint32_t address, size_t cb, uint32_t value) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); const bool is_stm32l1 = stm32lx_is_stm32l1(t); /* Clear errors. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); + target_mem_write32(t, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); /* Erase and program option in one go. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), (is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA) | STM32Lx_NVM_PECR_FIX); if (cb == 4) - adiv5_ap_mem_write(ap, address, value); + target_mem_write32(t, address, value); else if (cb == 2) - adiv5_ap_mem_write_halfword(ap, address, value); + target_mem_write16(t, address, value); else if (cb == 1) - adiv5_ap_mem_write_byte(ap, address, value); + target_mem_write8(t, address, value); else return false; uint32_t sr; do { - sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); } while (sr & STM32Lx_NVM_SR_BSY); return !(sr & STM32Lx_NVM_SR_ERR_M); @@ -888,11 +880,10 @@ static bool stm32lx_cmd_stubs(target* t, static bool stm32lx_cmd_option(target* t, int argc, char** argv) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); const size_t opt_size = stm32lx_nvm_option_size(t); - if (!stm32lx_nvm_opt_unlock(ap, nvm)) { + if (!stm32lx_nvm_opt_unlock(t, nvm)) { gdb_out("unable to unlock NVM option bytes\n"); return true; } @@ -900,7 +891,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) size_t cb = strlen(argv[1]); if (argc == 2 && !strncasecmp(argv[1], "obl_launch", cb)) { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_OBL_LAUNCH); } else if (argc == 4 && !strncasecmp(argv[1], "raw", cb)) { @@ -934,7 +925,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) /* Report the current option values */ for(unsigned i = 0; i < opt_size; i += sizeof(uint32_t)) { uint32_t addr = STM32Lx_NVM_OPT_PHYS + i; - uint32_t val = adiv5_ap_mem_read(ap, addr); + uint32_t val = target_mem_read32(t, addr); gdb_outf("0x%08x: 0x%04x 0x%04x %s\n", addr, val & 0xffff, (val >> 16) & 0xffff, ((val & 0xffff) == ((~val >> 16) & 0xffff)) @@ -942,7 +933,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) } if (stm32lx_is_stm32l1(t)) { - uint32_t optr = adiv5_ap_mem_read(ap, STM32Lx_NVM_OPTR(nvm)); + uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm)); uint8_t rdprot = (optr >> STM32L1_NVM_OPTR_RDPROT_S) & STM32L1_NVM_OPTR_RDPROT_M; if (rdprot == STM32L1_NVM_OPTR_RDPROT_0) @@ -964,7 +955,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) (optr & STM32L1_NVM_OPTR_nBFB2) ? 1 : 0); } else { - uint32_t optr = adiv5_ap_mem_read(ap, STM32Lx_NVM_OPTR(nvm)); + uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm)); uint8_t rdprot = (optr >> STM32L0_NVM_OPTR_RDPROT_S) & STM32L0_NVM_OPTR_RDPROT_M; if (rdprot == STM32L0_NVM_OPTR_RDPROT_0) @@ -997,17 +988,16 @@ usage: STM32Lx_NVM_OPT_PHYS + opt_size - sizeof(uint32_t)); done: - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(t, nvm); return true; } static bool stm32lx_cmd_eeprom(target* t, int argc, char** argv) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) { + if (!stm32lx_nvm_prog_data_unlock(t, nvm)) { gdb_out("unable to unlock EEPROM\n"); return true; } @@ -1061,6 +1051,6 @@ usage: + stm32lx_nvm_eeprom_size(t)); done: - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(t, nvm); return true; } diff --git a/src/stm32l1.c b/src/stm32l1.c index c72cccd..8e63347 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -87,7 +87,7 @@ bool stm32l1_probe(struct target_s *target) { uint32_t idcode; - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), STM32L1_DBGMCU_IDCODE); + idcode = target_mem_read32(target, STM32L1_DBGMCU_IDCODE); switch(idcode & 0xFFF) { case 0x416: /* CAT. 1 device */ case 0x429: /* CAT. 2 device */ @@ -105,45 +105,44 @@ bool stm32l1_probe(struct target_s *target) return false; } -static void stm32l1_flash_unlock(ADIv5_AP_t *ap) +static void stm32l1_flash_unlock(target *t) { - adiv5_ap_mem_write(ap, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY1); - adiv5_ap_mem_write(ap, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY2); - adiv5_ap_mem_write(ap, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY1); - adiv5_ap_mem_write(ap, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY2); + target_mem_write32(t, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY1); + target_mem_write32(t, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY2); + target_mem_write32(t, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY1); + target_mem_write32(t, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY2); } static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; addr &= ~255; len &= ~255; - stm32l1_flash_unlock(ap); + stm32l1_flash_unlock(target); /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_ERASE | STM32L1_FLASH_PECR_PROG); + target_mem_write32(target, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_ERASE | STM32L1_FLASH_PECR_PROG); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) + while(target_mem_read32(target, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) if(target_check_error(target)) return -1; while(len) { /* Write first word of page to 0 */ - adiv5_ap_mem_write(ap, addr, 0); + target_mem_write32(target, addr, 0); len -= 256; addr += 256; } /* Disable programming mode */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, 0); + target_mem_write32(target, STM32L1_FLASH_PECR, 0); /* Check for error */ - sr = adiv5_ap_mem_read(ap, STM32L1_FLASH_SR); + sr = target_mem_read32(target, STM32L1_FLASH_SR); if ((sr & STM32L1_FLASH_SR_ERROR_MASK) || !(sr & STM32L1_FLASH_SR_EOP)) return -1; @@ -153,7 +152,6 @@ static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, size_t le static int stm32l1_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; /* Handle non word-aligned start */ @@ -164,7 +162,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, wlen = len; memcpy((uint8_t *)&data + (dest & 3), src, wlen); - adiv5_ap_mem_write(ap, dest & ~3, data); + target_mem_write32(target, dest & ~3, data); src += wlen; dest += wlen; len -= wlen; @@ -185,10 +183,10 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, /* Write half-pages */ if(len > 128) { /* Enable half page mode */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_FPRG | STM32L1_FLASH_PECR_PROG); + target_mem_write32(target, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_FPRG | STM32L1_FLASH_PECR_PROG); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) + while(target_mem_read32(target, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) if(target_check_error(target)) return -1; @@ -198,10 +196,10 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, len -= len & ~127; /* Disable half page mode */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, 0); + target_mem_write32(target, STM32L1_FLASH_PECR, 0); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) + while(target_mem_read32(target, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) if(target_check_error(target)) return -1; } @@ -219,11 +217,11 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, uint32_t data = 0; memcpy((uint8_t *)&data, src, len); - adiv5_ap_mem_write(ap, dest, data); + target_mem_write32(target, dest, data); } /* Check for error */ - sr = adiv5_ap_mem_read(ap, STM32L1_FLASH_SR); + sr = target_mem_read32(target, STM32L1_FLASH_SR); if ((sr & STM32L1_FLASH_SR_ERROR_MASK) || !(sr & STM32L1_FLASH_SR_EOP)) return -1; -- cgit v1.2.3 From 1e54139f4a45d379c1cda7ad02a3f4a7d321b78e Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 28 Mar 2015 20:15:33 -0700 Subject: target: Remove pc_read/pc_write methods. --- src/cortexm.c | 5 +---- src/include/cortexm.h | 1 + src/include/target.h | 9 --------- src/lmi.c | 3 ++- src/nrf51.c | 3 ++- src/stm32l0.c | 5 +++-- 6 files changed, 9 insertions(+), 17 deletions(-) (limited to 'src/lmi.c') diff --git a/src/cortexm.c b/src/cortexm.c index 4a4b5bf..0a9785f 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -62,7 +62,6 @@ const struct command_s cortexm_cmd_list[] = { static int cortexm_regs_read(target *t, void *data); static int cortexm_regs_write(target *t, const void *data); -static int cortexm_pc_write(target *t, const uint32_t val); static uint32_t cortexm_pc_read(target *t); static void cortexm_reset(target *t); @@ -218,8 +217,6 @@ bool cortexm_probe(target *t) t->tdesc = tdesc_cortex_m; t->regs_read = cortexm_regs_read; t->regs_write = cortexm_regs_write; - t->pc_write = cortexm_pc_write; - t->pc_read = cortexm_pc_read; t->reset = cortexm_reset; t->halt_request = cortexm_halt_request; @@ -428,7 +425,7 @@ static uint32_t cortexm_pc_read(target *t) return 0; } -static int cortexm_pc_write(target *t, const uint32_t val) +int cortexm_pc_write(target *t, const uint32_t val) { target_mem_write32(t, CORTEXM_DCRDR, val); target_mem_write32(t, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); diff --git a/src/include/cortexm.h b/src/include/cortexm.h index 8f4d45d..9c906a1 100644 --- a/src/include/cortexm.h +++ b/src/include/cortexm.h @@ -149,6 +149,7 @@ void cortexm_halt_resume(struct target_s *target, bool step); int cortexm_run_stub(struct target_s *target, uint32_t loadaddr, const uint16_t *stub, uint32_t stublen, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3); +int cortexm_pc_write(target *t, const uint32_t val); #endif diff --git a/src/include/target.h b/src/include/target.h index 92703b7..48e81f2 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -61,12 +61,6 @@ target *target_attach(target *t, target_destroy_callback destroy_cb); #define target_regs_write(target, data) \ (target)->regs_write((target), (data)) -#define target_pc_read(target) \ - (target)->pc_read((target)) - -#define target_pc_write(target, val) \ - (target)->pc_write((target), (val)) - /* Halt/resume functions */ #define target_reset(target) \ @@ -135,9 +129,6 @@ struct target_s { int (*regs_read)(target *t, void *data); int (*regs_write)(target *t, const void *data); - uint32_t (*pc_read)(target *t); - int (*pc_write)(target *t, const uint32_t val); - /* Halt/resume functions */ void (*reset)(target *t); void (*halt_request)(target *t); diff --git a/src/lmi.c b/src/lmi.c index d9aa613..f9fd225 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -30,6 +30,7 @@ #include "general.h" #include "adiv5.h" #include "target.h" +#include "cortexm.h" static int lmi_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int lmi_flash_write(struct target_s *target, uint32_t dest, @@ -163,7 +164,7 @@ int lmi_flash_write(struct target_s *target, uint32_t dest, DEBUG("Sending data\n"); target_mem_write(target, 0x20000030, data, len + 8); DEBUG("Running stub\n"); - target_pc_write(target, 0x20000000); + cortexm_pc_write(target, 0x20000000); target_halt_resume(target, 0); DEBUG("Waiting for halt\n"); while(!target_halt_wait(target)); diff --git a/src/nrf51.c b/src/nrf51.c index ed0137c..a75b356 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -26,6 +26,7 @@ #include "target.h" #include "command.h" #include "gdb_packet.h" +#include "cortexm.h" static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len); static int nrf51_flash_write(struct target_s *target, uint32_t dest, @@ -229,7 +230,7 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, /* Write stub and data to target ram and set PC */ target_mem_write(target, 0x20000000, nrf51_flash_write_stub, 0x28); target_mem_write(target, 0x20000028, data, len + 8); - target_pc_write(target, 0x20000000); + cortexm_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/stm32l0.c b/src/stm32l0.c index 93c5d94..6d02ad2 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -117,6 +117,7 @@ #include "target.h" #include "command.h" #include "gdb_packet.h" +#include "cortexm.h" #include "stm32lx-nvm.h" @@ -386,7 +387,7 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, &info, sizeof(info)); /* Execute stub */ - target_pc_write(target, STM32Lx_STUB_PHYS); + cortexm_pc_write(target, STM32Lx_STUB_PHYS); if (target_check_error(target)) return -1; target_halt_resume(target, 0); @@ -462,7 +463,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, &info, sizeof(info)); /* Execute stub */ - target_pc_write(target, STM32Lx_STUB_PHYS); + cortexm_pc_write(target, STM32Lx_STUB_PHYS); if (target_check_error(target)) return -1; target_halt_resume(target, 0); -- cgit v1.2.3 From 9f271d5cd7c51251ec5e90a986f6f70a3fff75d8 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 28 Mar 2015 20:47:17 -0700 Subject: Consistently use 'target *t' for target var. --- src/adiv5.c | 20 ++-- src/crc32.c | 10 +- src/include/cortexm.h | 8 +- src/include/crc32.h | 2 +- src/kinetis.c | 12 +-- src/lmi.c | 41 ++++---- src/lpc11xx.c | 78 +++++++------- src/lpc43xx.c | 135 ++++++++++++------------- src/nrf51.c | 64 ++++++------ src/sam3x.c | 104 +++++++++---------- src/samd.c | 119 +++++++++++----------- src/stm32f1.c | 98 +++++++++--------- src/stm32f4.c | 38 +++---- src/stm32l0.c | 275 +++++++++++++++++++++++--------------------------- 14 files changed, 488 insertions(+), 516 deletions(-) (limited to 'src/lmi.c') diff --git a/src/adiv5.c b/src/adiv5.c index 88aac31..039f129 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -37,12 +37,10 @@ static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP"; -static int ap_check_error(struct target_s *target); +static int ap_check_error(target *t); -static void ap_mem_read(struct target_s *target, void *dest, uint32_t src, - size_t len); -static void ap_mem_write(struct target_s *target, uint32_t dest, - const void *src, size_t len); +static void ap_mem_read(target *t, void *dest, uint32_t src, size_t len); +static void ap_mem_write(target *t, uint32_t dest, const void *src, size_t len); void adiv5_dp_ref(ADIv5_DP_t *dp) { @@ -160,9 +158,9 @@ void adiv5_dp_init(ADIv5_DP_t *dp) } static int -ap_check_error(struct target_s *target) +ap_check_error(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(target); + ADIv5_AP_t *ap = adiv5_target_ap(t); return adiv5_dp_error(ap->dp); } @@ -212,9 +210,9 @@ static void * extract(void *dest, uint32_t src, uint32_t val, enum align align) } static void -ap_mem_read(struct target_s *target, void *dest, uint32_t src, size_t len) +ap_mem_read(target *t, void *dest, uint32_t src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); + ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t tmp; uint32_t osrc = src; enum align align = MIN(ALIGNOF(src), ALIGNOF(len)); @@ -241,9 +239,9 @@ ap_mem_read(struct target_s *target, void *dest, uint32_t src, size_t len) } static void -ap_mem_write(struct target_s *target, uint32_t dest, const void *src, size_t len) +ap_mem_write(target *t, uint32_t dest, const void *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); + ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t odest = dest; enum align align = MIN(ALIGNOF(dest), ALIGNOF(len)); diff --git a/src/crc32.c b/src/crc32.c index e8a046d..6f1c0e3 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -94,13 +94,13 @@ uint32_t crc32_calc(uint32_t crc, uint8_t data) return (crc << 8) ^ crc32_table[((crc >> 24) ^ data) & 255]; } -uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) +uint32_t generic_crc32(target *t, uint32_t base, int len) { uint32_t crc = -1; uint8_t byte; while (len--) { - byte = target_mem_read8(target, base); + byte = target_mem_read8(t, base); crc = crc32_calc(crc, byte); base++; @@ -109,7 +109,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) } #else #include -uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) +uint32_t generic_crc32(target *t, uint32_t base, int len) { uint32_t data; uint32_t crc; @@ -118,7 +118,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) CRC_CR |= CRC_CR_RESET; while (len > 3) { - data = target_mem_read32(target, base); + data = target_mem_read32(t, base); CRC_DR = __builtin_bswap32(data); base += 4; @@ -128,7 +128,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) crc = CRC_DR; while (len--) { - data = target_mem_read8(target, base++); + data = target_mem_read8(t, base++); crc ^= data << 24; for (i = 0; i < 8; i++) { diff --git a/src/include/cortexm.h b/src/include/cortexm.h index 9c906a1..24e4c4d 100644 --- a/src/include/cortexm.h +++ b/src/include/cortexm.h @@ -143,10 +143,10 @@ #define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0) #define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0) -bool cortexm_attach(struct target_s *target); -void cortexm_detach(struct target_s *target); -void cortexm_halt_resume(struct target_s *target, bool step); -int cortexm_run_stub(struct target_s *target, uint32_t loadaddr, +bool cortexm_attach(target *t); +void cortexm_detach(target *t); +void cortexm_halt_resume(target *t, bool step); +int cortexm_run_stub(target *t, uint32_t loadaddr, const uint16_t *stub, uint32_t stublen, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3); int cortexm_pc_write(target *t, const uint32_t val); diff --git a/src/include/crc32.h b/src/include/crc32.h index 9966d8d..bd8d5c4 100644 --- a/src/include/crc32.h +++ b/src/include/crc32.h @@ -22,6 +22,6 @@ #define __CRC32_H uint32_t crc32_calc(uint32_t crc, uint8_t data); -uint32_t generic_crc32(struct target_s *target, uint32_t base, int len); +uint32_t generic_crc32(target *t, uint32_t base, int len); #endif diff --git a/src/kinetis.c b/src/kinetis.c index 9f27d9b..7ccb28d 100644 --- a/src/kinetis.c +++ b/src/kinetis.c @@ -54,8 +54,8 @@ #define KL25_PAGESIZE 0x400 -static int kl25_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int kl25_flash_write(struct target_s *target, uint32_t dest, +static int kl25_flash_erase(target *t, uint32_t addr, size_t len); +static int kl25_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static const char kl25_xml_memory_map[] = "" @@ -70,7 +70,7 @@ static const char kl25_xml_memory_map[] = "" " " ""; -bool kinetis_probe(struct target_s *t) +bool kinetis_probe(target *t) { uint32_t sdid = target_mem_read32(t, SIM_SDID); switch (sdid >> 20) { @@ -85,7 +85,7 @@ bool kinetis_probe(struct target_s *t) } static bool -kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[8]) +kl25_command(target *t, uint8_t cmd, uint32_t addr, const uint8_t data[8]) { uint8_t fstat; @@ -120,7 +120,7 @@ kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[ return true; } -static int kl25_flash_erase(struct target_s *t, uint32_t addr, size_t len) +static int kl25_flash_erase(target *t, uint32_t addr, size_t len) { addr &= ~(KL25_PAGESIZE - 1); len = (len + KL25_PAGESIZE - 1) & ~(KL25_PAGESIZE - 1); @@ -133,7 +133,7 @@ static int kl25_flash_erase(struct target_s *t, uint32_t addr, size_t len) return 0; } -static int kl25_flash_write(struct target_s *t, uint32_t dest, +static int kl25_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { /* FIXME handle misaligned start and end of sections */ diff --git a/src/lmi.c b/src/lmi.c index f9fd225..803a19e 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -32,8 +32,8 @@ #include "target.h" #include "cortexm.h" -static int lmi_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int lmi_flash_write(struct target_s *target, uint32_t dest, +static int lmi_flash_erase(target *t, uint32_t addr, size_t len); +static int lmi_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static const char lmi_driver_str[] = "TI Stellaris/Tiva"; @@ -99,30 +99,30 @@ static const uint16_t lmi_flash_write_stub[] = { // ... }; -bool lmi_probe(struct target_s *target) +bool lmi_probe(target *t) { - uint32_t did1 = target_mem_read32(target, 0x400FE004); + uint32_t did1 = target_mem_read32(t, 0x400FE004); switch (did1 >> 16) { case 0x1049: /* LM3S3748 */ - target->driver = lmi_driver_str; - target->xml_mem_map = lmi_xml_memory_map; - target->flash_erase = lmi_flash_erase; - target->flash_write = lmi_flash_write; + t->driver = lmi_driver_str; + t->xml_mem_map = lmi_xml_memory_map; + t->flash_erase = lmi_flash_erase; + t->flash_write = lmi_flash_write; return true; case 0x10A1: /* TM4C123GH6PM */ - target->driver = lmi_driver_str; - target->xml_mem_map = tm4c123gh6pm_xml_memory_map; - target->flash_erase = lmi_flash_erase; - target->flash_write = lmi_flash_write; + t->driver = lmi_driver_str; + t->xml_mem_map = tm4c123gh6pm_xml_memory_map; + t->flash_erase = lmi_flash_erase; + t->flash_write = lmi_flash_write; return true; } return false; } -int lmi_flash_erase(struct target_s *target, uint32_t addr, size_t len) +int lmi_flash_erase(target *t, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); + ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t tmp; addr &= 0xFFFFFC00; @@ -152,22 +152,21 @@ int lmi_flash_erase(struct target_s *target, uint32_t addr, size_t len) return 0; } -int lmi_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, size_t len) +int lmi_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { uint32_t data[(len>>2)+2]; data[0] = dest; data[1] = len >> 2; memcpy(&data[2], src, len); DEBUG("Sending stub\n"); - target_mem_write(target, 0x20000000, (void*)lmi_flash_write_stub, 0x30); + target_mem_write(t, 0x20000000, (void*)lmi_flash_write_stub, 0x30); DEBUG("Sending data\n"); - target_mem_write(target, 0x20000030, data, len + 8); + target_mem_write(t, 0x20000030, data, len + 8); DEBUG("Running stub\n"); - cortexm_pc_write(target, 0x20000000); - target_halt_resume(target, 0); + cortexm_pc_write(t, 0x20000000); + target_halt_resume(t, 0); DEBUG("Waiting for halt\n"); - while(!target_halt_wait(target)); + while(!target_halt_wait(t)); return 0; } diff --git a/src/lpc11xx.c b/src/lpc11xx.c index 6224464..3a85ded 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -61,10 +61,10 @@ static struct flash_program flash_pgm; static const char lpc8xx_driver[] = "lpc8xx"; static const char lpc11xx_driver[] = "lpc11xx"; -static void lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned param_len); -static int lpc11xx_flash_prepare(struct target_s *target, uint32_t addr, int len); -static int lpc11xx_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, +static void lpc11x_iap_call(target *t, struct flash_param *param, unsigned param_len); +static int lpc11xx_flash_prepare(target *t, uint32_t addr, int len); +static int lpc11xx_flash_erase(target *t, uint32_t addr, size_t len); +static int lpc11xx_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); /* @@ -103,12 +103,12 @@ static const char lpc8xx_xml_memory_map[] = "" ""; bool -lpc11xx_probe(struct target_s *target) +lpc11xx_probe(target *t) { uint32_t idcode; /* read the device ID register */ - idcode = target_mem_read32(target, 0x400483F4); + idcode = target_mem_read32(t, 0x400483F4); switch (idcode) { @@ -143,18 +143,18 @@ lpc11xx_probe(struct target_s *target) case 0x2972402B: /* lpc11u23/301 */ case 0x2988402B: /* lpc11u24x/301 */ case 0x2980002B: /* lpc11u24x/401 */ - target->driver = lpc11xx_driver; - target->xml_mem_map = lpc11xx_xml_memory_map; - target->flash_erase = lpc11xx_flash_erase; - target->flash_write = lpc11xx_flash_write; + t->driver = lpc11xx_driver; + t->xml_mem_map = lpc11xx_xml_memory_map; + t->flash_erase = lpc11xx_flash_erase; + t->flash_write = lpc11xx_flash_write; return true; case 0x1812202b: /* LPC812M101FDH20 */ - target->driver = lpc8xx_driver; - target->xml_mem_map = lpc8xx_xml_memory_map; - target->flash_erase = lpc11xx_flash_erase; - target->flash_write = lpc11xx_flash_write; + t->driver = lpc8xx_driver; + t->xml_mem_map = lpc8xx_xml_memory_map; + t->flash_erase = lpc11xx_flash_erase; + t->flash_write = lpc11xx_flash_write; return true; } @@ -163,55 +163,55 @@ lpc11xx_probe(struct target_s *target) } static void -lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned param_len) +lpc11x_iap_call(target *t, struct flash_param *param, unsigned param_len) { - uint32_t regs[target->regs_size / sizeof(uint32_t)]; + uint32_t regs[t->regs_size / sizeof(uint32_t)]; /* fill out the remainder of the parameters and copy the structure to RAM */ param->opcodes[0] = 0xbe00; param->opcodes[1] = 0x0000; - target_mem_write(target, IAP_RAM_BASE, param, param_len); + target_mem_write(t, IAP_RAM_BASE, param, param_len); /* set up for the call to the IAP ROM */ - target_regs_read(target, regs); + target_regs_read(t, regs); regs[0] = IAP_RAM_BASE + offsetof(struct flash_param, command); regs[1] = IAP_RAM_BASE + offsetof(struct flash_param, result); // stack pointer - top of the smallest ram less 32 for IAP usage - if (target->driver == lpc8xx_driver) + if (t->driver == lpc8xx_driver) regs[MSP] = IAP_RAM_BASE + MIN_RAM_SIZE_FOR_LPC8xx - RAM_USAGE_FOR_IAP_ROUTINES; else regs[MSP] = IAP_RAM_BASE + MIN_RAM_SIZE_FOR_LPC1xxx - RAM_USAGE_FOR_IAP_ROUTINES; regs[14] = IAP_RAM_BASE | 1; regs[15] = IAP_ENTRYPOINT; - target_regs_write(target, regs); + target_regs_write(t, regs); /* start the target and wait for it to halt again */ - target_halt_resume(target, 0); - while (!target_halt_wait(target)); + target_halt_resume(t, 0); + while (!target_halt_wait(t)); /* copy back just the parameters structure */ - target_mem_read(target, param, IAP_RAM_BASE, sizeof(struct flash_param)); + target_mem_read(t, param, IAP_RAM_BASE, sizeof(struct flash_param)); } -static int flash_page_size(struct target_s *target) +static int flash_page_size(target *t) { - if (target->driver == lpc8xx_driver) + if (t->driver == lpc8xx_driver) return 1024; else return 4096; } static int -lpc11xx_flash_prepare(struct target_s *target, uint32_t addr, int len) +lpc11xx_flash_prepare(target *t, uint32_t addr, int len) { /* prepare the sector(s) to be erased */ memset(&flash_pgm.p, 0, sizeof(flash_pgm.p)); flash_pgm.p.command[0] = IAP_CMD_PREPARE; - flash_pgm.p.command[1] = addr / flash_page_size(target); - flash_pgm.p.command[2] = (addr + len - 1) / flash_page_size(target); + flash_pgm.p.command[1] = addr / flash_page_size(t); + flash_pgm.p.command[2] = (addr + len - 1) / flash_page_size(t); - lpc11x_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } @@ -220,27 +220,27 @@ lpc11xx_flash_prepare(struct target_s *target, uint32_t addr, int len) } static int -lpc11xx_flash_erase(struct target_s *target, uint32_t addr, size_t len) +lpc11xx_flash_erase(target *t, uint32_t addr, size_t len) { - if (addr % flash_page_size(target)) + if (addr % flash_page_size(t)) return -1; /* prepare... */ - if (lpc11xx_flash_prepare(target, addr, len)) + if (lpc11xx_flash_prepare(t, addr, len)) return -1; /* and now erase them */ flash_pgm.p.command[0] = IAP_CMD_ERASE; - flash_pgm.p.command[1] = addr / flash_page_size(target); - flash_pgm.p.command[2] = (addr + len - 1) / flash_page_size(target); + flash_pgm.p.command[1] = addr / flash_page_size(t); + flash_pgm.p.command[2] = (addr + len - 1) / flash_page_size(t); flash_pgm.p.command[3] = 12000; /* XXX safe to assume this? */ - lpc11x_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } flash_pgm.p.command[0] = IAP_CMD_BLANKCHECK; - lpc11x_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } @@ -249,7 +249,7 @@ lpc11xx_flash_erase(struct target_s *target, uint32_t addr, size_t len) } static int -lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) +lpc11xx_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { unsigned first_chunk = dest / IAP_PGM_CHUNKSIZE; unsigned last_chunk = (dest + len - 1) / IAP_PGM_CHUNKSIZE; @@ -300,7 +300,7 @@ lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, } /* prepare... */ - if (lpc11xx_flash_prepare(target, chunk * IAP_PGM_CHUNKSIZE, IAP_PGM_CHUNKSIZE)) + if (lpc11xx_flash_prepare(t, chunk * IAP_PGM_CHUNKSIZE, IAP_PGM_CHUNKSIZE)) return -1; /* set the destination address and program */ @@ -310,7 +310,7 @@ lpc11xx_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, flash_pgm.p.command[3] = IAP_PGM_CHUNKSIZE; /* assuming we are running off IRC - safe lower bound */ flash_pgm.p.command[4] = 12000; /* XXX safe to presume this? */ - lpc11x_iap_call(target, &flash_pgm.p, sizeof(flash_pgm)); + lpc11x_iap_call(t, &flash_pgm.p, sizeof(flash_pgm)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } diff --git a/src/lpc43xx.c b/src/lpc43xx.c index 29e202a..1519306 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -119,20 +119,20 @@ struct flash_program { uint8_t data[IAP_PGM_CHUNKSIZE]; }; -static bool lpc43xx_cmd_erase(target *target, int argc, const char *argv[]); -static bool lpc43xx_cmd_reset(target *target, int argc, const char *argv[]); -static bool lpc43xx_cmd_mkboot(target *target, int argc, const char *argv[]); -static int lpc43xx_flash_init(struct target_s *target); -static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, +static bool lpc43xx_cmd_erase(target *t, int argc, const char *argv[]); +static bool lpc43xx_cmd_reset(target *t, int argc, const char *argv[]); +static bool lpc43xx_cmd_mkboot(target *t, int argc, const char *argv[]); +static int lpc43xx_flash_init(target *t); +static void lpc43xx_iap_call(target *t, struct flash_param *param, unsigned param_len); -static int lpc43xx_flash_prepare(struct target_s *target, +static int lpc43xx_flash_prepare(target *t, uint32_t addr, int len); -static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int lpc43xx_flash_write(struct target_s *target, +static int lpc43xx_flash_erase(target *t, uint32_t addr, size_t len); +static int lpc43xx_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); -static void lpc43xx_set_internal_clock(struct target_s *target); -static void lpc43xx_wdt_set_period(struct target_s *target); -static void lpc43xx_wdt_pet(struct target_s *target); +static void lpc43xx_set_internal_clock(target *t); +static void lpc43xx_wdt_set_period(target *t); +static void lpc43xx_wdt_pet(target *t); const struct command_s lpc43xx_cmd_list[] = { {"erase_mass", lpc43xx_cmd_erase, "Erase entire flash memory"}, @@ -166,45 +166,45 @@ static const char lpc4337_xml_memory_map[] = "" " " ""; -bool lpc43xx_probe(struct target_s *target) +bool lpc43xx_probe(target *t) { uint32_t chipid, cpuid; - chipid = target_mem_read32(target, LPC43XX_CHIPID); - cpuid = target_mem_read32(target, ARM_CPUID); + chipid = target_mem_read32(t, LPC43XX_CHIPID); + cpuid = target_mem_read32(t, ARM_CPUID); switch(chipid) { case 0x4906002B: /* Parts with on-chip flash */ switch (cpuid & 0xFF00FFF0) { case 0x4100C240: - target->driver = "LPC43xx Cortex-M4"; + t->driver = "LPC43xx Cortex-M4"; if (cpuid == 0x410FC241) { /* LPC4337 */ - target->xml_mem_map = lpc4337_xml_memory_map; - target->flash_erase = lpc43xx_flash_erase; - target->flash_write = lpc43xx_flash_write; - target_add_commands(target, lpc43xx_cmd_list, "LPC43xx"); + t->xml_mem_map = lpc4337_xml_memory_map; + t->flash_erase = lpc43xx_flash_erase; + t->flash_write = lpc43xx_flash_write; + target_add_commands(t, lpc43xx_cmd_list, "LPC43xx"); } break; case 0x4100C200: - target->driver = "LPC43xx Cortex-M0"; + t->driver = "LPC43xx Cortex-M0"; break; default: - target->driver = "LPC43xx "; + t->driver = "LPC43xx "; } return true; case 0x5906002B: /* Flashless parts */ case 0x6906002B: switch (cpuid & 0xFF00FFF0) { case 0x4100C240: - target->driver = "LPC43xx Cortex-M4"; + t->driver = "LPC43xx Cortex-M4"; break; case 0x4100C200: - target->driver = "LPC43xx Cortex-M0"; + t->driver = "LPC43xx Cortex-M0"; break; default: - target->driver = "LPC43xx "; + t->driver = "LPC43xx "; } return true; } @@ -213,7 +213,7 @@ bool lpc43xx_probe(struct target_s *target) } /* Reset all major systems _except_ debug */ -static bool lpc43xx_cmd_reset(target *target, int argc, const char *argv[]) +static bool lpc43xx_cmd_reset(target *t, int argc, const char *argv[]) { (void)argc; (void)argv; @@ -224,12 +224,12 @@ static bool lpc43xx_cmd_reset(target *target, int argc, const char *argv[]) static const uint32_t reset_val = 0x05FA0004; /* System reset on target */ - target_mem_write(target, AIRCR, &reset_val, sizeof(reset_val)); + target_mem_write(t, AIRCR, &reset_val, sizeof(reset_val)); return true; } -static bool lpc43xx_cmd_erase(target *target, int argc, const char *argv[]) +static bool lpc43xx_cmd_erase(target *t, int argc, const char *argv[]) { (void)argc; (void)argv; @@ -237,7 +237,7 @@ static bool lpc43xx_cmd_erase(target *target, int argc, const char *argv[]) uint32_t bank = 0; struct flash_program flash_pgm; - lpc43xx_flash_init(target); + lpc43xx_flash_init(t); for (bank = 0; bank < FLASH_NUM_BANK; bank++) { @@ -246,7 +246,7 @@ static bool lpc43xx_cmd_erase(target *target, int argc, const char *argv[]) flash_pgm.p.params.prepare.end_sector = FLASH_NUM_SECTOR-1; flash_pgm.p.params.prepare.flash_bank = bank; flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return false; } @@ -257,7 +257,7 @@ static bool lpc43xx_cmd_erase(target *target, int argc, const char *argv[]) flash_pgm.p.params.erase.cpu_clk_khz = CPU_CLK_KHZ; flash_pgm.p.params.erase.flash_bank = bank; flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return false; @@ -269,20 +269,20 @@ static bool lpc43xx_cmd_erase(target *target, int argc, const char *argv[]) return true; } -static int lpc43xx_flash_init(struct target_s *target) +static int lpc43xx_flash_init(target *t) { /* Deal with WDT */ - lpc43xx_wdt_set_period(target); + lpc43xx_wdt_set_period(t); /* Force internal clock */ - lpc43xx_set_internal_clock(target); + lpc43xx_set_internal_clock(t); struct flash_program flash_pgm; /* Initialize flash IAP */ flash_pgm.p.command = IAP_CMD_INIT; flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) return -1; @@ -332,40 +332,40 @@ static int32_t sector_number(uint32_t addr) } } -static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, unsigned param_len) +static void lpc43xx_iap_call(target *t, struct flash_param *param, unsigned param_len) { - uint32_t regs[target->regs_size / sizeof(uint32_t)]; + uint32_t regs[t->regs_size / sizeof(uint32_t)]; uint32_t iap_entry; /* Pet WDT before each IAP call, if it is on */ - lpc43xx_wdt_pet(target); + lpc43xx_wdt_pet(t); - target_mem_read(target, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry)); + target_mem_read(t, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry)); /* fill out the remainder of the parameters and copy the structure to RAM */ param->opcode = ARM_THUMB_BREAKPOINT; /* breakpoint */ param->pad0 = 0x0000; /* pad */ - target_mem_write(target, IAP_RAM_BASE, param, param_len); + target_mem_write(t, IAP_RAM_BASE, param, param_len); /* set up for the call to the IAP ROM */ - target_regs_read(target, regs); + target_regs_read(t, regs); regs[0] = IAP_RAM_BASE + offsetof(struct flash_param, command); regs[1] = IAP_RAM_BASE + offsetof(struct flash_param, result); regs[R_MSP] = IAP_RAM_BASE + IAP_RAM_SIZE; regs[R_LR] = IAP_RAM_BASE | 1; regs[R_PC] = iap_entry; - target_regs_write(target, regs); + target_regs_write(t, regs); /* start the target and wait for it to halt again */ - target_halt_resume(target, 0); - while (!target_halt_wait(target)); + target_halt_resume(t, 0); + while (!target_halt_wait(t)); /* copy back just the parameters structure */ - target_mem_read(target, param, IAP_RAM_BASE, sizeof(struct flash_param)); + target_mem_read(t, param, IAP_RAM_BASE, sizeof(struct flash_param)); } -static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len) +static int lpc43xx_flash_prepare(target *t, uint32_t addr, int len) { struct flash_program flash_pgm; @@ -376,7 +376,7 @@ static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len flash_pgm.p.params.prepare.flash_bank = flash_bank(addr); flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } @@ -384,7 +384,7 @@ static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len return 0; } -static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int lpc43xx_flash_erase(target *t, uint32_t addr, size_t len) { struct flash_program flash_pgm; @@ -393,11 +393,11 @@ static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t le return -1; /* init */ - if (lpc43xx_flash_init(target)) + if (lpc43xx_flash_init(t)) return -1; /* prepare... */ - if (lpc43xx_flash_prepare(target, addr, len)) + if (lpc43xx_flash_prepare(t, addr, len)) return -1; /* and now erase them */ @@ -407,7 +407,7 @@ static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t le flash_pgm.p.params.erase.cpu_clk_khz = CPU_CLK_KHZ; flash_pgm.p.params.erase.flash_bank = flash_bank(addr); flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } @@ -418,7 +418,7 @@ static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t le flash_pgm.p.params.blank_check.end_sector = sector_number(addr+len); flash_pgm.p.params.blank_check.flash_bank = flash_bank(addr); flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm.p)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm.p)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } @@ -426,13 +426,13 @@ static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t le return 0; } -static void lpc43xx_set_internal_clock(struct target_s *target) +static void lpc43xx_set_internal_clock(target *t) { const uint32_t val2 = (1 << 11) | (1 << 24); - target_mem_write(target, 0x40050000 + 0x06C, &val2, sizeof(val2)); + target_mem_write(t, 0x40050000 + 0x06C, &val2, sizeof(val2)); } -static int lpc43xx_flash_write(struct target_s *target, +static int lpc43xx_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { unsigned first_chunk = dest / IAP_PGM_CHUNKSIZE; @@ -472,12 +472,12 @@ static int lpc43xx_flash_write(struct target_s *target, } /* prepare... */ - if (lpc43xx_flash_prepare(target, chunk * IAP_PGM_CHUNKSIZE, IAP_PGM_CHUNKSIZE)) { + if (lpc43xx_flash_prepare(t, chunk * IAP_PGM_CHUNKSIZE, IAP_PGM_CHUNKSIZE)) { return -1; } /* copy buffer into target memory */ - target_mem_write(target, + target_mem_write(t, IAP_RAM_BASE + offsetof(struct flash_program, data), flash_pgm.data, sizeof(flash_pgm.data)); @@ -488,7 +488,7 @@ static int lpc43xx_flash_write(struct target_s *target, flash_pgm.p.params.program.byte_count = IAP_PGM_CHUNKSIZE; flash_pgm.p.params.program.cpu_clk_khz = CPU_CLK_KHZ; flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { return -1; } @@ -504,7 +504,7 @@ static int lpc43xx_flash_write(struct target_s *target, * This is done indepently of writing to give the user a chance to verify flash * before changing it. */ -static bool lpc43xx_cmd_mkboot(target *target, int argc, const char *argv[]) +static bool lpc43xx_cmd_mkboot(target *t, int argc, const char *argv[]) { /* Usage: mkboot 0 or mkboot 1 */ if (argc != 2) { @@ -519,7 +519,7 @@ static bool lpc43xx_cmd_mkboot(target *target, int argc, const char *argv[]) return false; } - lpc43xx_flash_init(target); + lpc43xx_flash_init(t); struct flash_program flash_pgm; /* special command to compute/write magic vector for signature */ @@ -527,7 +527,7 @@ static bool lpc43xx_cmd_mkboot(target *target, int argc, const char *argv[]) flash_pgm.p.params.make_active.flash_bank = bank; flash_pgm.p.params.make_active.cpu_clk_khz = CPU_CLK_KHZ; flash_pgm.p.result[0] = IAP_STATUS_CMD_SUCCESS; - lpc43xx_iap_call(target, &flash_pgm.p, sizeof(flash_pgm)); + lpc43xx_iap_call(t, &flash_pgm.p, sizeof(flash_pgm)); if (flash_pgm.p.result[0] != IAP_STATUS_CMD_SUCCESS) { gdb_outf("Set bootable failed.\n"); return false; @@ -537,11 +537,11 @@ static bool lpc43xx_cmd_mkboot(target *target, int argc, const char *argv[]) return true; } -static void lpc43xx_wdt_set_period(struct target_s *target) +static void lpc43xx_wdt_set_period(target *t) { uint32_t wdt_mode = 0; /* Check if WDT is on */ - target_mem_read(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); + target_mem_read(t, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); /* If WDT on, we can't disable it, but we may be able to set a long period */ if (wdt_mode && !(wdt_mode & LPC43XX_WDT_PROTECT)) @@ -549,15 +549,15 @@ static void lpc43xx_wdt_set_period(struct target_s *target) const uint32_t wdt_period = LPC43XX_WDT_PERIOD_MAX; - target_mem_write(target, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period)); + target_mem_write(t, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period)); } } -static void lpc43xx_wdt_pet(struct target_s *target) +static void lpc43xx_wdt_pet(target *t) { uint32_t wdt_mode = 0; /* Check if WDT is on */ - target_mem_read(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); + target_mem_read(t, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); /* If WDT on, pet */ if (wdt_mode) @@ -565,8 +565,7 @@ static void lpc43xx_wdt_pet(struct target_s *target) const uint32_t feed1 = 0xAA;; const uint32_t feed2 = 0x55;; - - target_mem_write(target, LPC43XX_WDT_FEED, &feed1, sizeof(feed1)); - target_mem_write(target, LPC43XX_WDT_FEED, &feed2, sizeof(feed2)); + target_mem_write(t, LPC43XX_WDT_FEED, &feed1, sizeof(feed1)); + target_mem_write(t, LPC43XX_WDT_FEED, &feed2, sizeof(feed2)); } } diff --git a/src/nrf51.c b/src/nrf51.c index a75b356..59b70f8 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -28,8 +28,8 @@ #include "gdb_packet.h" #include "cortexm.h" -static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int nrf51_flash_write(struct target_s *target, uint32_t dest, +static int nrf51_flash_erase(target *t, uint32_t addr, size_t len); +static int nrf51_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static bool nrf51_cmd_erase_all(target *t); @@ -135,11 +135,11 @@ static const uint16_t nrf51_flash_write_stub[] = { }; -bool nrf51_probe(struct target_s *target) +bool nrf51_probe(target *t) { - target->idcode = target_mem_read32(target, NRF51_FICR_CONFIGID) & 0xFFFF; + t->idcode = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF; - switch (target->idcode) { + switch (t->idcode) { case 0x001D: case 0x002A: case 0x0044: @@ -151,43 +151,43 @@ bool nrf51_probe(struct target_s *target) case 0x004D: case 0x0026: case 0x004C: - target->driver = "Nordic nRF51"; - target->xml_mem_map = nrf51_xml_memory_map; - target->flash_erase = nrf51_flash_erase; - target->flash_write = nrf51_flash_write; - target_add_commands(target, nrf51_cmd_list, "nRF51"); + t->driver = "Nordic nRF51"; + t->xml_mem_map = nrf51_xml_memory_map; + t->flash_erase = nrf51_flash_erase; + t->flash_write = nrf51_flash_write; + target_add_commands(t, nrf51_cmd_list, "nRF51"); return true; } return false; } -static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int nrf51_flash_erase(target *t, uint32_t addr, size_t len) { addr &= ~(NRF51_PAGE_SIZE - 1); len &= ~(NRF51_PAGE_SIZE - 1); /* Enable erase */ - target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); + target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); /* Poll for NVMC_READY */ - while (target_mem_read32(target, NRF51_NVMC_READY) == 0) - if(target_check_error(target)) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) + if(target_check_error(t)) return -1; while (len) { if (addr == NRF51_UICR) { // Special Case /* Write to the ERASE_UICR register to erase */ - target_mem_write32(target, NRF51_NVMC_ERASEUICR, 0x1); + target_mem_write32(t, NRF51_NVMC_ERASEUICR, 0x1); } else { // Standard Flash Page /* Write address of first word in page to erase it */ - target_mem_write32(target, NRF51_NVMC_ERASEPAGE, addr); + target_mem_write32(t, NRF51_NVMC_ERASEPAGE, addr); } /* Poll for NVMC_READY */ - while (target_mem_read32(target, NRF51_NVMC_READY) == 0) - if(target_check_error(target)) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) + if(target_check_error(t)) return -1; addr += NRF51_PAGE_SIZE; @@ -195,17 +195,17 @@ static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) } /* Return to read-only */ - target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); + target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); /* Poll for NVMC_READY */ - while (target_mem_read32(target, NRF51_NVMC_READY) == 0) - if(target_check_error(target)) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) + if(target_check_error(t)) return -1; return 0; } -static int nrf51_flash_write(struct target_s *target, uint32_t dest, +static int nrf51_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { uint32_t offset = dest % 4; @@ -220,26 +220,26 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Enable write */ - target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN); + target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN); /* Poll for NVMC_READY */ - while (target_mem_read32(target, NRF51_NVMC_READY) == 0) - if(target_check_error(target)) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) + if(target_check_error(t)) return -1; /* Write stub and data to target ram and set PC */ - target_mem_write(target, 0x20000000, nrf51_flash_write_stub, 0x28); - target_mem_write(target, 0x20000028, data, len + 8); - cortexm_pc_write(target, 0x20000000); - if(target_check_error(target)) + target_mem_write(t, 0x20000000, nrf51_flash_write_stub, 0x28); + target_mem_write(t, 0x20000028, data, len + 8); + cortexm_pc_write(t, 0x20000000); + if(target_check_error(t)) return -1; /* Execute the stub */ - target_halt_resume(target, 0); - while(!target_halt_wait(target)); + target_halt_resume(t, 0); + while(!target_halt_wait(t)); /* Return to read-only */ - target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); + target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); return 0; } diff --git a/src/sam3x.c b/src/sam3x.c index b9e59a0..63b0991 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -28,8 +28,8 @@ #include "command.h" #include "gdb_packet.h" -static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int sam3x_flash_write(struct target_s *target, uint32_t dest, +static int sam3x_flash_erase(target *t, uint32_t addr, size_t len); +static int sam3x_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static bool sam3x_cmd_gpnvm_get(target *t); @@ -146,59 +146,59 @@ static const char sam4s_xml_memory_map[] = "" #define SAM3_PAGE_SIZE 256 #define SAM4_PAGE_SIZE 512 -bool sam3x_probe(struct target_s *target) +bool sam3x_probe(target *t) { - target->idcode = target_mem_read32(target, SAM3X_CHIPID_CIDR); + t->idcode = target_mem_read32(t, SAM3X_CHIPID_CIDR); /* FIXME: Check for all variants with similar flash interface */ - switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM3XxC | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3XxE | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3XxG | CHIPID_CIDR_EPROC_CM3: - target->driver = "Atmel SAM3X"; - target->xml_mem_map = sam3x_xml_memory_map; - target->flash_erase = sam3x_flash_erase; - target->flash_write = sam3x_flash_write; - target_add_commands(target, sam3x_cmd_list, "SAM3X"); + t->driver = "Atmel SAM3X"; + t->xml_mem_map = sam3x_xml_memory_map; + t->flash_erase = sam3x_flash_erase; + t->flash_write = sam3x_flash_write; + target_add_commands(t, sam3x_cmd_list, "SAM3X"); return true; } - target->idcode = target_mem_read32(target, SAM3N_CHIPID_CIDR); - switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + t->idcode = target_mem_read32(t, SAM3N_CHIPID_CIDR); + switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3NxC | CHIPID_CIDR_EPROC_CM3: - target->driver = "Atmel SAM3N"; - target->xml_mem_map = sam3n_xml_memory_map; - target->flash_erase = sam3x_flash_erase; - target->flash_write = sam3x_flash_write; - target_add_commands(target, sam3x_cmd_list, "SAM3N"); + t->driver = "Atmel SAM3N"; + t->xml_mem_map = sam3n_xml_memory_map; + t->flash_erase = sam3x_flash_erase; + t->flash_write = sam3x_flash_write; + target_add_commands(t, sam3x_cmd_list, "SAM3N"); return true; } - target->idcode = target_mem_read32(target, SAM3S_CHIPID_CIDR); - switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + t->idcode = target_mem_read32(t, SAM3S_CHIPID_CIDR); + switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM3SxA | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3: - target->driver = "Atmel SAM3S"; - target->xml_mem_map = sam3n_xml_memory_map; - target->flash_erase = sam3x_flash_erase; - target->flash_write = sam3x_flash_write; - target_add_commands(target, sam3x_cmd_list, "SAM3S"); + t->driver = "Atmel SAM3S"; + t->xml_mem_map = sam3n_xml_memory_map; + t->flash_erase = sam3x_flash_erase; + t->flash_write = sam3x_flash_write; + target_add_commands(t, sam3x_cmd_list, "SAM3S"); return true; } - target->idcode = target_mem_read32(target, SAM4S_CHIPID_CIDR); - switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + t->idcode = target_mem_read32(t, SAM4S_CHIPID_CIDR); + switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM4SxA | CHIPID_CIDR_EPROC_CM4: case CHIPID_CIDR_ARCH_SAM4SxB | CHIPID_CIDR_EPROC_CM4: case CHIPID_CIDR_ARCH_SAM4SxC | CHIPID_CIDR_EPROC_CM4: - target->driver = "Atmel SAM4S"; - target->xml_mem_map = sam4s_xml_memory_map; - target->flash_erase = sam3x_flash_erase; - target->flash_write = sam3x_flash_write; - target_add_commands(target, sam3x_cmd_list, "SAM4S"); + t->driver = "Atmel SAM4S"; + t->xml_mem_map = sam4s_xml_memory_map; + t->flash_erase = sam3x_flash_erase; + t->flash_write = sam3x_flash_write; + target_add_commands(t, sam3x_cmd_list, "SAM4S"); return true; } @@ -206,27 +206,27 @@ bool sam3x_probe(struct target_s *target) } static int -sam3x_flash_cmd(struct target_s *target, uint32_t base, uint8_t cmd, uint16_t arg) +sam3x_flash_cmd(target *t, uint32_t base, uint8_t cmd, uint16_t arg) { DEBUG("%s: base = 0x%08x cmd = 0x%02X, arg = 0x%06X\n", __func__, base, cmd, arg); - target_mem_write32(target, EEFC_FCR(base), + target_mem_write32(t, EEFC_FCR(base), EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8)); - while (!(target_mem_read32(target, EEFC_FSR(base)) & EEFC_FSR_FRDY)) - if(target_check_error(target)) + while (!(target_mem_read32(t, EEFC_FSR(base)) & EEFC_FSR_FRDY)) + if(target_check_error(t)) return -1; - uint32_t sr = target_mem_read32(target, EEFC_FSR(base)); + uint32_t sr = target_mem_read32(t, EEFC_FSR(base)); return sr & EEFC_FSR_ERROR; } static uint32_t -sam3x_flash_base(struct target_s *target, uint32_t addr, uint32_t *offset) +sam3x_flash_base(target *t, uint32_t addr, uint32_t *offset) { - if (strcmp(target->driver, "Atmel SAM3X") == 0) { + if (strcmp(t->driver, "Atmel SAM3X") == 0) { uint32_t half = -1; - switch (target->idcode & CHIPID_CIDR_NVPSIZ_MASK) { + switch (t->idcode & CHIPID_CIDR_NVPSIZ_MASK) { case CHIPID_CIDR_NVPSIZ_128K: half = 0x00090000; break; @@ -248,9 +248,9 @@ sam3x_flash_base(struct target_s *target, uint32_t addr, uint32_t *offset) } } - if (strcmp(target->driver, "Atmel SAM4S") == 0) { + if (strcmp(t->driver, "Atmel SAM4S") == 0) { uint32_t half = -1; - switch (target->idcode & CHIPID_CIDR_NVPSIZ_MASK) { + switch (t->idcode & CHIPID_CIDR_NVPSIZ_MASK) { case CHIPID_CIDR_NVPSIZ_128K: case CHIPID_CIDR_NVPSIZ_256K: case CHIPID_CIDR_NVPSIZ_512K: @@ -281,16 +281,16 @@ sam3x_flash_base(struct target_s *target, uint32_t addr, uint32_t *offset) return SAM3N_EEFC_BASE; } -static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int sam3x_flash_erase(target *t, uint32_t addr, size_t len) { uint32_t offset; - uint32_t base = sam3x_flash_base(target, addr, &offset); + uint32_t base = sam3x_flash_base(t, addr, &offset); /* The SAM4S is the only supported device with a page erase command. * Erasing is done in 8-page chunks. arg[15:2] contains the page * number and arg[1:0] contains 0x1, indicating 8-page chunks. */ - if (strcmp(target->driver, "Atmel SAM4S") == 0) { + if (strcmp(t->driver, "Atmel SAM4S") == 0) { unsigned chunk = offset / SAM4_PAGE_SIZE; /* Fail if the start address is not 8-page-aligned. */ @@ -302,7 +302,7 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) */ while (len > 0) { int16_t arg = chunk | 0x1; - if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_EPA, arg)) + if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_EPA, arg)) return -1; len -= SAM4_PAGE_SIZE * 8; @@ -322,10 +322,10 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) memset(buf, 0xff, sizeof(buf)); /* Only do this once, since it doesn't change. */ - target_mem_write(target, addr, buf, SAM3_PAGE_SIZE); + target_mem_write(t, addr, buf, SAM3_PAGE_SIZE); while (len) { - if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_EWP, chunk)) + if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_EWP, chunk)) return -1; len -= SAM3_PAGE_SIZE; @@ -336,17 +336,17 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) return 0; } -static int sam3x_flash_write(struct target_s *target, uint32_t dest, +static int sam3x_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { unsigned page_size; - if (strcmp(target->driver, "Atmel SAM4S") == 0) { + if (strcmp(t->driver, "Atmel SAM4S") == 0) { page_size = SAM4_PAGE_SIZE; } else { page_size = SAM3_PAGE_SIZE; } uint32_t offset; - uint32_t base = sam3x_flash_base(target, dest, &offset); + uint32_t base = sam3x_flash_base(t, dest, &offset); uint8_t buf[page_size]; unsigned first_chunk = offset / page_size; unsigned last_chunk = (offset + len - 1) / page_size; @@ -380,8 +380,8 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, src += page_size; } - target_mem_write(target, dest, buf, page_size); - if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_WP, chunk)) + target_mem_write(t, dest, buf, page_size); + if(sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_WP, chunk)) return -1; } diff --git a/src/samd.c b/src/samd.c index a996610..c8517aa 100644 --- a/src/samd.c +++ b/src/samd.c @@ -40,8 +40,8 @@ #include "gdb_packet.h" #include "cortexm.h" -static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int samd_flash_write(struct target_s *target, uint32_t dest, +static int samd_flash_erase(target *t, uint32_t addr, size_t len); +static int samd_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static bool samd_cmd_erase_all(target *t); @@ -162,28 +162,28 @@ static const char samd_xml_memory_map[] = "" /** * Reads the SAM D20 Peripheral ID */ -uint64_t samd_read_pid(struct target_s *target) +uint64_t samd_read_pid(target *t) { uint64_t pid = 0; uint8_t i, j; /* Five PID registers to read LSB first */ for (i = 0, j = 0; i < 5; i++, j += 8) - pid |= (target_mem_read32(target, SAMD_DSU_PID(i)) & 0xFF) << j; + pid |= (target_mem_read32(t, SAMD_DSU_PID(i)) & 0xFF) << j; return pid; } /** * Reads the SAM D20 Component ID */ -uint32_t samd_read_cid(struct target_s *target) +uint32_t samd_read_cid(target *t) { uint64_t cid = 0; uint8_t i, j; /* Four CID registers to read LSB first */ for (i = 0, j = 0; i < 4; i++, j += 8) - cid |= (target_mem_read32(target, SAMD_DSU_CID(i)) & 0xFF) << j; + cid |= (target_mem_read32(t, SAMD_DSU_CID(i)) & 0xFF) << j; return cid; } @@ -193,7 +193,7 @@ uint32_t samd_read_cid(struct target_s *target) * removes the target from extended reset where required. */ static void -samd_reset(struct target_s *target) +samd_reset(target *t) { /** * SRST is not asserted here as it appears to reset the adiv5 @@ -212,31 +212,30 @@ samd_reset(struct target_s *target) */ /* Read DHCSR here to clear S_RESET_ST bit before reset */ - target_mem_read32(target, CORTEXM_DHCSR); + target_mem_read32(t, CORTEXM_DHCSR); /* Request system reset from NVIC: SRST doesn't work correctly */ /* This could be VECTRESET: 0x05FA0001 (reset only core) * or SYSRESETREQ: 0x05FA0004 (system reset) */ - target_mem_write32(target, CORTEXM_AIRCR, + target_mem_write32(t, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); /* Exit extended reset */ - if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(t, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - target_mem_write32(target, SAMD_DSU_CTRLSTAT, - SAMD_STATUSA_CRSTEXT); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } /* Poll for release from reset */ - while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); + while (target_mem_read32(t, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); /* Reset DFSR flags */ - target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(t, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); /* Clear any target errors */ - target_check_error(target); + target_check_error(t); } /** @@ -246,16 +245,16 @@ samd_reset(struct target_s *target) * Only required for SAM D20 _Revision B_ Silicon */ static void -samd20_revB_detach(struct target_s *target) +samd20_revB_detach(target *t) { - cortexm_detach(target); + cortexm_detach(t); /* ---- Additional ---- */ /* Exit extended reset */ - if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(t, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - target_mem_write32(target, SAMD_DSU_CTRLSTAT, + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } } @@ -267,16 +266,15 @@ samd20_revB_detach(struct target_s *target) * Only required for SAM D20 _Revision B_ Silicon */ static void -samd20_revB_halt_resume(struct target_s *target, bool step) +samd20_revB_halt_resume(target *t, bool step) { - cortexm_halt_resume(target, step); + cortexm_halt_resume(t, step); /* ---- Additional ---- */ /* Exit extended reset */ - if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & - SAMD_STATUSA_CRSTEXT) { + if (target_mem_read32(t, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - target_mem_write32(target, SAMD_DSU_CTRLSTAT, + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } } @@ -290,7 +288,7 @@ samd20_revB_halt_resume(struct target_s *target, bool step) * rescue the device. */ static bool -samd_protected_attach(struct target_s *target) +samd_protected_attach(target *t) { /** * TODO: Notify the user that we're not really attached and @@ -299,7 +297,7 @@ samd_protected_attach(struct target_s *target) */ /* Patch back in the normal cortexm attach for next time */ - target->attach = cortexm_attach; + t->attach = cortexm_attach; /* Allow attach this time */ return true; @@ -365,10 +363,10 @@ struct samd_descr samd_parse_device_id(uint32_t did) char variant_string[40]; -bool samd_probe(struct target_s *target) +bool samd_probe(target *t) { - uint32_t cid = samd_read_cid(target); - uint32_t pid = samd_read_pid(target); + uint32_t cid = samd_read_cid(t); + uint32_t pid = samd_read_pid(t); /* Check the ARM Coresight Component and Perhiperal IDs */ if ((cid != SAMD_CID_VALUE) || @@ -376,14 +374,13 @@ bool samd_probe(struct target_s *target) return false; /* Read the Device ID */ - uint32_t did = target_mem_read32(target, SAMD_DSU_DID); + uint32_t did = target_mem_read32(t, SAMD_DSU_DID); /* If the Device ID matches */ if ((did & SAMD_DID_MASK) != SAMD_DID_CONST_VALUE) return false; - uint32_t ctrlstat = target_mem_read32(target, - SAMD_DSU_CTRLSTAT); + uint32_t ctrlstat = target_mem_read32(t, SAMD_DSU_CTRLSTAT); struct samd_descr samd = samd_parse_device_id(did); /* Protected? */ @@ -403,8 +400,8 @@ bool samd_probe(struct target_s *target) } /* Setup Target */ - target->driver = variant_string; - target->reset = samd_reset; + t->driver = variant_string; + t->reset = samd_reset; if (samd.series == 20 && samd.revision == 'B') { /** @@ -412,8 +409,8 @@ bool samd_probe(struct target_s *target) * extended reset. Appears to be * related to Errata 35.4.1 ref 12015 */ - target->detach = samd20_revB_detach; - target->halt_resume = samd20_revB_halt_resume; + t->detach = samd20_revB_detach; + t->halt_resume = samd20_revB_halt_resume; } if (protected) { /** @@ -423,23 +420,23 @@ bool samd_probe(struct target_s *target) * attach on a temporary basis so they * can rescue the device. */ - target->attach = samd_protected_attach; + t->attach = samd_protected_attach; } - target->xml_mem_map = samd_xml_memory_map; - target->flash_erase = samd_flash_erase; - target->flash_write = samd_flash_write; - target_add_commands(target, samd_cmd_list, "SAMD"); + t->xml_mem_map = samd_xml_memory_map; + t->flash_erase = samd_flash_erase; + t->flash_write = samd_flash_write; + target_add_commands(t, samd_cmd_list, "SAMD"); /* If we're not in reset here */ if (!connect_assert_srst) { /* We'll have to release the target from * extended reset to make attach possible */ - if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(t, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - target_mem_write32(target, SAMD_DSU_CTRLSTAT, + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } } @@ -450,23 +447,23 @@ bool samd_probe(struct target_s *target) /** * Temporary (until next reset) flash memory locking / unlocking */ -static void samd_lock_current_address(struct target_s *target) +static void samd_lock_current_address(target *t) { /* Issue the unlock command */ - target_mem_write32(target, SAMD_NVMC_CTRLA, + target_mem_write32(t, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK); } -static void samd_unlock_current_address(struct target_s *target) +static void samd_unlock_current_address(target *t) { /* Issue the unlock command */ - target_mem_write32(target, SAMD_NVMC_CTRLA, + target_mem_write32(t, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK); } /** * Erase flash row by row */ -static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int samd_flash_erase(target *t, uint32_t addr, size_t len) { addr &= ~(SAMD_ROW_SIZE - 1); len &= ~(SAMD_ROW_SIZE - 1); @@ -474,21 +471,21 @@ static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len) while (len) { /* Write address of first word in row to erase it */ /* Must be shifted right for 16-bit address, see Datasheet ยง20.8.8 Address */ - target_mem_write32(target, SAMD_NVMC_ADDRESS, addr >> 1); + target_mem_write32(t, SAMD_NVMC_ADDRESS, addr >> 1); /* Unlock */ - samd_unlock_current_address(target); + samd_unlock_current_address(t); /* Issue the erase command */ - target_mem_write32(target, SAMD_NVMC_CTRLA, + target_mem_write32(t, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW); /* Poll for NVM Ready */ - while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) - if (target_check_error(target)) + while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + if (target_check_error(t)) return -1; /* Lock */ - samd_lock_current_address(target); + samd_lock_current_address(t); addr += SAMD_ROW_SIZE; len -= SAMD_ROW_SIZE; @@ -500,7 +497,7 @@ static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len) /** * Write flash page by page */ -static int samd_flash_write(struct target_s *target, uint32_t dest, +static int samd_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { /* Find the size of our 32-bit data buffer */ @@ -529,26 +526,26 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, length = MIN(end + 4, next_page) - addr; /* Write within a single page. This may be part or all of the page */ - target_mem_write(target, addr, &data[i], length); + target_mem_write(t, addr, &data[i], length); addr += length; i += (length >> 2); /* If MANW=0 (default) we may have triggered an automatic * write. Ignore this */ /* Unlock */ - samd_unlock_current_address(target); + samd_unlock_current_address(t); /* Issue the write page command */ - target_mem_write32(target, SAMD_NVMC_CTRLA, + target_mem_write32(t, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE); /* Poll for NVM Ready */ - while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) - if (target_check_error(target)) + while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + if (target_check_error(t)) return -1; /* Lock */ - samd_lock_current_address(target); + samd_lock_current_address(t); } return 0; diff --git a/src/stm32f1.c b/src/stm32f1.c index 8f7a7d7..49a5815 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -46,11 +46,11 @@ const struct command_s stm32f1_cmd_list[] = { }; -static int stm32md_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int stm32hd_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, size_t len, +static int stm32md_flash_erase(target *t, uint32_t addr, size_t len); +static int stm32hd_flash_erase(target *t, uint32_t addr, size_t len); +static int stm32f1_flash_erase(target *t, uint32_t addr, size_t len, uint32_t pagesize); -static int stm32f1_flash_write(struct target_s *target, uint32_t dest, +static int stm32f1_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static const char stm32f1_driver_str[] = "STM32, Medium density."; @@ -127,66 +127,66 @@ static const uint16_t stm32f1_flash_write_stub[] = { #define SRAM_BASE 0x20000000 #define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(stm32f1_flash_write_stub), 4) -bool stm32f1_probe(struct target_s *target) +bool stm32f1_probe(target *t) { - target->idcode = target_mem_read32(target, DBGMCU_IDCODE) & 0xfff; - switch(target->idcode) { + t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff; + switch(t->idcode) { case 0x410: /* Medium density */ case 0x412: /* Low denisty */ case 0x420: /* Value Line, Low-/Medium density */ - target->driver = stm32f1_driver_str; - target->xml_mem_map = stm32f1_xml_memory_map; - target->flash_erase = stm32md_flash_erase; - target->flash_write = stm32f1_flash_write; - target_add_commands(target, stm32f1_cmd_list, "STM32 LD/MD"); + t->driver = stm32f1_driver_str; + t->xml_mem_map = stm32f1_xml_memory_map; + t->flash_erase = stm32md_flash_erase; + t->flash_write = stm32f1_flash_write; + target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD"); return true; case 0x414: /* High density */ case 0x418: /* Connectivity Line */ case 0x428: /* Value Line, High Density */ - target->driver = stm32hd_driver_str; - target->xml_mem_map = stm32hd_xml_memory_map; - target->flash_erase = stm32hd_flash_erase; - target->flash_write = stm32f1_flash_write; - target_add_commands(target, stm32f1_cmd_list, "STM32 HD/CL"); + t->driver = stm32hd_driver_str; + t->xml_mem_map = stm32hd_xml_memory_map; + t->flash_erase = stm32hd_flash_erase; + t->flash_write = stm32f1_flash_write; + target_add_commands(t, stm32f1_cmd_list, "STM32 HD/CL"); return true; case 0x422: /* STM32F30x */ case 0x432: /* STM32F37x */ - target->driver = stm32f3_driver_str; - target->xml_mem_map = stm32hd_xml_memory_map; - target->flash_erase = stm32hd_flash_erase; - target->flash_write = stm32f1_flash_write; - target_add_commands(target, stm32f1_cmd_list, "STM32F3"); + t->driver = stm32f3_driver_str; + t->xml_mem_map = stm32hd_xml_memory_map; + t->flash_erase = stm32hd_flash_erase; + t->flash_write = stm32f1_flash_write; + target_add_commands(t, stm32f1_cmd_list, "STM32F3"); return true; } - target->idcode = target_mem_read32(target, DBGMCU_IDCODE_F0) & 0xfff; - switch(target->idcode) { + t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff; + switch(t->idcode) { case 0x444: /* STM32F03 RM0091 Rev.7 */ case 0x445: /* STM32F04 RM0091 Rev.7 */ case 0x440: /* STM32F05 RM0091 Rev.7 */ case 0x448: /* STM32F07 RM0091 Rev.7 */ case 0x442: /* STM32F09 RM0091 Rev.7 */ - switch(target->idcode) { + switch(t->idcode) { case 0x444: /* STM32F03 */ - target->driver = stm32f03_driver_str; + t->driver = stm32f03_driver_str; break; case 0x445: /* STM32F04 */ - target->driver = stm32f04_driver_str; + t->driver = stm32f04_driver_str; break; case 0x440: /* STM32F05 */ - target->driver = stm32f05_driver_str; + t->driver = stm32f05_driver_str; break; case 0x448: /* STM32F07 */ - target->driver = stm32f07_driver_str; + t->driver = stm32f07_driver_str; break; case 0x442: /* STM32F09 */ - target->driver = stm32f09_driver_str; + t->driver = stm32f09_driver_str; break; } - target->xml_mem_map = stm32f1_xml_memory_map; - target->flash_erase = stm32md_flash_erase; - target->flash_write = stm32f1_flash_write; - target_add_commands(target, stm32f1_cmd_list, "STM32F0"); + t->xml_mem_map = stm32f1_xml_memory_map; + t->flash_erase = stm32md_flash_erase; + t->flash_write = stm32f1_flash_write; + target_add_commands(t, stm32f1_cmd_list, "STM32F0"); return true; } @@ -199,7 +199,7 @@ static void stm32f1_flash_unlock(target *t) target_mem_write32(t, FLASH_KEYR, KEY2); } -static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, +static int stm32f1_flash_erase(target *t, uint32_t addr, size_t len, uint32_t pagesize) { uint16_t sr; @@ -207,19 +207,19 @@ static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, addr &= ~(pagesize - 1); len = (len + pagesize - 1) & ~(pagesize - 1); - stm32f1_flash_unlock(target); + stm32f1_flash_unlock(t); while(len) { /* Flash page erase instruction */ - target_mem_write32(target, FLASH_CR, FLASH_CR_PER); + target_mem_write32(t, FLASH_CR, FLASH_CR_PER); /* write address to FMA */ - target_mem_write32(target, FLASH_AR, addr); + target_mem_write32(t, FLASH_AR, addr); /* Flash page erase start instruction */ - target_mem_write32(target, FLASH_CR, FLASH_CR_STRT | FLASH_CR_PER); + target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_PER); /* Read FLASH_SR to poll for BSY bit */ - while (target_mem_read32(target, FLASH_SR) & FLASH_SR_BSY) - if(target_check_error(target)) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) + if(target_check_error(t)) return -1; len -= pagesize; @@ -227,24 +227,24 @@ static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, } /* Check for error */ - sr = target_mem_read32(target, FLASH_SR); + sr = target_mem_read32(t, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return -1; return 0; } -static int stm32hd_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int stm32hd_flash_erase(target *t, uint32_t addr, size_t len) { - return stm32f1_flash_erase(target, addr, len, 0x800); + return stm32f1_flash_erase(t, addr, len, 0x800); } -static int stm32md_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int stm32md_flash_erase(target *t, uint32_t addr, size_t len) { - return stm32f1_flash_erase(target, addr, len, 0x400); + return stm32f1_flash_erase(t, addr, len, 0x400); } -static int stm32f1_flash_write(struct target_s *target, uint32_t dest, +static int stm32f1_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { uint32_t offset = dest % 4; @@ -256,8 +256,8 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)data + offset, src, len); /* Write stub and data to target ram and set PC */ - target_mem_write(target, STUB_BUFFER_BASE, (void*)data, sizeof(data)); - return cortexm_run_stub(target, SRAM_BASE, stm32f1_flash_write_stub, + target_mem_write(t, STUB_BUFFER_BASE, (void*)data, sizeof(data)); + return cortexm_run_stub(t, SRAM_BASE, stm32f1_flash_write_stub, sizeof(stm32f1_flash_write_stub), dest - offset, STUB_BUFFER_BASE, sizeof(data), 0); diff --git a/src/stm32f4.c b/src/stm32f4.c index fe844ca..125a15e 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -47,8 +47,8 @@ const struct command_s stm32f4_cmd_list[] = { }; -static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t len); -static int stm32f4_flash_write(struct target_s *target, uint32_t dest, +static int stm32f4_flash_erase(target *t, uint32_t addr, size_t len); +static int stm32f4_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); static const char stm32f4_driver_str[] = "STM32F4xx"; @@ -127,11 +127,11 @@ static const uint16_t stm32f4_flash_write_stub[] = { #define SRAM_BASE 0x20000000 #define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(stm32f4_flash_write_stub), 4) -bool stm32f4_probe(struct target_s *target) +bool stm32f4_probe(target *t) { uint32_t idcode; - idcode = target_mem_read32(target, DBGMCU_IDCODE); + idcode = target_mem_read32(t, DBGMCU_IDCODE); switch(idcode & 0xFFF) { case 0x411: /* Documented to be 0x413! This is what I read... */ case 0x413: /* F407VGT6 */ @@ -139,11 +139,11 @@ bool stm32f4_probe(struct target_s *target) case 0x423: /* F401 B/C RM0368 Rev.3 */ case 0x431: /* F411 RM0383 Rev.4 */ case 0x433: /* F401 D/E RM0368 Rev.3 */ - target->xml_mem_map = stm32f4_xml_memory_map; - target->driver = stm32f4_driver_str; - target->flash_erase = stm32f4_flash_erase; - target->flash_write = stm32f4_flash_write; - target_add_commands(target, stm32f4_cmd_list, "STM32F4"); + t->xml_mem_map = stm32f4_xml_memory_map; + t->driver = stm32f4_driver_str; + t->flash_erase = stm32f4_flash_erase; + t->flash_write = stm32f4_flash_write; + target_add_commands(t, stm32f4_cmd_list, "STM32F4"); return true; } return false; @@ -158,7 +158,7 @@ static void stm32f4_flash_unlock(target *t) } } -static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t len) +static int stm32f4_flash_erase(target *t, uint32_t addr, size_t len) { uint16_t sr; uint32_t cr; @@ -166,7 +166,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le addr &= 0x07FFC000; - stm32f4_flash_unlock(target); + stm32f4_flash_unlock(t); while(len) { if (addr < 0x10000) { /* Sector 0..3 */ @@ -183,13 +183,13 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le } cr |= FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER; /* Flash page erase instruction */ - target_mem_write32(target, FLASH_CR, cr); + target_mem_write32(t, FLASH_CR, cr); /* write address to FMA */ - target_mem_write32(target, FLASH_CR, cr | FLASH_CR_STRT); + target_mem_write32(t, FLASH_CR, cr | FLASH_CR_STRT); /* Read FLASH_SR to poll for BSY bit */ - while(target_mem_read32(target, FLASH_SR) & FLASH_SR_BSY) - if(target_check_error(target)) + while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) + if(target_check_error(t)) return -1; len -= pagesize; @@ -197,14 +197,14 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le } /* Check for error */ - sr = target_mem_read32(target, FLASH_SR); + sr = target_mem_read32(t, FLASH_SR); if(sr & SR_ERROR_MASK) return -1; return 0; } -static int stm32f4_flash_write(struct target_s *target, uint32_t dest, +static int stm32f4_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) { uint32_t offset = dest % 4; @@ -216,8 +216,8 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)data + offset, src, len); /* Write buffer to target ram call stub */ - target_mem_write(target, STUB_BUFFER_BASE, data, sizeof(data)); - return cortexm_run_stub(target, SRAM_BASE, stm32f4_flash_write_stub, + target_mem_write(t, STUB_BUFFER_BASE, data, sizeof(data)); + return cortexm_run_stub(t, SRAM_BASE, stm32f4_flash_write_stub, sizeof(stm32f4_flash_write_stub), dest - offset, STUB_BUFFER_BASE, sizeof(data), 0); diff --git a/src/stm32l0.c b/src/stm32l0.c index 6d02ad2..695bd22 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -123,37 +123,25 @@ static int inhibit_stubs; /* Local option to force non-stub flash IO */ -static int stm32lx_nvm_erase(struct target_s* target, - uint32_t addr, size_t len); -static int stm32lx_nvm_write(struct target_s* target, - uint32_t destination, - const uint8_t* source, +static int stm32lx_nvm_erase(target *t, uint32_t addr, size_t len); +static int stm32lx_nvm_write(target *t, uint32_t dest, const uint8_t* src, size_t size); -static int stm32lx_nvm_prog_erase(struct target_s* target, - uint32_t addr, size_t len); -static int stm32lx_nvm_prog_write(struct target_s* target, - uint32_t destination, - const uint8_t* source, +static int stm32lx_nvm_prog_erase(target *t, uint32_t addr, size_t len); +static int stm32lx_nvm_prog_write(target *t, uint32_t dest, const uint8_t* src, size_t size); -static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, - uint32_t addr, size_t len); -static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, - uint32_t destination, - const uint8_t* source, - size_t size); +static int stm32lx_nvm_prog_erase_stubbed(target *t, uint32_t addr, size_t len); +static int stm32lx_nvm_prog_write_stubbed(target *t, uint32_t dest, + const uint8_t* src, size_t size); -static int stm32lx_nvm_data_erase(struct target_s* target, - uint32_t addr, size_t len); -static int stm32lx_nvm_data_write(struct target_s* target, - uint32_t destination, - const uint8_t* source, - size_t size); +static int stm32lx_nvm_data_erase(target *t, uint32_t addr, size_t len); +static int stm32lx_nvm_data_write(target *t, uint32_t dest, + const uint8_t* src, size_t size); -static bool stm32lx_cmd_option (target* t, int argc, char** argv); -static bool stm32lx_cmd_eeprom (target* t, int argc, char** argv); -static bool stm32lx_cmd_stubs (target* t, int argc, char** argv); +static bool stm32lx_cmd_option(target* t, int argc, char** argv); +static bool stm32lx_cmd_eeprom(target* t, int argc, char** argv); +static bool stm32lx_cmd_stubs(target* t, int argc, char** argv); static const struct command_s stm32lx_cmd_list[] = { { "stubs", (cmd_handler) stm32lx_cmd_stubs, @@ -216,9 +204,9 @@ static const uint16_t stm32l0_nvm_prog_erase_stub [] = { #include "../flashstub/stm32l05x-nvm-prog-erase.stub" }; -static uint32_t stm32lx_nvm_prog_page_size(struct target_s* target) +static uint32_t stm32lx_nvm_prog_page_size(target *t) { - switch (target->idcode) { + switch (t->idcode) { case 0x417: /* STM32L0xx */ return STM32L0_NVM_PROG_PAGE_SIZE; default: /* STM32L1xx */ @@ -226,9 +214,9 @@ static uint32_t stm32lx_nvm_prog_page_size(struct target_s* target) } } -static bool stm32lx_is_stm32l1(struct target_s* target) +static bool stm32lx_is_stm32l1(target *t) { - switch (target->idcode) { + switch (t->idcode) { case 0x417: /* STM32L0xx */ return false; default: /* STM32L1xx */ @@ -236,9 +224,9 @@ static bool stm32lx_is_stm32l1(struct target_s* target) } } -static uint32_t stm32lx_nvm_eeprom_size(struct target_s* target) +static uint32_t stm32lx_nvm_eeprom_size(target *t) { - switch (target->idcode) { + switch (t->idcode) { case 0x417: /* STM32L0xx */ return STM32L0_NVM_EEPROM_SIZE; default: /* STM32L1xx */ @@ -246,9 +234,9 @@ static uint32_t stm32lx_nvm_eeprom_size(struct target_s* target) } } -static uint32_t stm32lx_nvm_phys(struct target_s* target) +static uint32_t stm32lx_nvm_phys(target *t) { - switch (target->idcode) { + switch (t->idcode) { case 0x417: /* STM32L0xx */ return STM32L0_NVM_PHYS; default: /* STM32L1xx */ @@ -256,9 +244,9 @@ static uint32_t stm32lx_nvm_phys(struct target_s* target) } } -static uint32_t stm32lx_nvm_data_page_size(struct target_s* target) +static uint32_t stm32lx_nvm_data_page_size(target *t) { - switch (target->idcode) { + switch (t->idcode) { case 0x417: /* STM32L0xx */ return STM32L0_NVM_DATA_PAGE_SIZE; default: /* STM32L1xx */ @@ -266,9 +254,9 @@ static uint32_t stm32lx_nvm_data_page_size(struct target_s* target) } } -static uint32_t stm32lx_nvm_option_size(struct target_s* target) +static uint32_t stm32lx_nvm_option_size(target *t) { - switch (target->idcode) { + switch (t->idcode) { case 0x417: /* STM32L0xx */ return STM32L0_NVM_OPT_SIZE; default: /* STM32L1xx */ @@ -279,40 +267,38 @@ static uint32_t stm32lx_nvm_option_size(struct target_s* target) /** Query MCU memory for an indication as to whether or not the currently attached target is served by this module. We detect the STM32L0xx parts as well as the STM32L1xx's. */ -bool stm32l0_probe(struct target_s* target) +bool stm32l0_probe(target *t) { uint32_t idcode; - idcode = target_mem_read32(target, - STM32L1_DBGMCU_IDCODE_PHYS) & 0xfff; + idcode = target_mem_read32(t, STM32L1_DBGMCU_IDCODE_PHYS) & 0xfff; switch (idcode) { case 0x416: /* CAT. 1 device */ case 0x429: /* CAT. 2 device */ case 0x427: /* CAT. 3 device */ case 0x436: /* CAT. 4 device */ case 0x437: /* CAT. 5 device */ - target->idcode = idcode; - target->driver = stm32l1_driver_str; - target->xml_mem_map = stm32l1_xml_memory_map; - target->flash_erase = stm32lx_nvm_erase; - target->flash_write = stm32lx_nvm_write; - target_add_commands(target, stm32lx_cmd_list, "STM32L1x"); + t->idcode = idcode; + t->driver = stm32l1_driver_str; + t->xml_mem_map = stm32l1_xml_memory_map; + t->flash_erase = stm32lx_nvm_erase; + t->flash_write = stm32lx_nvm_write; + target_add_commands(t, stm32lx_cmd_list, "STM32L1x"); return true; } - idcode = target_mem_read32(target, - STM32L0_DBGMCU_IDCODE_PHYS) & 0xfff; + idcode = target_mem_read32(t, STM32L0_DBGMCU_IDCODE_PHYS) & 0xfff; switch (idcode) { default: break; case 0x417: /* STM32L0x[123] & probably others */ - target->idcode = idcode; - target->driver = stm32l0_driver_str; - target->xml_mem_map = stm32l0_xml_memory_map; - target->flash_erase = stm32lx_nvm_erase; - target->flash_write = stm32lx_nvm_write; - target_add_commands(target, stm32lx_cmd_list, "STM32L0x"); + t->idcode = idcode; + t->driver = stm32l0_driver_str; + t->xml_mem_map = stm32l0_xml_memory_map; + t->flash_erase = stm32lx_nvm_erase; + t->flash_write = stm32lx_nvm_write; + target_add_commands(t, stm32lx_cmd_list, "STM32L0x"); return true; } @@ -364,17 +350,17 @@ static bool stm32lx_nvm_opt_unlock(target *t, uint32_t nvm) /** Erase a region of flash using a stub function. This only works when the MCU hasn't entered a fault state(see NOTES). The flash array is erased for all pages from addr to addr+len inclusive. */ -static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, +static int stm32lx_nvm_prog_erase_stubbed(target *t, uint32_t addr, size_t size) { struct stm32lx_nvm_stub_info info; - const uint32_t nvm = stm32lx_nvm_phys(target); + const uint32_t nvm = stm32lx_nvm_phys(t); info.nvm = nvm; - info.page_size = stm32lx_nvm_prog_page_size(target); + info.page_size = stm32lx_nvm_prog_page_size(t); /* Load the stub */ - target_mem_write(target, STM32Lx_STUB_PHYS, + target_mem_write(t, STM32Lx_STUB_PHYS, &stm32l0_nvm_prog_erase_stub[0], sizeof(stm32l0_nvm_prog_erase_stub)); @@ -383,21 +369,20 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, info.size = size; /* Copy parameters */ - target_mem_write(target, STM32Lx_STUB_INFO_PHYS, - &info, sizeof(info)); + target_mem_write(t, STM32Lx_STUB_INFO_PHYS, &info, sizeof(info)); /* Execute stub */ - cortexm_pc_write(target, STM32Lx_STUB_PHYS); - if (target_check_error(target)) + cortexm_pc_write(t, STM32Lx_STUB_PHYS); + if (target_check_error(t)) return -1; - target_halt_resume(target, 0); - while (!target_halt_wait(target)) + target_halt_resume(t, 0); + while (!target_halt_wait(t)) ; - { - if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) - & STM32Lx_NVM_SR_ERR_M) - return -1; - } + + if (target_mem_read32(t, STM32Lx_NVM_SR(nvm)) + & STM32Lx_NVM_SR_ERR_M) + return -1; + return 0; } @@ -407,14 +392,14 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, when the MCU hasn't entered a fault state. Once the MCU faults, this function will not succeed because the MCU will fault before executing a single instruction in the stub. */ -static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, +static int stm32lx_nvm_prog_write_stubbed(target *t, uint32_t destination, const uint8_t* source, size_t size) { struct stm32lx_nvm_stub_info info; - const uint32_t nvm = stm32lx_nvm_phys(target); - const size_t page_size = stm32lx_nvm_prog_page_size(target); + const uint32_t nvm = stm32lx_nvm_phys(t); + const size_t page_size = stm32lx_nvm_prog_page_size(t); /* We can only handle word aligned writes and even word-multiple ranges. The stm32lx's cannot perform @@ -427,7 +412,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, info.page_size = page_size; /* Load the stub */ - target_mem_write(target, STM32Lx_STUB_PHYS, + target_mem_write(t, STM32Lx_STUB_PHYS, &stm32l0_nvm_prog_write_stub[0], sizeof(stm32l0_nvm_prog_write_stub)); @@ -451,7 +436,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, info.size = cb; /* Copy data to write to flash */ - target_mem_write(target, info.source, source, info.size); + target_mem_write(t, info.source, source, info.size); /* Move pointers early */ destination += cb; @@ -459,18 +444,18 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, size -= cb; /* Copy parameters */ - target_mem_write(target, STM32Lx_STUB_INFO_PHYS, + target_mem_write(t, STM32Lx_STUB_INFO_PHYS, &info, sizeof(info)); /* Execute stub */ - cortexm_pc_write(target, STM32Lx_STUB_PHYS); - if (target_check_error(target)) + cortexm_pc_write(t, STM32Lx_STUB_PHYS); + if (target_check_error(t)) return -1; - target_halt_resume(target, 0); - while (!target_halt_wait(target)) + target_halt_resume(t, 0); + while (!target_halt_wait(t)) ; - if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) + if (target_mem_read32(t, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_ERR_M) return -1; } @@ -482,19 +467,19 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, /** Erase a region of NVM for STM32Lx. This is the lead function and it will invoke an implementation, stubbed or not depending on the options and the range of addresses. */ -static int stm32lx_nvm_erase(struct target_s* target, uint32_t addr, size_t size) +static int stm32lx_nvm_erase(target *t, uint32_t addr, size_t size) { if (addr >= STM32Lx_NVM_EEPROM_PHYS) - return stm32lx_nvm_data_erase(target, addr, size); + return stm32lx_nvm_data_erase(t, addr, size); /* Use stub if not inhibited, the MCU is in a non-exceptonal state and there is stub. */ volatile uint32_t regs[20]; - target_regs_read(target, ®s); + target_regs_read(t, ®s); if (inhibit_stubs || (regs[16] & 0xf)) - return stm32lx_nvm_prog_erase(target, addr, size); + return stm32lx_nvm_prog_erase(t, addr, size); - return stm32lx_nvm_prog_erase_stubbed(target, addr, size); + return stm32lx_nvm_prog_erase_stubbed(t, addr, size); } @@ -503,13 +488,13 @@ static int stm32lx_nvm_erase(struct target_s* target, uint32_t addr, size_t size the options and the range of addresses. Data (EEPROM) writes don't have to care about alignment, but the program flash does. There is a fixup for unaligned program flash writes. */ -static int stm32lx_nvm_write(struct target_s* target, +static int stm32lx_nvm_write(target *t, uint32_t destination, const uint8_t* source, size_t size) { if (destination >= STM32Lx_NVM_EEPROM_PHYS) - return stm32lx_nvm_data_write(target, destination, source, + return stm32lx_nvm_data_write(t, destination, source, size); /* Unaligned destinations. To make this feature simple to @@ -532,12 +517,12 @@ static int stm32lx_nvm_write(struct target_s* target, /* Skip stub if the MCU is in a questionable state, or if the user asks us to avoid stubs. */ volatile uint32_t regs[20]; - target_regs_read(target, ®s); + target_regs_read(t, ®s); if (inhibit_stubs || (regs[16] & 0xf)) - return stm32lx_nvm_prog_write(target, destination, source, + return stm32lx_nvm_prog_write(t, destination, source, size); - return stm32lx_nvm_prog_write_stubbed(target, destination, source, + return stm32lx_nvm_prog_write_stubbed(t, destination, source, size); } @@ -546,49 +531,46 @@ static int stm32lx_nvm_write(struct target_s* target, interface. This is slower than stubbed versions(see NOTES). The flash array is erased for all pages from addr to addr+len inclusive. NVM register file address chosen from target. */ -static int stm32lx_nvm_prog_erase(struct target_s* target, - uint32_t addr, size_t len) +static int stm32lx_nvm_prog_erase(target *t, uint32_t addr, size_t len) { - const size_t page_size = stm32lx_nvm_prog_page_size(target); - const uint32_t nvm = stm32lx_nvm_phys(target); + const size_t page_size = stm32lx_nvm_prog_page_size(t); + const uint32_t nvm = stm32lx_nvm_phys(t); /* Word align */ len += (addr & 3); addr &= ~3; - if (!stm32lx_nvm_prog_data_unlock(target, nvm)) + if (!stm32lx_nvm_prog_data_unlock(t, nvm)) return -1; /* Flash page erase instruction */ - target_mem_write32(target, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_PROG); - { - uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); - if ((pecr & (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) - != (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) - return -1; - } + uint32_t pecr = target_mem_read32(t, STM32Lx_NVM_PECR(nvm)); + if ((pecr & (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) + != (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) + return -1; /* Clear errors. Note that this only works when we wait for the NVM block to complete the last operation. */ - target_mem_write32(target, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); + target_mem_write32(t, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); while (len > 0) { /* Write first word of page to 0 */ - target_mem_write32(target, addr, 0); + target_mem_write32(t, addr, 0); len -= page_size; addr += page_size; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(target, nvm); + stm32lx_nvm_lock(t, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); - if (target_check_error(target)) + uint32_t sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); + if (target_check_error(t)) return -1; if (sr & STM32Lx_NVM_SR_BSY) continue; @@ -604,13 +586,13 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, /** Write to program flash using operations through the debug interface. This is slower than the stubbed write(see NOTES). NVM register file address chosen from target. */ -static int stm32lx_nvm_prog_write(struct target_s* target, +static int stm32lx_nvm_prog_write(target *t, uint32_t destination, const uint8_t* source_8, size_t size) { - const uint32_t nvm = stm32lx_nvm_phys(target); - const bool is_stm32l1 = stm32lx_is_stm32l1(target); + const uint32_t nvm = stm32lx_nvm_phys(t); + const bool is_stm32l1 = stm32lx_is_stm32l1(t); /* We can only handle word aligned writes and even word-multiple ranges. The stm32lx's cannot perform @@ -619,19 +601,19 @@ static int stm32lx_nvm_prog_write(struct target_s* target, if ((destination & 3) || (size & 3)) return -1; - if (!stm32lx_nvm_prog_data_unlock(target, nvm)) + if (!stm32lx_nvm_prog_data_unlock(t, nvm)) return -1; - const size_t half_page_size = stm32lx_nvm_prog_page_size(target)/2; + const size_t half_page_size = stm32lx_nvm_prog_page_size(t)/2; uint32_t* source = (uint32_t*) source_8; while (size > 0) { /* Wait for BSY to clear because we cannot write the PECR until the previous operation completes on STM32Lxxx. */ - while (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) + while (target_mem_read32(t, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_BSY) - if (target_check_error(target)) { + if (target_check_error(t)) { return -1; } @@ -639,7 +621,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, // than a half page to write if (size < half_page_size || (destination & (half_page_size - 1))) { - target_mem_write32(target, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), is_stm32l1 ? 0 : STM32Lx_NVM_PECR_PROG); @@ -650,31 +632,31 @@ static int stm32lx_nvm_prog_write(struct target_s* target, c = size; size -= c; - target_mem_write(target, destination, source, c); + target_mem_write(t, destination, source, c); source += c/4; destination += c; } // Or we are writing a half-page(s) else { - target_mem_write32(target, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_FPRG); size_t c = size & ~(half_page_size - 1); size -= c; - target_mem_write(target, destination, source, c); + target_mem_write(t, destination, source, c); source += c/4; destination += c; } } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(target, nvm); + stm32lx_nvm_lock(t, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); - if (target_check_error(target)) { + uint32_t sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); + if (target_check_error(t)) { return -1; } if (sr & STM32Lx_NVM_SR_BSY) @@ -693,45 +675,43 @@ static int stm32lx_nvm_prog_write(struct target_s* target, interface . The flash is erased for all pages from addr to addr+len, inclusive, on a word boundary. NVM register file address chosen from target. */ -static int stm32lx_nvm_data_erase(struct target_s* target, +static int stm32lx_nvm_data_erase(target *t, uint32_t addr, size_t len) { - const size_t page_size = stm32lx_nvm_data_page_size(target); - const uint32_t nvm = stm32lx_nvm_phys(target); + const size_t page_size = stm32lx_nvm_data_page_size(t); + const uint32_t nvm = stm32lx_nvm_phys(t); /* Word align */ len += (addr & 3); addr &= ~3; - if (!stm32lx_nvm_prog_data_unlock(target, nvm)) + if (!stm32lx_nvm_prog_data_unlock(t, nvm)) return -1; /* Flash data erase instruction */ - target_mem_write32(target, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA); - { - uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); - if ((pecr & (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) - != (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) - return -1; - } + uint32_t pecr = target_mem_read32(t, STM32Lx_NVM_PECR(nvm)); + if ((pecr & (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) + != (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) + return -1; while (len > 0) { /* Write first word of page to 0 */ - target_mem_write32(target, addr, 0); + target_mem_write32(t, addr, 0); len -= page_size; addr += page_size; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(target, nvm); + stm32lx_nvm_lock(t, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); - if (target_check_error(target)) + uint32_t sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); + if (target_check_error(t)) return -1; if (sr & STM32Lx_NVM_SR_BSY) continue; @@ -748,39 +728,38 @@ static int stm32lx_nvm_data_erase(struct target_s* target, NVM register file address chosen from target. Unaligned destination writes are supported (though unaligned sources are not). */ -static int stm32lx_nvm_data_write(struct target_s* target, +static int stm32lx_nvm_data_write(target *t, uint32_t destination, const uint8_t* source_8, size_t size) { - const uint32_t nvm = stm32lx_nvm_phys(target); - const bool is_stm32l1 = stm32lx_is_stm32l1(target); - uint32_t* source = (uint32_t*) source_8; + const uint32_t nvm = stm32lx_nvm_phys(t); + const bool is_stm32l1 = stm32lx_is_stm32l1(t); + uint32_t* source = (uint32_t*) source_8; - if (!stm32lx_nvm_prog_data_unlock(target, nvm)) + if (!stm32lx_nvm_prog_data_unlock(t, nvm)) return -1; - - target_mem_write32(target, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA); while (size) { size -= 4; uint32_t v = *source++; - target_mem_write32(target, destination, v); + target_mem_write32(t, destination, v); destination += 4; - if (target_check_error(target)) + if (target_check_error(t)) return -1; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(target, nvm); + stm32lx_nvm_lock(t, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); - if (target_check_error(target)) + uint32_t sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); + if (target_check_error(t)) return -1; if (sr & STM32Lx_NVM_SR_BSY) continue; -- cgit v1.2.3 From 2215e33bcfbe677092c75ba51a2a9bb6bd154884 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 29 Mar 2015 15:58:18 -0700 Subject: lmi: Clean up magic numbers, remove adiv5 links, and doc ref. --- src/lmi.c | 59 ++++++++++++++++++++++++++++------------------------------- 1 file changed, 28 insertions(+), 31 deletions(-) (limited to 'src/lmi.c') diff --git a/src/lmi.c b/src/lmi.c index 803a19e..6fe1cdb 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -21,17 +21,28 @@ /* This file implements TI/LMI LM3S target specific functions providing * the XML memory map and Flash memory programming. * - * Issues: - * No detection of the target device. - * Add reference to documentation. - * Flash erase is very slow. + * According to: TivaTM TM4C123GH6PM Microcontroller Datasheet */ #include "general.h" -#include "adiv5.h" #include "target.h" #include "cortexm.h" +#define SRAM_BASE 0x20000000 +#define BLOCK_SIZE 0x400 +#define LMI_SCB_BASE 0x400FE000 +#define LMI_SCB_DID1 (LMI_SCB_BASE + 0x004) + +#define LMI_FLASH_BASE 0x400FD000 +#define LMI_FLASH_FMA (LMI_FLASH_BASE + 0x000) +#define LMI_FLASH_FMC (LMI_FLASH_BASE + 0x008) + +#define LMI_FLASH_FMC_WRITE (1 << 0) +#define LMI_FLASH_FMC_ERASE (1 << 1) +#define LMI_FLASH_FMC_MERASE (1 << 2) +#define LMI_FLASH_FMC_COMT (1 << 3) +#define LMI_FLASH_FMC_WRKEY 0xA4420000 + static int lmi_flash_erase(target *t, uint32_t addr, size_t len); static int lmi_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len); @@ -101,7 +112,7 @@ static const uint16_t lmi_flash_write_stub[] = { bool lmi_probe(target *t) { - uint32_t did1 = target_mem_read32(t, 0x400FE004); + uint32_t did1 = target_mem_read32(t, LMI_SCB_DID1); switch (did1 >> 16) { case 0x1049: /* LM3S3748 */ t->driver = lmi_driver_str; @@ -122,32 +133,18 @@ bool lmi_probe(target *t) int lmi_flash_erase(target *t, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - uint32_t tmp; - - addr &= 0xFFFFFC00; - len &= 0xFFFFFC00; - - /* setup word access */ - adiv5_ap_write(ap, 0x00, 0xA2000052); - - /* select Flash Control */ - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, 0x04, 0x400FD000); + addr &= ~(BLOCK_SIZE - 1); + len &= ~(BLOCK_SIZE - 1); while(len) { - /* write address to FMA */ - adiv5_ap_write(ap, ADIV5_AP_DB(0), addr); /* Required to switch banks */ - /* set ERASE bit in FMC */ - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(2), 0xA4420002); - /* Read FMC to poll for ERASE bit */ - adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DB(2), 0); - do { - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, - ADIV5_AP_DB(2), 0); - } while (tmp & 2); - - len -= 0x400; - addr += 0x400; + target_mem_write32(t, LMI_FLASH_FMA, addr); + target_mem_write32(t, LMI_FLASH_FMC, + LMI_FLASH_FMC_WRKEY | LMI_FLASH_FMC_ERASE); + while (target_mem_read32(t, LMI_FLASH_FMC) & + LMI_FLASH_FMC_ERASE); + + len -= BLOCK_SIZE; + addr += BLOCK_SIZE; } return 0; } @@ -159,7 +156,7 @@ int lmi_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) data[1] = len >> 2; memcpy(&data[2], src, len); DEBUG("Sending stub\n"); - target_mem_write(t, 0x20000000, (void*)lmi_flash_write_stub, 0x30); + target_mem_write(t, SRAM_BASE, lmi_flash_write_stub, 0x30); DEBUG("Sending data\n"); target_mem_write(t, 0x20000030, data, len + 8); DEBUG("Running stub\n"); -- cgit v1.2.3 From cac286d3985c531fb5d96dc5315530e313212c17 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 29 Mar 2015 16:20:57 -0700 Subject: lmi: Use generated stub with cortexm_run_stub. --- flashstub/lmi.stub | 1 + src/lmi.c | 53 ++++++++--------------------------------------------- 2 files changed, 9 insertions(+), 45 deletions(-) create mode 100644 flashstub/lmi.stub (limited to 'src/lmi.c') diff --git a/flashstub/lmi.stub b/flashstub/lmi.stub new file mode 100644 index 0000000..afaf939 --- /dev/null +++ b/flashstub/lmi.stub @@ -0,0 +1 @@ +0x4809, 0x490B, 0x467A, 0x3230, 0x4B0A, 0x4D08, 0xB15B, 0x6001, 0x6814, 0x6044, 0x6085, 0x6884, 0x2601, 0x4234, 0xD1FB, 0x3B01, 0x3104, 0x3204, 0xE7F2, 0xBE00, 0xD000, 0x400F, 0x0001, 0xA442, 0x0000, 0x0000, 0x0004, 0x0000, 0x6548, 0x6C6C, 0x206F, 0x6F57, 0x6C72, 0x2164, 0x000A, 0x0000, 0x0000, diff --git a/src/lmi.c b/src/lmi.c index 6fe1cdb..fb425a2 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -29,7 +29,10 @@ #include "cortexm.h" #define SRAM_BASE 0x20000000 +#define STUB_BUFFER_BASE (SRAM_BASE + 0x30) + #define BLOCK_SIZE 0x400 + #define LMI_SCB_BASE 0x400FE000 #define LMI_SCB_DID1 (LMI_SCB_BASE + 0x004) @@ -73,41 +76,7 @@ static const char tm4c123gh6pm_xml_memory_map[] = "" static const uint16_t lmi_flash_write_stub[] = { -// _start: - 0x4809, // ldr r0, [pc, #36] // _flashbase - 0x490b, // ldr r1, [pc, #44] // _addr - 0x467a, // mov r2, pc - 0x3230, // adds r2, #48 - 0x4b0a, // ldr r3, [pc, #40] // _size - 0x4d08, // ldr r5, [pc, #32] // _flash_write_cmd -// _next: - 0xb15b, // cbz r3, _done - 0x6001, // str r1, [r0, #0] - 0x6814, // ldr r4, [r2] - 0x6044, // str r4, [r0, #4] - 0x6085, // str r5, [r0, #8] -// _wait: - 0x6884, // ldr r4, [r0, #8] - 0x2601, // movs r6, #1 - 0x4234, // tst r4, r6 - 0xd1fb, // bne _wait - - 0x3b01, // subs r3, #1 - 0x3104, // adds r1, #4 - 0x3204, // adds r2, #4 - 0xe7f2, // b _next -// _done: - 0xbe00, // bkpt -// _flashbase: - 0xd000, 0x400f, // .word 0x400fd000 -// _flash_write_cmd: - 0x0001, 0xa442, // .word 0xa4420001 -// _addr: -// 0x0000, 0x0000, -// _size: -// 0x0000, 0x0000, -// _data: -// ... +#include "../flashstub/lmi.stub" }; bool lmi_probe(target *t) @@ -155,16 +124,10 @@ int lmi_flash_write(target *t, uint32_t dest, const uint8_t *src, size_t len) data[0] = dest; data[1] = len >> 2; memcpy(&data[2], src, len); - DEBUG("Sending stub\n"); - target_mem_write(t, SRAM_BASE, lmi_flash_write_stub, 0x30); - DEBUG("Sending data\n"); - target_mem_write(t, 0x20000030, data, len + 8); - DEBUG("Running stub\n"); - cortexm_pc_write(t, 0x20000000); - target_halt_resume(t, 0); - DEBUG("Waiting for halt\n"); - while(!target_halt_wait(t)); - return 0; + target_mem_write(t, SRAM_BASE, lmi_flash_write_stub, + sizeof(lmi_flash_write_stub)); + target_mem_write(t, STUB_BUFFER_BASE, data, len + 8); + return cortexm_run_stub(t, SRAM_BASE, 0, 0, 0, 0); } -- cgit v1.2.3