From 8c877d6dfa5aff2b70ce2c96ef6314bcae7a25c2 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Mon, 17 Jun 2013 15:53:32 +1200 Subject: Fix trailing whitespace everywhere. --- src/include/adiv5.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/include/adiv5.h') diff --git a/src/include/adiv5.h b/src/include/adiv5.h index d2d4be0..1bfb5a1 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -111,7 +111,7 @@ typedef struct ADIv5_DP_s { uint32_t (*error)(struct ADIv5_DP_s *dp); - uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t APnDP, uint8_t RnW, + uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t APnDP, uint8_t RnW, uint8_t addr, uint32_t value); union { @@ -135,7 +135,7 @@ static inline uint32_t adiv5_dp_error(ADIv5_DP_t *dp) return dp->error(dp); } -static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t APnDP, +static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t APnDP, uint8_t RnW, uint8_t addr, uint32_t value) { return dp->low_access(dp, APnDP, RnW, addr, value); -- cgit v1.2.3 From d8f737fc53fa27bb13a934f94e39157748401ce4 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Wed, 19 Jun 2013 21:05:53 +1200 Subject: Disable ADIv5 timeout while target is running. --- src/adiv5_jtagdp.c | 6 +++++- src/adiv5_swdp.c | 4 ++-- src/cortexm.c | 4 ++++ src/include/adiv5.h | 2 ++ 4 files changed, 13 insertions(+), 3 deletions(-) (limited to 'src/include/adiv5.h') diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index 693b94e..4306101 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -92,10 +92,14 @@ static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t R jtag_dev_write_ir(dp->dev, APnDP?IR_APACC:IR_DPACC); + int tries = 1000; do { jtag_dev_shift_dr(dp->dev, (uint8_t*)&response, (uint8_t*)&request, 35); ack = response & 0x07; - } while(ack == JTAGDP_ACK_WAIT); + } while(--tries && (ack == JTAGDP_ACK_WAIT)); + + if (dp->allow_timeout && (ack == JTAGDP_ACK_WAIT)) + return 0; if((ack != JTAGDP_ACK_OK)) { /* Fatal error if invalid ACK response */ diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index 839127d..c021190 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -135,8 +135,8 @@ static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW ack = swdptap_seq_in(3); } while(--tries && ack == SWDP_ACK_WAIT); - if(!tries) - PLATFORM_FATAL_ERROR(1); + if (dp->allow_timeout && (ack == SWDP_ACK_WAIT)) + return 0; if(ack == SWDP_ACK_FAULT) { dp->fault = 1; diff --git a/src/cortexm.c b/src/cortexm.c index 7819598..a8bb34b 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -584,6 +584,7 @@ cortexm_halt_request(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); + ap->dp->allow_timeout = false; adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN); } @@ -596,6 +597,8 @@ cortexm_halt_wait(struct target_s *target) if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) return 0; + ap->dp->allow_timeout = false; + /* We've halted. Let's find out why. */ uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR); adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */ @@ -654,6 +657,7 @@ cortexm_halt_resume(struct target_s *target, bool step) } adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr); + ap->dp->allow_timeout = true; } static int cortexm_fault_unwind(struct target_s *target) diff --git a/src/include/adiv5.h b/src/include/adiv5.h index 1bfb5a1..64b6a28 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -106,6 +106,8 @@ typedef struct ADIv5_DP_s { uint32_t idcode; + bool allow_timeout; + void (*dp_write)(struct ADIv5_DP_s *dp, uint8_t addr, uint32_t value); uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint8_t addr); -- cgit v1.2.3 From 9c5ffd61f7d654418c76015f0073e4accbf9e004 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Tue, 6 Jan 2015 22:26:00 +1300 Subject: First cut at Freescale Kinetis support. --- src/Makefile | 1 + src/adiv5.c | 20 +++++++ src/cortexm.c | 1 + src/include/adiv5.h | 2 + src/include/target.h | 1 + src/kinetis.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 179 insertions(+) create mode 100644 src/kinetis.c (limited to 'src/include/adiv5.h') diff --git a/src/Makefile b/src/Makefile index 62cc617..b30922c 100644 --- a/src/Makefile +++ b/src/Makefile @@ -27,6 +27,7 @@ SRC = \ lmi.c \ lpc11xx.c \ lpc43xx.c \ + kinetis.c \ main.c \ nrf51.c \ platform.c \ diff --git a/src/adiv5.c b/src/adiv5.c index e7f45c9..6dcc919 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -414,6 +414,26 @@ void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value) adiv5_ap_write(ap, ADIV5_AP_DRW, v); } +uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr) +{ + adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | + ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); + adiv5_ap_write(ap, ADIV5_AP_TAR, addr); + uint32_t v = adiv5_ap_read(ap, ADIV5_AP_DRW); + + return v >> ((addr & 3) * 8); +} + +void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value) +{ + uint32_t v = value << ((addr & 3) * 8); + + adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | + ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); + adiv5_ap_write(ap, ADIV5_AP_TAR, addr); + adiv5_ap_write(ap, ADIV5_AP_DRW, v); +} + void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value) { adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, diff --git a/src/cortexm.c b/src/cortexm.c index 3ac960c..731632e 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -386,6 +386,7 @@ cortexm_probe(struct target_s *target) PROBE(nrf51_probe); PROBE(samd20_probe); PROBE(lmi_probe); + PROBE(kinetis_probe); #undef PROBE return true; diff --git a/src/include/adiv5.h b/src/include/adiv5.h index 64b6a28..0f17119 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -172,6 +172,8 @@ uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr); void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value); uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr); void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value); +uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr); +void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value); void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value); uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint8_t addr); diff --git a/src/include/target.h b/src/include/target.h index f28f2f8..100c4a0 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -225,6 +225,7 @@ bool lpc43xx_probe(struct target_s *target); bool sam3x_probe(struct target_s *target); bool nrf51_probe(struct target_s *target); bool samd20_probe(struct target_s *target); +bool kinetis_probe(struct target_s *target); #endif diff --git a/src/kinetis.c b/src/kinetis.c new file mode 100644 index 0000000..393bb18 --- /dev/null +++ b/src/kinetis.c @@ -0,0 +1,154 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2015 Black Sphere Technologies Ltd. + * Written by Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* This file implements KL25 target specific functions providing + * the XML memory map and Flash memory programming. + */ + +#include +#include + +#include "general.h" +#include "adiv5.h" +#include "target.h" + +#define SIM_SDID 0x40048024 + +#define FTFA_BASE 0x40020000 +#define FTFA_FSTAT (FTFA_BASE + 0x00) +#define FTFA_FCNFG (FTFA_BASE + 0x01) +#define FTFA_FSEC (FTFA_BASE + 0x02) +#define FTFA_FOPT (FTFA_BASE + 0x03) +#define FTFA_FCCOB(x) (FTFA_BASE + 0x04 + ((x) ^ 3)) + +#define FTFA_FSTAT_CCIF (1 << 7) +#define FTFA_FSTAT_RDCOLERR (1 << 6) +#define FTFA_FSTAT_ACCERR (1 << 5) +#define FTFA_FSTAT_FPVIOL (1 << 4) +#define FTFA_FSTAT_MGSTAT0 (1 << 0) + +#define FTFA_CMD_CHECK_ERASE 0x01 +#define FTFA_CMD_PROGRAM_CHECK 0x02 +#define FTFA_CMD_READ_RESOURCE 0x03 +#define FTFA_CMD_PROGRAM_LONGWORD 0x06 +#define FTFA_CMD_ERASE_SECTOR 0x09 +#define FTFA_CMD_CHECK_ERASE_ALL 0x40 +#define FTFA_CMD_READ_ONCE 0x41 +#define FTFA_CMD_PROGRAM_ONCE 0x43 +#define FTFA_CMD_ERASE_ALL 0x44 +#define FTFA_CMD_BACKDOOR_ACCESS 0x45 + +#define KL25_PAGESIZE 0x400 + +static int kl25_flash_erase(struct target_s *target, uint32_t addr, int len); +static int kl25_flash_write(struct target_s *target, uint32_t dest, + const uint8_t *src, int len); + +static const char kl25_xml_memory_map[] = "" +/* ""*/ + "" + " " + " 0x400" + " " + " " + " " + ""; + +bool kinetis_probe(struct target_s *t) +{ + uint32_t sdid = adiv5_ap_mem_read(adiv5_target_ap(t), SIM_SDID); + switch (sdid >> 20) { + case 0x251: + t->driver = "KL25"; + t->xml_mem_map = kl25_xml_memory_map; + t->flash_erase = kl25_flash_erase; + t->flash_write = kl25_flash_write; + return true; + } + return false; +} + +static bool +kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[8]) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + uint8_t fstat; + + /* Wait for CCIF to be high */ + do { + fstat = adiv5_ap_mem_read_byte(ap, FTFA_FSTAT); + /* Check ACCERR and FPVIOL are zero in FSTAT */ + if (fstat & (FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL)) + return false; + } while (!(fstat & FTFA_FSTAT_CCIF)); + + /* Write command to FCCOB */ + addr &= 0xffffff; + addr |= (uint32_t)cmd << 24; + adiv5_ap_mem_write(ap, FTFA_FCCOB(0), addr); + if (data) { + adiv5_ap_mem_write(ap, FTFA_FCCOB(4), *(uint32_t*)&data[0]); + adiv5_ap_mem_write(ap, FTFA_FCCOB(8), *(uint32_t*)&data[4]); + } + + /* Enable execution by clearing CCIF */ + adiv5_ap_mem_write_byte(ap, FTFA_FSTAT, FTFA_FSTAT_CCIF); + + /* Wait for execution to complete */ + do { + fstat = adiv5_ap_mem_read_byte(ap, FTFA_FSTAT); + /* Check ACCERR and FPVIOL are zero in FSTAT */ + if (fstat & (FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL)) + return false; + } while (!(fstat & FTFA_FSTAT_CCIF)); + + return true; +} + +static int kl25_flash_erase(struct target_s *t, uint32_t addr, int len) +{ + addr &= ~(KL25_PAGESIZE - 1); + len = (len + KL25_PAGESIZE - 1) & ~(KL25_PAGESIZE - 1); + + while (len) { + kl25_command(t, FTFA_CMD_ERASE_SECTOR, addr, NULL); + len -= KL25_PAGESIZE; + addr += KL25_PAGESIZE; + } + return 0; +} + +static int kl25_flash_write(struct target_s *t, uint32_t dest, + const uint8_t *src, int len) +{ + /* FIXME handle misaligned start and end of sections */ + if ((dest & 3) || (len & 3)) + return -1; + + while (len) { + kl25_command(t, FTFA_CMD_PROGRAM_LONGWORD, dest, src); + len -= 4; + dest += 4; + src += 4; + } + return 0; +} -- cgit v1.2.3 From 4d4813de87721528fc9a06174dd1da5c245ae2f3 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 1 Mar 2015 22:16:04 -0800 Subject: Clean up includes everywhere. All source files include general.h first and before anything else. This inlcludes platform.h and platform_support.h No header file needs to include to include any of these, but should include any others needed for it's own declarations.--- src/adiv5.c | 5 ---- src/adiv5_jtagdp.c | 3 --- src/adiv5_swdp.c | 5 ---- src/arm7tdmi.c | 4 ---- src/command.c | 6 ----- src/cortexm.c | 7 ++---- src/crc32.c | 2 +- src/gdb_main.c | 11 --------- src/gdb_packet.c | 9 ++------ src/hex_utils.c | 4 +--- src/include/adiv5.h | 1 - src/include/arm7tdmi.h | 1 - src/include/command.h | 1 - src/include/cortexm.h | 20 ++++++++++++++++ src/include/crc32.h | 2 -- src/include/gdb_packet.h | 2 -- src/include/general.h | 12 +++++++--- src/include/jtag_scan.h | 2 -- src/include/jtagtap.h | 2 -- src/include/morse.h | 2 -- src/include/platform_support.h | 41 +++++++++++++++++++++++++++++++++ src/include/swdptap.h | 2 -- src/include/target.h | 2 -- src/jtag_scan.c | 7 ------ src/kinetis.c | 3 --- src/lmi.c | 3 --- src/lpc11xx.c | 21 +++++++++++++---- src/lpc43xx.c | 5 +--- src/main.c | 10 +++----- src/nrf51.c | 3 --- src/platforms/common/usbuart.h | 1 - src/platforms/f4discovery/platform.c | 22 +++++------------- src/platforms/f4discovery/platform.h | 14 ++--------- src/platforms/f4discovery/usbdfu.c | 6 ++--- src/platforms/launchpad-icdi/platform.c | 11 ++++----- src/platforms/launchpad-icdi/platform.h | 16 +------------ src/platforms/libftdi/jtagtap.c | 1 + src/platforms/libftdi/platform.c | 15 +++--------- src/platforms/libftdi/platform.h | 5 ---- src/platforms/libftdi/swdptap.c | 2 +- src/platforms/native/platform.c | 22 ++++-------------- src/platforms/native/platform.h | 22 ++---------------- src/platforms/stlink/platform.c | 22 ++++-------------- src/platforms/stlink/platform.h | 16 ++++--------- src/platforms/stm32/cdcacm.c | 2 +- src/platforms/stm32/dfu_f1.c | 5 ++-- src/platforms/stm32/dfu_f4.c | 6 ++--- src/platforms/stm32/dfucore.c | 2 +- src/platforms/stm32/gdb_if.c | 2 +- src/platforms/stm32/gpio.h | 10 ++++++++ src/platforms/stm32/jtagtap.c | 2 -- src/platforms/stm32/traceswo.c | 5 +--- src/platforms/stm32/usbuart.c | 2 +- src/platforms/swlink/platform.c | 21 ++++------------- src/platforms/swlink/platform.h | 16 ++----------- src/platforms/tm4c/cdcacm.c | 2 +- src/platforms/tm4c/gdb_if.c | 6 +++-- src/platforms/tm4c/jtagtap.c | 1 + src/platforms/tm4c/swdptap.c | 1 - src/platforms/tm4c/traceswo.c | 5 ---- src/platforms/tm4c/usbuart.c | 4 ++-- src/sam3x.c | 3 --- src/samd.c | 4 ---- src/stm32f1.c | 3 --- src/stm32f4.c | 3 --- src/stm32l1.c | 3 --- src/target.c | 2 -- 67 files changed, 167 insertions(+), 316 deletions(-) create mode 100644 src/include/platform_support.h (limited to 'src/include/adiv5.h') diff --git a/src/adiv5.c b/src/adiv5.c index 6dcc919..361cd75 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -25,15 +25,10 @@ * Currently doesn't use ROM table for introspection, just assumes * the device is Cortex-M3. */ - -#include -#include - #include "general.h" #include "jtag_scan.h" #include "gdb_packet.h" #include "adiv5.h" - #include "target.h" #ifndef DO_RESET_SEQ diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index fd77a04..8f62a11 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -23,14 +23,11 @@ */ #include "general.h" -#include "platform.h" #include "adiv5.h" #include "jtag_scan.h" #include "jtagtap.h" #include "morse.h" -#include - #define JTAGDP_ACK_OK 0x02 #define JTAGDP_ACK_WAIT 0x01 diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index 6bafc91..9df362f 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -23,17 +23,12 @@ */ #include "general.h" -#include "platform.h" #include "adiv5.h" - #include "swdptap.h" #include "jtagtap.h" - #include "command.h" #include "morse.h" -#include - #define SWDP_ACK_OK 0x01 #define SWDP_ACK_WAIT 0x02 #define SWDP_ACK_FAULT 0x04 diff --git a/src/arm7tdmi.c b/src/arm7tdmi.c index 1c7b443..1721787 100644 --- a/src/arm7tdmi.c +++ b/src/arm7tdmi.c @@ -24,14 +24,10 @@ */ #include "general.h" -#include "platform.h" #include "target.h" #include "jtag_scan.h" #include "jtagtap.h" -#include -#include - /* TODO: * Skeleton target. * EmbeddedICE registers, halt/resume target. diff --git a/src/command.c b/src/command.c index 7c17864..f271085 100644 --- a/src/command.c +++ b/src/command.c @@ -22,18 +22,12 @@ * commands. */ -#include -#include - #include "general.h" - #include "command.h" #include "gdb_packet.h" - #include "jtag_scan.h" #include "target.h" #include "morse.h" - #include "adiv5.h" #ifdef PLATFORM_HAS_TRACESWO diff --git a/src/cortexm.c b/src/cortexm.c index 12914d3..a016342 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -28,11 +28,6 @@ * Issues: * There are way too many magic numbers used here. */ -#include -#include -#include -#include - #include "general.h" #include "jtagtap.h" #include "jtag_scan.h" @@ -42,6 +37,8 @@ #include "gdb_packet.h" #include "cortexm.h" +#include + static char cortexm_driver_str[] = "ARM Cortex-M"; static bool cortexm_vector_catch(target *t, int argc, char *argv[]); diff --git a/src/crc32.c b/src/crc32.c index 810a9dd..42d1d48 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -18,7 +18,7 @@ * along with this program. If not, see . */ -#include "platform.h" +#include "general.h" #include "target.h" #if !defined(STM32F1) && !defined(STM32F4) diff --git a/src/gdb_main.c b/src/gdb_main.c index 41ab84a..17ad9a5 100644 --- a/src/gdb_main.c +++ b/src/gdb_main.c @@ -24,26 +24,15 @@ * Originally written for GDB 6.8, updated and tested with GDB 7.2. */ -#include -#include -#include - -#include - -#include "platform.h" - #include "general.h" #include "hex_utils.h" #include "gdb_if.h" #include "gdb_packet.h" #include "gdb_main.h" - #include "jtagtap.h" #include "jtag_scan.h" #include "adiv5.h" - #include "target.h" - #include "command.h" #include "crc32.h" diff --git a/src/gdb_packet.c b/src/gdb_packet.c index d43be42..4dc934f 100644 --- a/src/gdb_packet.c +++ b/src/gdb_packet.c @@ -22,18 +22,13 @@ * reception and transmission as well as some convenience functions. */ -#define _GNU_SOURCE -#include -#include -#include - -#include - #include "general.h" #include "gdb_if.h" #include "gdb_packet.h" #include "hex_utils.h" +#include + int gdb_getpacket(unsigned char *packet, int size) { diff --git a/src/hex_utils.c b/src/hex_utils.c index e477281..45382ff 100644 --- a/src/hex_utils.c +++ b/src/hex_utils.c @@ -21,9 +21,7 @@ /* Convenience function to convert to/from ascii strings of hex digits. */ -#include -#include - +#include "general.h" #include "hex_utils.h" static char hexdigits[] = "0123456789abcdef"; diff --git a/src/include/adiv5.h b/src/include/adiv5.h index 0f17119..e0ce9cf 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -21,7 +21,6 @@ #ifndef __ADIV5_H #define __ADIV5_H -#include "general.h" #include "jtag_scan.h" #include "target.h" diff --git a/src/include/arm7tdmi.h b/src/include/arm7tdmi.h index ffcd6e9..fa7d586 100644 --- a/src/include/arm7tdmi.h +++ b/src/include/arm7tdmi.h @@ -21,7 +21,6 @@ #ifndef __ARM7TDMI_H #define __ARM7TDMI_H -#include "general.h" #include "jtag_scan.h" void arm7tdmi_jtag_handler(jtag_dev_t *dev); diff --git a/src/include/command.h b/src/include/command.h index 32b0d7b..3910bbb 100644 --- a/src/include/command.h +++ b/src/include/command.h @@ -21,7 +21,6 @@ #ifndef __COMMAND_H #define __COMMAND_H -#include "general.h" #include "target.h" int command_process(target *t, char *cmd); diff --git a/src/include/cortexm.h b/src/include/cortexm.h index f1fc07a..1fd77e6 100644 --- a/src/include/cortexm.h +++ b/src/include/cortexm.h @@ -1,6 +1,26 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2015 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #ifndef __CORTEXM_H #define __CORTEXM_H +#include "target.h" + /* Private peripheral bus base address */ #define CORTEXM_PPB_BASE 0xE0000000 diff --git a/src/include/crc32.h b/src/include/crc32.h index 6cc00ea..9966d8d 100644 --- a/src/include/crc32.h +++ b/src/include/crc32.h @@ -21,8 +21,6 @@ #ifndef __CRC32_H #define __CRC32_H -#include "platform.h" - uint32_t crc32_calc(uint32_t crc, uint8_t data); uint32_t generic_crc32(struct target_s *target, uint32_t base, int len); diff --git a/src/include/gdb_packet.h b/src/include/gdb_packet.h index 9f5430f..222b86d 100644 --- a/src/include/gdb_packet.h +++ b/src/include/gdb_packet.h @@ -21,8 +21,6 @@ #ifndef __GDB_PACKET_H #define __GDB_PACKET_H -#include - int gdb_getpacket(unsigned char *packet, int size); void gdb_putpacket(unsigned char *packet, int size); #define gdb_putpacketz(packet) gdb_putpacket((packet), strlen(packet)) diff --git a/src/include/general.h b/src/include/general.h index b0721ac..b4e9aeb 100644 --- a/src/include/general.h +++ b/src/include/general.h @@ -21,15 +21,21 @@ #ifndef __GENERAL_H #define __GENERAL_H +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include + #include "platform.h" +#include "platform_support.h" #ifndef DEBUG #include #define DEBUG printf #endif -#include -#include - #endif diff --git a/src/include/jtag_scan.h b/src/include/jtag_scan.h index b425b95..aa006e7 100644 --- a/src/include/jtag_scan.h +++ b/src/include/jtag_scan.h @@ -21,8 +21,6 @@ #ifndef __JTAG_SCAN_H #define __JTAG_SCAN_H -#include "general.h" - #define JTAG_MAX_DEVS 5 #define JTAG_MAX_IR_LEN 16 diff --git a/src/include/jtagtap.h b/src/include/jtagtap.h index fd13f2b..0072594 100644 --- a/src/include/jtagtap.h +++ b/src/include/jtagtap.h @@ -21,8 +21,6 @@ #ifndef __JTAGTAP_H #define __JTAGTAP_H -#include "general.h" - /* Note: Signal names are as for the device under test. */ int jtagtap_init(void); diff --git a/src/include/morse.h b/src/include/morse.h index ac53893..5ba39b1 100644 --- a/src/include/morse.h +++ b/src/include/morse.h @@ -21,8 +21,6 @@ #ifndef __MORSE_H #define __MORSE_H -#include - extern const char *morse_msg; void morse(const char *msg, char repeat); diff --git a/src/include/platform_support.h b/src/include/platform_support.h new file mode 100644 index 0000000..cc88ab6 --- /dev/null +++ b/src/include/platform_support.h @@ -0,0 +1,41 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2015 Gareth McMullin + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __PLATFORM_SUPPORT_H +#define __PLATFORM_SUPPORT_H + +#ifndef __GENERAL_H +# error "Include 'general.h' instead" +#endif + +#if defined(LIBFTDI) +void platform_init(int argc, char **argv); +#else +void platform_init(void); +#endif + +const char *platform_target_voltage(void); +int platform_hwversion(void); +void platform_delay(uint32_t delay); +void platform_srst_set_val(bool assert); +bool platform_target_get_power(void); +void platform_target_set_power(bool power); + +#endif + diff --git a/src/include/swdptap.h b/src/include/swdptap.h index 5bb0545..3263a1d 100644 --- a/src/include/swdptap.h +++ b/src/include/swdptap.h @@ -21,8 +21,6 @@ #ifndef __SWDPTAP_H #define __SWDPTAP_H -#include "general.h" - int swdptap_init(void); void swdptap_reset(void); diff --git a/src/include/target.h b/src/include/target.h index 50f1ebe..0e6d9c2 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -25,8 +25,6 @@ #ifndef __TARGET_H #define __TARGET_H -#include "general.h" - typedef struct target_s target; /* The destroy callback function will be called by target_list_free() just diff --git a/src/jtag_scan.c b/src/jtag_scan.c index 257e6c4..208a1db 100644 --- a/src/jtag_scan.c +++ b/src/jtag_scan.c @@ -22,19 +22,12 @@ * to detect devices on the scan chain and read their IDCODEs. * It depends on the low-level function provided by the platform's jtagtap.c. */ -#include -#include -#include - -#include #include "general.h" #include "jtagtap.h" #include "morse.h" #include "jtag_scan.h" - #include "gdb_packet.h" - #include "adiv5.h" #include "arm7tdmi.h" diff --git a/src/kinetis.c b/src/kinetis.c index 393bb18..4b7cf31 100644 --- a/src/kinetis.c +++ b/src/kinetis.c @@ -22,9 +22,6 @@ * the XML memory map and Flash memory programming. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/lmi.c b/src/lmi.c index a251242..8d409d0 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -27,9 +27,6 @@ * Flash erase is very slow. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/lpc11xx.c b/src/lpc11xx.c index ef26e78..d9e918e 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -1,8 +1,19 @@ - -#include -#include -#include - +/* + * This file is part of the Black Magic Debug project. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/lpc43xx.c b/src/lpc43xx.c index bfb96f7..3940fed 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -17,11 +17,8 @@ * along with this program. If not, see . */ -#include -#include -#include -#include "command.h" #include "general.h" +#include "command.h" #include "adiv5.h" #include "target.h" #include "gdb_packet.h" diff --git a/src/main.c b/src/main.c index 809d4bf..60db15c 100644 --- a/src/main.c +++ b/src/main.c @@ -22,26 +22,22 @@ * protocol loop. */ -#include -#include -#include - +#include "general.h" #include "gdb_if.h" #include "gdb_main.h" #include "jtagtap.h" #include "jtag_scan.h" - #include "target.h" int main(int argc, char **argv) { #if defined(LIBFTDI) - assert(platform_init(argc, argv) == 0); + platform_init(argc, argv); #else (void) argc; (void) argv; - assert(platform_init() == 0); + platform_init(); #endif PLATFORM_SET_FATAL_ERROR_RECOVERY(); diff --git a/src/nrf51.c b/src/nrf51.c index 7305d29..6c1a8b9 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -21,9 +21,6 @@ * the device, providing the XML memory map and Flash memory programming. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/platforms/common/usbuart.h b/src/platforms/common/usbuart.h index 39f7dcd..51f5702 100644 --- a/src/platforms/common/usbuart.h +++ b/src/platforms/common/usbuart.h @@ -22,7 +22,6 @@ #include #include -#include "general.h" void usbuart_init(void); diff --git a/src/platforms/f4discovery/platform.c b/src/platforms/f4discovery/platform.c index e051564..cf6cdf3 100644 --- a/src/platforms/f4discovery/platform.c +++ b/src/platforms/f4discovery/platform.c @@ -22,7 +22,11 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" +#include "morse.h" + #include #include #include @@ -32,16 +36,12 @@ #include #include -#include "jtag_scan.h" -#include "usbuart.h" -#include "morse.h" - uint8_t running_status; volatile uint32_t timeout_counter; jmp_buf fatal_error_jmpbuf; -int platform_init(void) +void platform_init(void) { /* Check the USER button*/ rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN); @@ -86,17 +86,7 @@ int platform_init(void) systick_counter_enable(); usbuart_init(); - cdcacm_init(); - - // Set recovery point - if (setjmp(fatal_error_jmpbuf)) { - return 0; // Do nothing on failure - } - - jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/f4discovery/platform.h b/src/platforms/f4discovery/platform.h index 140e8d1..f58205d 100644 --- a/src/platforms/f4discovery/platform.h +++ b/src/platforms/f4discovery/platform.h @@ -24,19 +24,12 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include -#include -#include -#include -#include - -#include -#include - #include "gdb_packet.h" #include "gpio.h" #include "morse.h" +#include + #define PLATFORM_HAS_TRACESWO #define BOARD_IDENT "Black Magic Probe (F4Discovery), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade) for F4Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -173,9 +166,6 @@ extern jmp_buf fatal_error_jmpbuf; longjmp(fatal_error_jmpbuf, (error)); \ } -int platform_init(void); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); static inline int platform_hwversion(void) { return 0; diff --git a/src/platforms/f4discovery/usbdfu.c b/src/platforms/f4discovery/usbdfu.c index 7070ade..6a40295 100644 --- a/src/platforms/f4discovery/usbdfu.c +++ b/src/platforms/f4discovery/usbdfu.c @@ -17,14 +17,14 @@ * along with this program. If not, see . */ -#include +#include "general.h" +#include "usbdfu.h" + #include #include #include #include -#include "usbdfu.h" - void dfu_detach(void) { /* USB device must detach, we just reset... */ diff --git a/src/platforms/launchpad-icdi/platform.c b/src/platforms/launchpad-icdi/platform.c index 1e66e12..0e3fb85 100644 --- a/src/platforms/launchpad-icdi/platform.c +++ b/src/platforms/launchpad-icdi/platform.c @@ -1,5 +1,6 @@ -#include "platform.h" +#include "general.h" #include "gdb_if.h" +#include "cdcacm.h" #include "usbuart.h" #include @@ -26,14 +27,14 @@ void sys_tick_handler(void) trace_tick(); } -int +void platform_init(void) { int i; for(i=0; i<1000000; i++); rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLL_DIV_80MHZ); - + // Enable all JTAG ports and set pins to output periph_clock_enable(RCC_GPIOA); periph_clock_enable(RCC_GPIOB); @@ -59,10 +60,6 @@ platform_init(void) usbuart_init(); cdcacm_init(); - - //jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/launchpad-icdi/platform.h b/src/platforms/launchpad-icdi/platform.h index 8c343a8..5f686f4 100644 --- a/src/platforms/launchpad-icdi/platform.h +++ b/src/platforms/launchpad-icdi/platform.h @@ -1,16 +1,13 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include +#include "gdb_packet.h" #include -#include #include #include -#include "gdb_packet.h" - #define CDCACM_PACKET_SIZE 64 #define BOARD_IDENT "Black Magic Probe (Launchpad ICDI), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade) for Launchpad, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -110,8 +107,6 @@ extern usbd_driver lm4f_usb_driver; #define PLATFORM_HAS_TRACESWO -int platform_init(void); - inline static void gpio_set_val(uint32_t port, uint8_t pin, uint8_t val) { gpio_write(port, pin, val == 0 ? 0 : 0xff); } @@ -120,15 +115,6 @@ inline static uint8_t gpio_get(uint32_t port, uint8_t pin) { return !(gpio_read(port, pin) == 0); } -void platform_delay(uint32_t delay); -const char *platform_target_voltage(void); - -/* */ -void cdcacm_init(void); -/* Returns current usb configuration, or 0 if not configured. */ -int cdcacm_get_config(void); -int cdcacm_get_dtr(void); - #define disconnect_usb() do { usbd_disconnect(usbdev,1); nvic_disable_irq(USB_IRQ);} while(0) #define setup_vbus_irq() diff --git a/src/platforms/libftdi/jtagtap.c b/src/platforms/libftdi/jtagtap.c index 91f6ae2..c9bc876 100644 --- a/src/platforms/libftdi/jtagtap.c +++ b/src/platforms/libftdi/jtagtap.c @@ -69,6 +69,7 @@ void jtagtap_reset(void) void jtagtap_srst(bool assert) { + (void)assert; platform_buffer_flush(); //ftdi_write_data(ftdic, "\x80\x88\xAB", 3); //usleep(1000); diff --git a/src/platforms/libftdi/platform.c b/src/platforms/libftdi/platform.c index 723efa3..e53f011 100644 --- a/src/platforms/libftdi/platform.c +++ b/src/platforms/libftdi/platform.c @@ -17,14 +17,10 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#include "platform.h" +#include "general.h" #include "gdb_if.h" -#include "jtag_scan.h" -#include -#include #include -#include struct ftdi_context *ftdic; @@ -121,7 +117,7 @@ static struct cable_desc_s { }, }; -int platform_init(int argc, char **argv) +void platform_init(int argc, char **argv) { int err; int c; @@ -149,7 +145,7 @@ int platform_init(int argc, char **argv) if (index == sizeof(cable_desc)/sizeof(cable_desc[0])){ fprintf(stderr, "No cable matching %s found\n",cablename); - return -1; + exit(-1); } if (cable_desc[index].dbus_data) @@ -212,12 +208,7 @@ int platform_init(int argc, char **argv) } assert(ftdi_write_data(ftdic, ftdi_init, 9) == 9); - assert(gdb_if_init() == 0); - - jtag_scan(NULL); - - return 0; } void platform_buffer_flush(void) diff --git a/src/platforms/libftdi/platform.h b/src/platforms/libftdi/platform.h index a95a3f4..135b2e3 100644 --- a/src/platforms/libftdi/platform.h +++ b/src/platforms/libftdi/platform.h @@ -21,7 +21,6 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include #include #ifndef WIN32 @@ -42,10 +41,6 @@ extern struct ftdi_context *ftdic; -int platform_init(int argc, char **argv); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); - void platform_buffer_flush(void); int platform_buffer_write(const uint8_t *data, int size); int platform_buffer_read(uint8_t *data, int size); diff --git a/src/platforms/libftdi/swdptap.c b/src/platforms/libftdi/swdptap.c index ef350de..eb6e65e 100644 --- a/src/platforms/libftdi/swdptap.c +++ b/src/platforms/libftdi/swdptap.c @@ -26,7 +26,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "swdptap.h" static void swdptap_turnaround(uint8_t dir); diff --git a/src/platforms/native/platform.c b/src/platforms/native/platform.c index 3f61f5f..9b39238 100644 --- a/src/platforms/native/platform.c +++ b/src/platforms/native/platform.c @@ -22,7 +22,10 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" +#include "morse.h" #include #include @@ -33,11 +36,6 @@ #include #include -#include "jtag_scan.h" -#include "cdcacm.h" -#include "usbuart.h" -#include "morse.h" - uint8_t running_status; volatile uint32_t timeout_counter; @@ -62,7 +60,7 @@ int platform_hwversion(void) return hwversion; } -int platform_init(void) +void platform_init(void) { rcc_clock_setup_in_hse_8mhz_out_72mhz(); @@ -136,16 +134,6 @@ int platform_init(void) cdcacm_init(); usbuart_init(); - - /* Set recovery point */ - if (setjmp(fatal_error_jmpbuf)) { - /* Do nothing on failure */ - return 0; - } - - jtag_scan(NULL); - - return 0; } void platform_srst_set_val(bool assert) diff --git a/src/platforms/native/platform.h b/src/platforms/native/platform.h index 321c3f3..5688e60 100644 --- a/src/platforms/native/platform.h +++ b/src/platforms/native/platform.h @@ -24,20 +24,12 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include -#include -#include - -#include -#include - -#include -#include - #include "gdb_packet.h" #include "gpio.h" #include "morse.h" +#include + #define PLATFORM_HAS_TRACESWO #define PLATFORM_HAS_POWER_SWITCH #define BOARD_IDENT "Black Magic Probe" @@ -173,13 +165,6 @@ extern jmp_buf fatal_error_jmpbuf; longjmp(fatal_error_jmpbuf, (error)); \ } while (0) -int platform_init(void); -const char *platform_target_voltage(void); -int platform_hwversion(void); -void platform_set_timeout(uint32_t ms); -bool platform_timeout_expired(void); -void platform_delay(uint32_t delay); - /* Use newlib provided integer only stdio functions */ #define sscanf siscanf #define sprintf siprintf @@ -188,9 +173,6 @@ void platform_delay(uint32_t delay); #define disconnect_usb() gpio_set_mode(USB_PU_PORT, GPIO_MODE_INPUT, 0, USB_PU_PIN); void assert_boot_pin(void); void setup_vbus_irq(void); -void platform_srst_set_val(bool assert); -bool platform_target_get_power(void); -void platform_target_set_power(bool power); #endif diff --git a/src/platforms/stlink/platform.c b/src/platforms/stlink/platform.c index 6ef8c77..6194d92 100644 --- a/src/platforms/stlink/platform.c +++ b/src/platforms/stlink/platform.c @@ -22,7 +22,10 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" + #include #include #include @@ -31,11 +34,6 @@ #include #include -#include "jtag_scan.h" -#include - -#include - uint8_t running_status; volatile uint32_t timeout_counter; @@ -68,7 +66,7 @@ int platform_hwversion(void) return hwversion; } -int platform_init(void) +void platform_init(void) { rcc_clock_setup_in_hse_8mhz_out_72mhz(); @@ -119,16 +117,6 @@ int platform_init(void) SCB_VTOR = 0x2000; /* Relocate interrupt vector table here */ cdcacm_init(); - - /* Set recovery point */ - if (setjmp(fatal_error_jmpbuf)) { - /* Do nothing on failure */ - return 0; - } - - jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/stlink/platform.h b/src/platforms/stlink/platform.h index a33ca06..5768817 100644 --- a/src/platforms/stlink/platform.h +++ b/src/platforms/stlink/platform.h @@ -24,18 +24,14 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include +#include "gdb_packet.h" +#include "gpio.h" + #include #include - -#include #include #include -#include - -#include "gdb_packet.h" -#include "gpio.h" #define BOARD_IDENT "Black Magic Probe (STLINK), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade) for STLink/Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -151,11 +147,6 @@ extern uint16_t led_idle_run; longjmp(fatal_error_jmpbuf, (error)); \ } while (0) -int platform_init(void); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); -void platform_srst_set_val(bool assert); - /* Use newlib provided integer only stdio functions */ #define sscanf siscanf #define sprintf siprintf @@ -163,6 +154,7 @@ void platform_srst_set_val(bool assert); void disconnect_usb(void); void assert_boot_pin(void); +void setup_vbus_irq(void); #endif diff --git a/src/platforms/stm32/cdcacm.c b/src/platforms/stm32/cdcacm.c index 074b534..577925a 100644 --- a/src/platforms/stm32/cdcacm.c +++ b/src/platforms/stm32/cdcacm.c @@ -33,7 +33,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "gdb_if.h" #include "cdcacm.h" #if defined(PLATFORM_HAS_TRACESWO) diff --git a/src/platforms/stm32/dfu_f1.c b/src/platforms/stm32/dfu_f1.c index bb1e274..abbdbe6 100644 --- a/src/platforms/stm32/dfu_f1.c +++ b/src/platforms/stm32/dfu_f1.c @@ -16,12 +16,11 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -#include "platform.h" +#include "general.h" +#include "usbdfu.h" #include #include -#include "usbdfu.h" #define FLASH_OBP_RDP 0x1FFFF800 #define FLASH_OBP_WRP10 0x1FFFF808 diff --git a/src/platforms/stm32/dfu_f4.c b/src/platforms/stm32/dfu_f4.c index 1065938..2ececa0 100644 --- a/src/platforms/stm32/dfu_f4.c +++ b/src/platforms/stm32/dfu_f4.c @@ -16,8 +16,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -#include "platform.h" +#include "general.h" +#include "usbdfu.h" #if defined(STM32F2) # include @@ -26,8 +26,6 @@ #endif #include -#include "usbdfu.h" - static uint32_t sector_addr[] = { 0x8000000, 0x8004000, 0x8008000, 0x800c000, 0x8010000, 0x8020000, 0x8040000, 0x8060000, diff --git a/src/platforms/stm32/dfucore.c b/src/platforms/stm32/dfucore.c index 77cef4e..7b733d7 100644 --- a/src/platforms/stm32/dfucore.c +++ b/src/platforms/stm32/dfucore.c @@ -17,7 +17,7 @@ * along with this program. If not, see . */ -#include "platform.h" +#include "general.h" #include #if defined(STM32F1) diff --git a/src/platforms/stm32/gdb_if.c b/src/platforms/stm32/gdb_if.c index 6cc9084..286c66b 100644 --- a/src/platforms/stm32/gdb_if.c +++ b/src/platforms/stm32/gdb_if.c @@ -22,7 +22,7 @@ * Serial Debugging protocol is implemented. This implementation for STM32 * uses the USB CDC-ACM device bulk endpoints to implement the channel. */ -#include "platform.h" +#include "general.h" #include "cdcacm.h" #include "gdb_if.h" diff --git a/src/platforms/stm32/gpio.h b/src/platforms/stm32/gpio.h index 035f3c9..ee8275e 100644 --- a/src/platforms/stm32/gpio.h +++ b/src/platforms/stm32/gpio.h @@ -20,6 +20,16 @@ #ifndef __GPIO_H #define __GPIO_H +#include + +#ifndef STM32F4 +# include +# include +#else +# include +# include +#endif + #define INLINE_GPIO #define gpio_set_val(port, pin, val) do { \ diff --git a/src/platforms/stm32/jtagtap.c b/src/platforms/stm32/jtagtap.c index 2d09b84..3c45a81 100644 --- a/src/platforms/stm32/jtagtap.c +++ b/src/platforms/stm32/jtagtap.c @@ -23,9 +23,7 @@ #include #include "general.h" - #include "jtagtap.h" -#include "platform.h" int jtagtap_init(void) { diff --git a/src/platforms/stm32/traceswo.c b/src/platforms/stm32/traceswo.c index 29bae8f..a2e704d 100644 --- a/src/platforms/stm32/traceswo.c +++ b/src/platforms/stm32/traceswo.c @@ -32,15 +32,12 @@ * The core can then process the buffer to extract the frame. */ #include "general.h" +#include "cdcacm.h" #include #include #include -#include -#include "platform.h" -#include "cdcacm.h" - void traceswo_init(void) { TRACE_TIM_CLK_EN(); diff --git a/src/platforms/stm32/usbuart.c b/src/platforms/stm32/usbuart.c index 970a609..cce2904 100644 --- a/src/platforms/stm32/usbuart.c +++ b/src/platforms/stm32/usbuart.c @@ -27,7 +27,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "cdcacm.h" #define USBUART_TIMER_FREQ_HZ 1000000U /* 1us per tick */ diff --git a/src/platforms/swlink/platform.c b/src/platforms/swlink/platform.c index 853cbc9..168ba2a 100644 --- a/src/platforms/swlink/platform.c +++ b/src/platforms/swlink/platform.c @@ -22,7 +22,10 @@ * implementation. */ -#include "platform.h" +#include "general.h" +#include "cdcacm.h" +#include "usbuart.h" + #include #include #include @@ -31,17 +34,12 @@ #include #include -#include "jtag_scan.h" -#include - -#include - uint8_t running_status; volatile uint32_t timeout_counter; jmp_buf fatal_error_jmpbuf; -int platform_init(void) +void platform_init(void) { uint32_t data; rcc_clock_setup_in_hse_8mhz_out_72mhz(); @@ -98,15 +96,6 @@ int platform_init(void) SCB_VTOR = 0x2000; // Relocate interrupt vector table here cdcacm_init(); - - // Set recovery point - if (setjmp(fatal_error_jmpbuf)) { - return 0; // Do nothing on failure - } - - jtag_scan(NULL); - - return 0; } void platform_delay(uint32_t delay) diff --git a/src/platforms/swlink/platform.h b/src/platforms/swlink/platform.h index 26cb7a6..dec5548 100644 --- a/src/platforms/swlink/platform.h +++ b/src/platforms/swlink/platform.h @@ -24,19 +24,11 @@ #ifndef __PLATFORM_H #define __PLATFORM_H -#include -#include -#include - -#include -#include - -#include -#include - #include "gdb_packet.h" #include "gpio.h" +#include + #define BOARD_IDENT "Black Magic Probe (SWLINK), (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_DFU "Black Magic (Upgrade), STM8S Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" #define BOARD_IDENT_UPD "Black Magic (DFU Upgrade), STM8S Discovery, (Firmware 1.5" VERSION_SUFFIX ", build " BUILDDATE ")" @@ -149,10 +141,6 @@ extern jmp_buf fatal_error_jmpbuf; longjmp(fatal_error_jmpbuf, (error)); \ } -int platform_init(void); -const char *platform_target_voltage(void); -void platform_delay(uint32_t delay); - /* Use newlib provided integer only stdio functions */ #define sscanf siscanf #define sprintf siprintf diff --git a/src/platforms/tm4c/cdcacm.c b/src/platforms/tm4c/cdcacm.c index 041d85b..2677ad5 100644 --- a/src/platforms/tm4c/cdcacm.c +++ b/src/platforms/tm4c/cdcacm.c @@ -35,7 +35,7 @@ #include #include -#include "platform.h" +#include "general.h" #include "gdb_if.h" #if defined(PLATFORM_HAS_TRACESWO) #include diff --git a/src/platforms/tm4c/gdb_if.c b/src/platforms/tm4c/gdb_if.c index b14bbd3..7119638 100644 --- a/src/platforms/tm4c/gdb_if.c +++ b/src/platforms/tm4c/gdb_if.c @@ -22,10 +22,12 @@ * Serial Debugging protocol is implemented. This implementation for STM32 * uses the USB CDC-ACM device bulk endpoints to implement the channel. */ -#include "platform.h" -#include +#include "general.h" #include "gdb_if.h" +#include "cdcacm.h" + +#include static volatile uint32_t head_out, tail_out; static volatile uint32_t count_in; diff --git a/src/platforms/tm4c/jtagtap.c b/src/platforms/tm4c/jtagtap.c index f340b1e..e0bdd68 100644 --- a/src/platforms/tm4c/jtagtap.c +++ b/src/platforms/tm4c/jtagtap.c @@ -1,3 +1,4 @@ +#include "general.h" #include "jtagtap.h" int diff --git a/src/platforms/tm4c/swdptap.c b/src/platforms/tm4c/swdptap.c index 7004598..058f6ba 100644 --- a/src/platforms/tm4c/swdptap.c +++ b/src/platforms/tm4c/swdptap.c @@ -1,5 +1,4 @@ #include "general.h" -#include "platform.h" #include "swdptap.h" static void swdptap_turnaround(uint8_t dir) diff --git a/src/platforms/tm4c/traceswo.c b/src/platforms/tm4c/traceswo.c index eb63139..03c6d66 100644 --- a/src/platforms/tm4c/traceswo.c +++ b/src/platforms/tm4c/traceswo.c @@ -32,14 +32,9 @@ #include #include #include - #include - #include -#include -#include "platform.h" - void traceswo_init(void) { periph_clock_enable(RCC_GPIOD); diff --git a/src/platforms/tm4c/usbuart.c b/src/platforms/tm4c/usbuart.c index bb769f0..da82198 100644 --- a/src/platforms/tm4c/usbuart.c +++ b/src/platforms/tm4c/usbuart.c @@ -19,6 +19,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ +#include "general.h" +#include "cdcacm.h" #include #include @@ -27,8 +29,6 @@ #include #include -#include - #define FIFO_SIZE 128 /* RX Fifo buffer */ diff --git a/src/sam3x.c b/src/sam3x.c index e6b8f2e..ef99290 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -22,9 +22,6 @@ * the device, providing the XML memory map and Flash memory programming. */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/samd.c b/src/samd.c index b043c50..1a7a553 100644 --- a/src/samd.c +++ b/src/samd.c @@ -32,10 +32,6 @@ * particularly Sections 12. DSU and 20. NVMCTRL */ -#include -#include -#include - #include "general.h" #include "jtagtap.h" #include "adiv5.h" diff --git a/src/stm32f1.c b/src/stm32f1.c index bce00d3..017196a 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -29,9 +29,6 @@ * Programming manual - STM32F10xxx Flash memory microcontrollers */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/stm32f4.c b/src/stm32f4.c index 148c31b..bc3572f 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -30,9 +30,6 @@ * manual */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/stm32l1.c b/src/stm32l1.c index 0472885..227f67c 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -29,9 +29,6 @@ * Flash and EEPROM programming */ -#include -#include - #include "general.h" #include "adiv5.h" #include "target.h" diff --git a/src/target.c b/src/target.c index 2a68f23..4299a45 100644 --- a/src/target.c +++ b/src/target.c @@ -21,8 +21,6 @@ #include "general.h" #include "target.h" -#include - target *target_list = NULL; bool connect_assert_srst; -- cgit v1.2.3 From 2e785e56fa4e77549878eac88f2c4891af043e64 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 14 Mar 2015 18:03:04 -0700 Subject: adiv5: Encode APnDP into register definition. Clean up magic numbers in adiv5 calls. Removed old adiv5_dp_write_ap and adiv5_dp_read_ap.--- src/adiv5.c | 90 +++++++++++++++++++---------------------------------- src/adiv5_jtagdp.c | 31 +++++++++--------- src/adiv5_swdp.c | 28 +++++++++++------ src/cortexm.c | 35 ++++++++++++--------- src/include/adiv5.h | 57 +++++++++++++++++---------------- src/lmi.c | 11 ++++--- src/samd.c | 4 +-- 7 files changed, 123 insertions(+), 133 deletions(-) (limited to 'src/include/adiv5.h') diff --git a/src/adiv5.c b/src/adiv5.c index 361cd75..aee8471 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -160,23 +160,6 @@ void adiv5_dp_init(ADIv5_DP_t *dp) adiv5_dp_unref(dp); } -void adiv5_dp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) -{ - adiv5_dp_low_access(dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, addr, value); -} - -uint32_t adiv5_dp_read_ap(ADIv5_DP_t *dp, uint8_t addr) -{ - uint32_t ret; - - adiv5_dp_low_access(dp, ADIV5_LOW_AP, ADIV5_LOW_READ, addr, 0); - ret = adiv5_dp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, - ADIV5_DP_RDBUFF, 0); - - return ret; -} - - static int ap_check_error(struct target_s *target) { @@ -194,26 +177,24 @@ ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); while(--len) { - *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); src += 4; /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); } } - *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_DP, ADIV5_LOW_READ, - ADIV5_DP_RDBUFF, 0); + *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, + ADIV5_DP_RDBUFF, 0); return 0; } @@ -229,12 +210,10 @@ ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); while(--len) { - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); @@ -242,13 +221,13 @@ ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); } } - tmp = adiv5_dp_low_access(ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); return 0; @@ -263,25 +242,23 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len) adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); while(--len) { - tmp = adiv5_dp_low_access(ap->dp, 1, 1, ADIV5_AP_DRW, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); *dest++ = (tmp >> ((src & 0x3) << 3) & 0xFF); src++; /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); } } - tmp = adiv5_dp_low_access(ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); *dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF); return 0; @@ -298,16 +275,15 @@ ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src, adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, dest); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); while(len--) { - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, *src++); dest += 4; /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { odest = dest; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } @@ -325,17 +301,16 @@ ap_mem_write_halfwords(struct target_s *target, uint32_t dest, const uint16_t *s adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, dest); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); while(len--) { uint32_t tmp = (uint32_t)*src++ << ((dest & 2) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, tmp); dest += 2; /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { odest = dest; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } @@ -350,17 +325,16 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, - ADIV5_AP_TAR, dest); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); while(len--) { uint32_t tmp = (uint32_t)*src++ << ((dest++ & 3) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, tmp); /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { odest = dest; - adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } @@ -429,19 +403,19 @@ void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value) adiv5_ap_write(ap, ADIV5_AP_DRW, v); } -void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value) +void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value) { adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, ((uint32_t)ap->apsel << 24)|(addr & 0xF0)); - adiv5_dp_write_ap(ap->dp, addr, value); + adiv5_dp_write(ap->dp, addr, value); } -uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint8_t addr) +uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr) { uint32_t ret; adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, ((uint32_t)ap->apsel << 24)|(addr & 0xF0)); - ret = adiv5_dp_read_ap(ap->dp, addr); + ret = adiv5_dp_read(ap->dp, addr); return ret; } diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index 8f62a11..eb60caa 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -36,13 +36,13 @@ #define IR_DPACC 0xA #define IR_APACC 0xB -static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value); -static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr); +static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); +static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr); static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp); -static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value); +static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value); void adiv5_jtag_dp_handler(jtag_dev_t *dev) @@ -60,35 +60,36 @@ void adiv5_jtag_dp_handler(jtag_dev_t *dev) adiv5_dp_init(dp); } -static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) +static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) { - adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, addr, value); + adiv5_jtagdp_low_access(dp, ADIV5_LOW_WRITE, addr, value); } -static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr) +static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr) { - adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, addr, 0); - return adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, + adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, addr, 0); + return adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); } static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp) { - adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, - ADIV5_DP_CTRLSTAT, 0); - return adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, + adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_CTRLSTAT, 0); + return adiv5_jtagdp_low_access(dp, ADIV5_LOW_WRITE, ADIV5_DP_CTRLSTAT, 0xF0000032) & 0x32; } -static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value) +static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value) { + bool APnDP = addr & ADIV5_APnDP; + addr &= 0xff; uint64_t request, response; uint8_t ack; request = ((uint64_t)value << 3) | ((addr >> 1) & 0x06) | (RnW?1:0); - jtag_dev_write_ir(dp->dev, APnDP?IR_APACC:IR_DPACC); + jtag_dev_write_ir(dp->dev, APnDP ? IR_APACC : IR_DPACC); int tries = 1000; do { diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index 9df362f..3e775cc 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -33,13 +33,13 @@ #define SWDP_ACK_WAIT 0x02 #define SWDP_ACK_FAULT 0x04 -static void adiv5_swdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value); -static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint8_t addr); +static void adiv5_swdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); +static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr); static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp); -static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value); +static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value); int adiv5_swdp_scan(void) @@ -78,14 +78,20 @@ int adiv5_swdp_scan(void) return target_list?1:0; } -static void adiv5_swdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) +static void adiv5_swdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) { - adiv5_swdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, addr, value); + adiv5_swdp_low_access(dp, ADIV5_LOW_WRITE, addr, value); } -static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint8_t addr) +static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr) { - return adiv5_swdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, addr, 0); + if (addr & ADIV5_APnDP) { + adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0); + return adiv5_dp_low_access(dp, ADIV5_LOW_READ, + ADIV5_DP_RDBUFF, 0); + } else { + return adiv5_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0); + } } static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp) @@ -111,9 +117,11 @@ static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp) return err; } -static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value) +static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, + uint16_t addr, uint32_t value) { + bool APnDP = addr & ADIV5_APnDP; + addr &= 0xff; uint8_t request = 0x81; uint32_t response; uint8_t ack; diff --git a/src/cortexm.c b/src/cortexm.c index b1d3569..da48f8e 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -359,20 +359,23 @@ cortexm_regs_read(struct target_s *target, void *data) /* Map the banked data registers (0x10-0x1c) to the * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */ - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_TAR, CORTEXM_DHCSR); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR); /* Walk the regnum_cortex_m array, reading the registers it * calls out. */ adiv5_ap_write(ap, ADIV5_AP_DB(1), regnum_cortex_m[0]); /* Required to switch banks */ - *regs++ = adiv5_dp_read_ap(ap->dp, ADIV5_AP_DB(2)); + *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), regnum_cortex_m[i]); - *regs++ = adiv5_dp_read_ap(ap->dp, ADIV5_AP_DB(2)); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), + regnum_cortex_m[i]); + *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); } if (target->target_options & TOPT_FLAVOUR_V7MF) for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), regnum_cortex_mf[i]); - *regs++ = adiv5_dp_read_ap(ap->dp, ADIV5_AP_DB(2)); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(1), + regnum_cortex_mf[i]); + *regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2)); } return 0; @@ -391,22 +394,26 @@ cortexm_regs_write(struct target_s *target, const void *data) /* Map the banked data registers (0x10-0x1c) to the * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */ - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_TAR, CORTEXM_DHCSR); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR); /* Walk the regnum_cortex_m array, writing the registers it * calls out. */ adiv5_ap_write(ap, ADIV5_AP_DB(2), *regs++); /* Required to switch banks */ - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), 0x10000 | regnum_cortex_m[0]); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), + 0x10000 | regnum_cortex_m[0]); for(i = 1; i < sizeof(regnum_cortex_m) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(2), *regs++); - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), - 0x10000 | regnum_cortex_m[i]); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(2), *regs++); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1), + 0x10000 | regnum_cortex_m[i]); } if (target->target_options & TOPT_FLAVOUR_V7MF) for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) { - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(2), *regs++); - adiv5_dp_low_access(ap->dp, 1, 0, ADIV5_AP_DB(1), - 0x10000 | regnum_cortex_mf[i]); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(2), *regs++); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, + ADIV5_AP_DB(1), + 0x10000 | regnum_cortex_mf[i]); } return 0; diff --git a/src/include/adiv5.h b/src/include/adiv5.h index e0ce9cf..cfdb4e5 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -24,12 +24,16 @@ #include "jtag_scan.h" #include "target.h" +#define ADIV5_APnDP 0x100 +#define ADIV5_DP_REG(x) (x) +#define ADIV5_AP_REG(x) (ADIV5_APnDP | (x)) + /* ADIv5 DP Register addresses */ -#define ADIV5_DP_IDCODE 0x0 -#define ADIV5_DP_ABORT 0x0 -#define ADIV5_DP_CTRLSTAT 0x4 -#define ADIV5_DP_SELECT 0x8 -#define ADIV5_DP_RDBUFF 0xC +#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0) +#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0) +#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4) +#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8) +#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xC) /* AP Abort Register (ABORT) */ /* Bits 31:5 - Reserved */ @@ -63,15 +67,15 @@ /* ADIv5 MEM-AP Registers */ -#define ADIV5_AP_CSW 0x00 -#define ADIV5_AP_TAR 0x04 +#define ADIV5_AP_CSW ADIV5_AP_REG(0x00) +#define ADIV5_AP_TAR ADIV5_AP_REG(0x04) /* 0x08 - Reserved */ -#define ADIV5_AP_DRW 0x0C -#define ADIV5_AP_DB(x) (0x10 + (4*(x))) +#define ADIV5_AP_DRW ADIV5_AP_REG(0x0C) +#define ADIV5_AP_DB(x) ADIV5_AP_REG(0x10 + (4*(x))) /* 0x20:0xF0 - Reserved */ -#define ADIV5_AP_CFG 0xF4 -#define ADIV5_AP_BASE 0xF8 -#define ADIV5_AP_IDR 0xFC +#define ADIV5_AP_CFG ADIV5_AP_REG(0xF4) +#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8) +#define ADIV5_AP_IDR ADIV5_AP_REG(0xFC) /* AP Control and Status Word (CSW) */ #define ADIV5_AP_CSW_DBGSWENABLE (1u << 31) @@ -93,11 +97,9 @@ #define ADIV5_AP_CSW_SIZE_WORD (2u << 0) #define ADIV5_AP_CSW_SIZE_MASK (7u << 0) -/* Constants to make RnW and APnDP parameters more clear in code */ +/* Constants to make RnW parameters more clear in code */ #define ADIV5_LOW_WRITE 0 #define ADIV5_LOW_READ 1 -#define ADIV5_LOW_DP 0 -#define ADIV5_LOW_AP 1 /* Try to keep this somewhat absract for later adding SW-DP */ typedef struct ADIv5_DP_s { @@ -107,13 +109,13 @@ typedef struct ADIv5_DP_s { bool allow_timeout; - void (*dp_write)(struct ADIv5_DP_s *dp, uint8_t addr, uint32_t value); - uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint8_t addr); + void (*dp_write)(struct ADIv5_DP_s *dp, uint16_t addr, uint32_t value); + uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr); uint32_t (*error)(struct ADIv5_DP_s *dp); - uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t APnDP, uint8_t RnW, - uint8_t addr, uint32_t value); + uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW, + uint16_t addr, uint32_t value); union { jtag_dev_t *dev; @@ -121,12 +123,12 @@ typedef struct ADIv5_DP_s { }; } ADIv5_DP_t; -static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value) +static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) { dp->dp_write(dp, addr, value); } -static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint8_t addr) +static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr) { return dp->dp_read(dp, addr); } @@ -136,10 +138,10 @@ static inline uint32_t adiv5_dp_error(ADIv5_DP_t *dp) return dp->error(dp); } -static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t APnDP, - uint8_t RnW, uint8_t addr, uint32_t value) +static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW, + uint16_t addr, uint32_t value) { - return dp->low_access(dp, APnDP, RnW, addr, value); + return dp->low_access(dp, RnW, addr, value); } typedef struct ADIv5_AP_s { @@ -164,9 +166,6 @@ void adiv5_ap_ref(ADIv5_AP_t *ap); void adiv5_dp_unref(ADIv5_DP_t *dp); void adiv5_ap_unref(ADIv5_AP_t *ap); -void adiv5_dp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value); -uint32_t adiv5_dp_read_ap(ADIv5_DP_t *dp, uint8_t addr); - uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr); void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value); uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr); @@ -174,8 +173,8 @@ void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value); uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr); void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value); -void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value); -uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint8_t addr); +void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value); +uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr); void adiv5_jtag_dp_handler(jtag_dev_t *dev); int adiv5_swdp_scan(void); diff --git a/src/lmi.c b/src/lmi.c index 0f16db4..9359458 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -131,17 +131,18 @@ int lmi_flash_erase(struct target_s *target, uint32_t addr, size_t len) adiv5_ap_write(ap, 0x00, 0xA2000052); /* select Flash Control */ - adiv5_dp_low_access(ap->dp, 1, 0, 0x04, 0x400FD000); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, 0x04, 0x400FD000); while(len) { /* write address to FMA */ - adiv5_ap_write(ap, 0x10, addr); /* Required to switch banks */ + adiv5_ap_write(ap, ADIV5_AP_DB(0), addr); /* Required to switch banks */ /* set ERASE bit in FMC */ - adiv5_dp_low_access(ap->dp, 1, 0, 0x08, 0xA4420002); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(2), 0xA4420002); /* Read FMC to poll for ERASE bit */ - adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DB(2), 0); do { - tmp = adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0); + tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, + ADIV5_AP_DB(2), 0); } while (tmp & 2); len -= 0x400; diff --git a/src/samd.c b/src/samd.c index 6f73956..2719763 100644 --- a/src/samd.c +++ b/src/samd.c @@ -553,7 +553,7 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, /* Partial, manual page write */ for (; addr <= MINIMUM(end, end_of_this_page); addr += 4, i++) { - adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); + adiv5_dp_write(ap->dp, ADIV5_AP_DRW, data[i]); } /* Unlock */ @@ -578,7 +578,7 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, /* Full, automatic page write */ for (; addr < page + SAMD_PAGE_SIZE; addr += 4, i++) { - adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); + adiv5_dp_write(ap->dp, ADIV5_AP_DRW, data[i]); } } -- cgit v1.2.3 From 2bf54f9a72bd9ee57e668f09075b65486e418216 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 15 Mar 2015 16:02:09 -0700 Subject: Replace adiv5_ap_mem* functions with inline wrappers to target mem*. --- src/adiv5.c | 60 ---------------------- src/cortexm.c | 100 ++++++++++++++++++------------------- src/crc32.c | 6 +-- src/include/adiv5.h | 7 --- src/include/target.h | 38 +++++++++++++- src/kinetis.c | 15 +++--- src/lmi.c | 2 +- src/lpc11xx.c | 2 +- src/lpc43xx.c | 4 +- src/nrf51.c | 60 ++++++++-------------- src/sam3x.c | 49 ++++++++---------- src/samd.c | 134 +++++++++++++++++++++---------------------------- src/stm32f1.c | 73 ++++++++++++--------------- src/stm32f4.c | 56 +++++++++------------ src/stm32l0.c | 138 ++++++++++++++++++++++++--------------------------- src/stm32l1.c | 40 +++++++-------- 16 files changed, 336 insertions(+), 448 deletions(-) (limited to 'src/include/adiv5.h') diff --git a/src/adiv5.c b/src/adiv5.c index 8f99a9d..2179ca6 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -273,66 +273,6 @@ ap_mem_write(struct target_s *target, uint32_t dest, const void *src, size_t len } } -uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - return adiv5_ap_read(ap, ADIV5_AP_DRW); -} - -void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_ap_write(ap, ADIV5_AP_DRW, value); -} - -uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - uint32_t v = adiv5_ap_read(ap, ADIV5_AP_DRW); - if (addr & 2) - return v >> 16; - else - return v & 0xFFFF; -} - -void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value) -{ - uint32_t v = value; - if (addr & 2) - v <<= 16; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_ap_write(ap, ADIV5_AP_DRW, v); -} - -uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr) -{ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - uint32_t v = adiv5_ap_read(ap, ADIV5_AP_DRW); - - return v >> ((addr & 3) * 8); -} - -void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value) -{ - uint32_t v = value << ((addr & 3) * 8); - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_ap_write(ap, ADIV5_AP_DRW, v); -} - void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value) { adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, diff --git a/src/cortexm.c b/src/cortexm.c index fcc6a9d..4bfb4d9 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -228,16 +228,16 @@ cortexm_probe(struct target_s *target) target_add_commands(target, cortexm_cmd_list, cortexm_driver_str); /* Probe for FP extension */ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t cpacr = adiv5_ap_mem_read(ap, CORTEXM_CPACR); + uint32_t cpacr = target_mem_read32(target, CORTEXM_CPACR); cpacr |= 0x00F00000; /* CP10 = 0b11, CP11 = 0b11 */ - adiv5_ap_mem_write(ap, CORTEXM_CPACR, cpacr); - if (adiv5_ap_mem_read(ap, CORTEXM_CPACR) == cpacr) { + target_mem_write32(target, CORTEXM_CPACR, cpacr); + if (target_mem_read32(target, CORTEXM_CPACR) == cpacr) { target->target_options |= TOPT_FLAVOUR_V7MF; target->regs_size += sizeof(regnum_cortex_mf); target->tdesc = tdesc_cortex_mf; } + ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = calloc(1, sizeof(*priv)); ap->priv = priv; ap->priv_free = free; @@ -284,35 +284,35 @@ bool cortexm_attach(struct target_s *target) return false; /* Request halt on reset */ - adiv5_ap_mem_write(ap, CORTEXM_DEMCR, priv->demcr); + target_mem_write32(target, CORTEXM_DEMCR, priv->demcr); /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); /* size the break/watchpoint units */ priv->hw_breakpoint_max = CORTEXM_MAX_BREAKPOINTS; - r = adiv5_ap_mem_read(ap, CORTEXM_FPB_CTRL); + r = target_mem_read32(target, CORTEXM_FPB_CTRL); if (((r >> 4) & 0xf) < priv->hw_breakpoint_max) /* only look at NUM_COMP1 */ priv->hw_breakpoint_max = (r >> 4) & 0xf; priv->hw_watchpoint_max = CORTEXM_MAX_WATCHPOINTS; - r = adiv5_ap_mem_read(ap, CORTEXM_DWT_CTRL); + r = target_mem_read32(target, CORTEXM_DWT_CTRL); if ((r >> 28) > priv->hw_watchpoint_max) priv->hw_watchpoint_max = r >> 28; /* Clear any stale breakpoints */ for(i = 0; i < priv->hw_breakpoint_max; i++) { - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); + target_mem_write32(target, CORTEXM_FPB_COMP(i), 0); priv->hw_breakpoint[i] = 0; } /* Clear any stale watchpoints */ for(i = 0; i < priv->hw_watchpoint_max; i++) { - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0); priv->hw_watchpoint[i].type = 0; } /* Flash Patch Control Register: set ENABLE */ - adiv5_ap_mem_write(ap, CORTEXM_FPB_CTRL, + target_mem_write32(target, CORTEXM_FPB_CTRL, CORTEXM_FPB_CTRL_KEY | CORTEXM_FPB_CTRL_ENABLE); target->set_hw_bp = cortexm_set_hw_bp; target->clear_hw_bp = cortexm_clear_hw_bp; @@ -336,14 +336,14 @@ void cortexm_detach(struct target_s *target) /* Clear any stale breakpoints */ for(i = 0; i < priv->hw_breakpoint_max; i++) - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); + target_mem_write32(target, CORTEXM_FPB_COMP(i), 0); /* Clear any stale watchpoints */ for(i = 0; i < priv->hw_watchpoint_max; i++) - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0); /* Disable debug */ - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); + target_mem_write32(target, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); } static int @@ -422,10 +422,8 @@ cortexm_regs_write(struct target_s *target, const void *data) static uint32_t cortexm_pc_read(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - adiv5_ap_mem_write(ap, CORTEXM_DCRSR, 0x0F); - return adiv5_ap_mem_read(ap, CORTEXM_DCRDR); + target_mem_write32(target, CORTEXM_DCRSR, 0x0F); + return target_mem_read32(target, CORTEXM_DCRDR); return 0; } @@ -433,10 +431,8 @@ cortexm_pc_read(struct target_s *target) static int cortexm_pc_write(struct target_s *target, const uint32_t val) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - adiv5_ap_mem_write(ap, CORTEXM_DCRDR, val); - adiv5_ap_mem_write(ap, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); + target_mem_write32(target, CORTEXM_DCRDR, val); + target_mem_write32(target, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F); return 0; } @@ -446,26 +442,24 @@ cortexm_pc_write(struct target_s *target, const uint32_t val) static void cortexm_reset(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - jtagtap_srst(true); jtagtap_srst(false); /* Read DHCSR here to clear S_RESET_ST bit before reset */ - adiv5_ap_mem_read(ap, CORTEXM_DHCSR); + target_mem_read32(target, CORTEXM_DHCSR); /* Request system reset from NVIC: SRST doesn't work correctly */ /* This could be VECTRESET: 0x05FA0001 (reset only core) * or SYSRESETREQ: 0x05FA0004 (system reset) */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, - CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); + target_mem_write32(target, CORTEXM_AIRCR, + CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); /* Poll for release from reset */ - while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); + while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); } static void @@ -474,8 +468,9 @@ cortexm_halt_request(struct target_s *target) ADIv5_AP_t *ap = adiv5_target_ap(target); ap->dp->allow_timeout = false; - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, - CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN); + target_mem_write32(target, CORTEXM_DHCSR, + CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | + CORTEXM_DHCSR_C_DEBUGEN); } static int @@ -483,14 +478,14 @@ cortexm_halt_wait(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = ap->priv; - if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) + if (!(target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) return 0; ap->dp->allow_timeout = false; /* We've halted. Let's find out why. */ - uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR); - adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */ + uint32_t dfsr = target_mem_read32(target, CORTEXM_DFSR); + target_mem_write32(target, CORTEXM_DFSR, dfsr); /* write back to reset */ if ((dfsr & CORTEXM_DFSR_VCATCH) && cortexm_fault_unwind(target)) return SIGSEGV; @@ -502,7 +497,7 @@ cortexm_halt_wait(struct target_s *target) * call. */ uint32_t pc = cortexm_pc_read(target); uint16_t bkpt_instr; - target_mem_read(target, &bkpt_instr, pc, 2); + bkpt_instr = target_mem_read16(target, pc); if (bkpt_instr == 0xBEAB) { int n = cortexm_hostio_request(target); if (n > 0) { @@ -535,27 +530,26 @@ void cortexm_halt_resume(struct target_s *target, bool step) /* Disable interrupts while single stepping... */ if(step != priv->stepping) { - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT); + target_mem_write32(target, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT); priv->stepping = step; } if (priv->on_bkpt) { uint32_t pc = cortexm_pc_read(target); - if ((adiv5_ap_mem_read_halfword(ap, pc) & 0xFF00) == 0xBE00) + if ((target_mem_read16(target, pc) & 0xFF00) == 0xBE00) cortexm_pc_write(target, pc + 2); } - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr); + target_mem_write32(target, CORTEXM_DHCSR, dhcsr); ap->dp->allow_timeout = true; } static int cortexm_fault_unwind(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t hfsr = adiv5_ap_mem_read(ap, CORTEXM_HFSR); - uint32_t cfsr = adiv5_ap_mem_read(ap, CORTEXM_CFSR); - adiv5_ap_mem_write(ap, CORTEXM_HFSR, hfsr);/* write back to reset */ - adiv5_ap_mem_write(ap, CORTEXM_CFSR, cfsr);/* write back to reset */ + uint32_t hfsr = target_mem_read32(target, CORTEXM_HFSR); + uint32_t cfsr = target_mem_read32(target, CORTEXM_CFSR); + target_mem_write32(target, CORTEXM_HFSR, hfsr);/* write back to reset */ + target_mem_write32(target, CORTEXM_CFSR, cfsr);/* write back to reset */ /* We check for FORCED in the HardFault Status Register or * for a configurable fault to avoid catching core resets */ if((hfsr & CORTEXM_HFSR_FORCED) || cfsr) { @@ -598,7 +592,7 @@ static int cortexm_fault_unwind(struct target_s *target) /* Reset exception state to allow resuming from restored * state. */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, + target_mem_write32(target, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_VECTCLRACTIVE); /* Write pre-exception registers back to core */ @@ -630,7 +624,7 @@ cortexm_set_hw_bp(struct target_s *target, uint32_t addr) priv->hw_breakpoint[i] = addr | 1; - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), val); + target_mem_write32(target, CORTEXM_FPB_COMP(i), val); return 0; } @@ -649,7 +643,7 @@ cortexm_clear_hw_bp(struct target_s *target, uint32_t addr) priv->hw_breakpoint[i] = 0; - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); + target_mem_write32(target, CORTEXM_FPB_COMP(i), 0); return 0; } @@ -683,7 +677,7 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t for(i = 0; i < priv->hw_watchpoint_max; i++) if((priv->hw_watchpoint[i].type == 0) && - ((adiv5_ap_mem_read(ap, CORTEXM_DWT_FUNC(i)) & 0xF) == 0)) + ((target_mem_read32(target, CORTEXM_DWT_FUNC(i)) & 0xF) == 0)) break; if(i == priv->hw_watchpoint_max) return -2; @@ -692,9 +686,9 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t priv->hw_watchpoint[i].addr = addr; priv->hw_watchpoint[i].size = len; - adiv5_ap_mem_write(ap, CORTEXM_DWT_COMP(i), addr); - adiv5_ap_mem_write(ap, CORTEXM_DWT_MASK(i), len); - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), type | + target_mem_write32(target, CORTEXM_DWT_COMP(i), addr); + target_mem_write32(target, CORTEXM_DWT_MASK(i), len); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), type | ((target->target_options & TOPT_FLAVOUR_V6M) ? 0: CORTEXM_DWT_FUNC_DATAVSIZE_WORD)); return 0; @@ -732,7 +726,7 @@ cortexm_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_ priv->hw_watchpoint[i].type = 0; - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); + target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0); return 0; } @@ -747,7 +741,7 @@ cortexm_check_hw_wp(struct target_s *target, uint32_t *addr) for(i = 0; i < priv->hw_watchpoint_max; i++) /* if SET and MATCHED then break */ if(priv->hw_watchpoint[i].type && - (adiv5_ap_mem_read(ap, CORTEXM_DWT_FUNC(i)) & + (target_mem_read32(target, CORTEXM_DWT_FUNC(i)) & CORTEXM_DWT_FUNC_MATCHED)) break; @@ -781,7 +775,7 @@ static bool cortexm_vector_catch(target *t, int argc, char *argv[]) else priv->demcr &= ~tmp; - adiv5_ap_mem_write(ap, CORTEXM_DEMCR, priv->demcr); + target_mem_write32(t, CORTEXM_DEMCR, priv->demcr); } gdb_out("Catching vectors: "); diff --git a/src/crc32.c b/src/crc32.c index fffc04c..e8a046d 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -100,7 +100,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) uint8_t byte; while (len--) { - target_mem_read(target, &byte, base, 1); + byte = target_mem_read8(target, base); crc = crc32_calc(crc, byte); base++; @@ -118,7 +118,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) CRC_CR |= CRC_CR_RESET; while (len > 3) { - target_mem_read(target, &data, base, 4); + data = target_mem_read32(target, base); CRC_DR = __builtin_bswap32(data); base += 4; @@ -128,7 +128,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) crc = CRC_DR; while (len--) { - target_mem_read(target, &data, base++, 1); + data = target_mem_read8(target, base++); crc ^= data << 24; for (i = 0; i < 8; i++) { diff --git a/src/include/adiv5.h b/src/include/adiv5.h index cfdb4e5..4bc3905 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -166,13 +166,6 @@ void adiv5_ap_ref(ADIv5_AP_t *ap); void adiv5_dp_unref(ADIv5_DP_t *dp); void adiv5_ap_unref(ADIv5_AP_t *ap); -uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr); -void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value); -uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr); -void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value); -uint8_t adiv5_ap_mem_read_byte(ADIv5_AP_t *ap, uint32_t addr); -void adiv5_ap_mem_write_byte(ADIv5_AP_t *ap, uint32_t addr, uint8_t value); - void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value); uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr); diff --git a/src/include/target.h b/src/include/target.h index b48e054..b6ea67d 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -111,7 +111,6 @@ target *target_attach(target *t, target_destroy_callback destroy_cb); #define target_hostio_reply(target, recode, errcode) \ (target)->hostio_reply((target), (retcode), (errcode)) - struct target_s { /* Notify controlling debugger if target is lost */ target_destroy_callback destroy_callback; @@ -187,6 +186,43 @@ target *target_new(unsigned size); void target_list_free(void); void target_add_commands(target *t, const struct command_s *cmds, const char *name); +static inline uint32_t target_mem_read32(target *t, uint32_t addr) +{ + uint32_t ret; + target_mem_read(t, &ret, addr, sizeof(ret)); + return ret; +} + +static inline void target_mem_write32(target *t, uint32_t addr, uint32_t value) +{ + target_mem_write(t, addr, &value, sizeof(value)); +} + +static inline uint16_t target_mem_read16(target *t, uint32_t addr) +{ + uint16_t ret; + target_mem_read(t, &ret, addr, sizeof(ret)); + return ret; +} + +static inline void target_mem_write16(target *t, uint32_t addr, uint16_t value) +{ + target_mem_write(t, addr, &value, sizeof(value)); +} + +static inline uint8_t target_mem_read8(target *t, uint32_t addr) +{ + uint8_t ret; + target_mem_read(t, &ret, addr, sizeof(ret)); + return ret; +} + +static inline void target_mem_write8(target *t, uint32_t addr, uint8_t value) +{ + target_mem_write(t, addr, &value, sizeof(value)); +} + + /* Probe for various targets. * Actual functions implemented in their respective drivers. */ diff --git a/src/kinetis.c b/src/kinetis.c index b260d2a..9f27d9b 100644 --- a/src/kinetis.c +++ b/src/kinetis.c @@ -72,7 +72,7 @@ static const char kl25_xml_memory_map[] = "" bool kinetis_probe(struct target_s *t) { - uint32_t sdid = adiv5_ap_mem_read(adiv5_target_ap(t), SIM_SDID); + uint32_t sdid = target_mem_read32(t, SIM_SDID); switch (sdid >> 20) { case 0x251: t->driver = "KL25"; @@ -87,12 +87,11 @@ bool kinetis_probe(struct target_s *t) static bool kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[8]) { - ADIv5_AP_t *ap = adiv5_target_ap(t); uint8_t fstat; /* Wait for CCIF to be high */ do { - fstat = adiv5_ap_mem_read_byte(ap, FTFA_FSTAT); + fstat = target_mem_read8(t, FTFA_FSTAT); /* Check ACCERR and FPVIOL are zero in FSTAT */ if (fstat & (FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL)) return false; @@ -101,18 +100,18 @@ kl25_command(struct target_s *t, uint8_t cmd, uint32_t addr, const uint8_t data[ /* Write command to FCCOB */ addr &= 0xffffff; addr |= (uint32_t)cmd << 24; - adiv5_ap_mem_write(ap, FTFA_FCCOB(0), addr); + target_mem_write32(t, FTFA_FCCOB(0), addr); if (data) { - adiv5_ap_mem_write(ap, FTFA_FCCOB(4), *(uint32_t*)&data[0]); - adiv5_ap_mem_write(ap, FTFA_FCCOB(8), *(uint32_t*)&data[4]); + target_mem_write32(t, FTFA_FCCOB(4), *(uint32_t*)&data[0]); + target_mem_write32(t, FTFA_FCCOB(8), *(uint32_t*)&data[4]); } /* Enable execution by clearing CCIF */ - adiv5_ap_mem_write_byte(ap, FTFA_FSTAT, FTFA_FSTAT_CCIF); + target_mem_write8(t, FTFA_FSTAT, FTFA_FSTAT_CCIF); /* Wait for execution to complete */ do { - fstat = adiv5_ap_mem_read_byte(ap, FTFA_FSTAT); + fstat = target_mem_read8(t, FTFA_FSTAT); /* Check ACCERR and FPVIOL are zero in FSTAT */ if (fstat & (FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL)) return false; diff --git a/src/lmi.c b/src/lmi.c index 8c5e143..d9aa613 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -100,7 +100,7 @@ static const uint16_t lmi_flash_write_stub[] = { bool lmi_probe(struct target_s *target) { - uint32_t did1 = adiv5_ap_mem_read(adiv5_target_ap(target), 0x400FE004); + uint32_t did1 = target_mem_read32(target, 0x400FE004); switch (did1 >> 16) { case 0x1049: /* LM3S3748 */ target->driver = lmi_driver_str; diff --git a/src/lpc11xx.c b/src/lpc11xx.c index eca3daf..6224464 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -108,7 +108,7 @@ lpc11xx_probe(struct target_s *target) uint32_t idcode; /* read the device ID register */ - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), 0x400483F4); + idcode = target_mem_read32(target, 0x400483F4); switch (idcode) { diff --git a/src/lpc43xx.c b/src/lpc43xx.c index 0ae9418..29e202a 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -170,8 +170,8 @@ bool lpc43xx_probe(struct target_s *target) { uint32_t chipid, cpuid; - chipid = adiv5_ap_mem_read(adiv5_target_ap(target), LPC43XX_CHIPID); - cpuid = adiv5_ap_mem_read(adiv5_target_ap(target), ARM_CPUID); + chipid = target_mem_read32(target, LPC43XX_CHIPID); + cpuid = target_mem_read32(target, ARM_CPUID); switch(chipid) { case 0x4906002B: /* Parts with on-chip flash */ diff --git a/src/nrf51.c b/src/nrf51.c index a4396bb..ed0137c 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -136,9 +136,7 @@ static const uint16_t nrf51_flash_write_stub[] = { bool nrf51_probe(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - target->idcode = adiv5_ap_mem_read(ap, NRF51_FICR_CONFIGID) & 0xFFFF; + target->idcode = target_mem_read32(target, NRF51_FICR_CONFIGID) & 0xFFFF; switch (target->idcode) { case 0x001D: @@ -165,32 +163,29 @@ bool nrf51_probe(struct target_s *target) static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - - ADIv5_AP_t *ap = adiv5_target_ap(target); - addr &= ~(NRF51_PAGE_SIZE - 1); len &= ~(NRF51_PAGE_SIZE - 1); /* Enable erase */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; while (len) { if (addr == NRF51_UICR) { // Special Case /* Write to the ERASE_UICR register to erase */ - adiv5_ap_mem_write(ap, NRF51_NVMC_ERASEUICR, 0x1); + target_mem_write32(target, NRF51_NVMC_ERASEUICR, 0x1); } else { // Standard Flash Page /* Write address of first word in page to erase it */ - adiv5_ap_mem_write(ap, NRF51_NVMC_ERASEPAGE, addr); + target_mem_write32(target, NRF51_NVMC_ERASEPAGE, addr); } /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -199,10 +194,10 @@ static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) } /* Return to read-only */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -212,7 +207,6 @@ static int nrf51_flash_erase(struct target_s *target, uint32_t addr, size_t len) static int nrf51_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; uint32_t data[2 + words]; @@ -225,10 +219,10 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Enable write */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(target, NRF51_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -244,30 +238,28 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, while(!target_halt_wait(target)); /* Return to read-only */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); + target_mem_write32(target, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN); return 0; } static bool nrf51_cmd_erase_all(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_out("erase..\n"); /* Enable erase */ - adiv5_ap_mem_write(ap, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); + target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) if(target_check_error(t)) return false; /* Erase all */ - adiv5_ap_mem_write(ap, NRF51_NVMC_ERASEALL, 1); + target_mem_write32(t, NRF51_NVMC_ERASEALL, 1); /* Poll for NVMC_READY */ - while(adiv5_ap_mem_read(ap, NRF51_NVMC_READY) == 0) + while (target_mem_read32(t, NRF51_NVMC_READY) == 0) if(target_check_error(t)) return false; @@ -276,28 +268,22 @@ static bool nrf51_cmd_erase_all(target *t) static bool nrf51_cmd_read_hwid(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t hwid = adiv5_ap_mem_read(ap, NRF51_FICR_CONFIGID) & 0xFFFF; + uint32_t hwid = target_mem_read32(t, NRF51_FICR_CONFIGID) & 0xFFFF; gdb_outf("Hardware ID: 0x%04X\n", hwid); return true; } static bool nrf51_cmd_read_fwid(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t fwid = (adiv5_ap_mem_read(ap, NRF51_FICR_CONFIGID) >> 16) & 0xFFFF; + uint32_t fwid = (target_mem_read32(t, NRF51_FICR_CONFIGID) >> 16) & 0xFFFF; gdb_outf("Firmware ID: 0x%04X\n", fwid); return true; } static bool nrf51_cmd_read_deviceid(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t deviceid_low = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEID_LOW); - uint32_t deviceid_high = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEID_HIGH); + uint32_t deviceid_low = target_mem_read32(t, NRF51_FICR_DEVICEID_LOW); + uint32_t deviceid_high = target_mem_read32(t, NRF51_FICR_DEVICEID_HIGH); gdb_outf("Device ID: 0x%08X%08X\n", deviceid_high, deviceid_low); @@ -305,11 +291,9 @@ static bool nrf51_cmd_read_deviceid(target *t) } static bool nrf51_cmd_read_deviceaddr(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t addr_type = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEADDRTYPE); - uint32_t addr_low = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEADDR_LOW); - uint32_t addr_high = adiv5_ap_mem_read(ap, NRF51_FICR_DEVICEADDR_HIGH) & 0xFFFF; + uint32_t addr_type = target_mem_read32(t, NRF51_FICR_DEVICEADDRTYPE); + uint32_t addr_low = target_mem_read32(t, NRF51_FICR_DEVICEADDR_LOW); + uint32_t addr_high = target_mem_read32(t, NRF51_FICR_DEVICEADDR_HIGH) & 0xFFFF; if ((addr_type & 1) == 0) { gdb_outf("Publicly Listed Address: 0x%04X%08X\n", addr_high, addr_low); diff --git a/src/sam3x.c b/src/sam3x.c index 211fc92..b9e59a0 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -148,9 +148,7 @@ static const char sam4s_xml_memory_map[] = "" bool sam3x_probe(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - target->idcode = adiv5_ap_mem_read(ap, SAM3X_CHIPID_CIDR); + target->idcode = target_mem_read32(target, SAM3X_CHIPID_CIDR); /* FIXME: Check for all variants with similar flash interface */ switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { @@ -165,7 +163,7 @@ bool sam3x_probe(struct target_s *target) return true; } - target->idcode = adiv5_ap_mem_read(ap, SAM3N_CHIPID_CIDR); + target->idcode = target_mem_read32(target, SAM3N_CHIPID_CIDR); switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3: case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3: @@ -177,21 +175,21 @@ bool sam3x_probe(struct target_s *target) target_add_commands(target, sam3x_cmd_list, "SAM3N"); return true; } - - target->idcode = adiv5_ap_mem_read(ap, SAM3S_CHIPID_CIDR); - switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { - case CHIPID_CIDR_ARCH_SAM3SxA | CHIPID_CIDR_EPROC_CM3: - case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3: - case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3: - target->driver = "Atmel SAM3S"; - target->xml_mem_map = sam3n_xml_memory_map; - target->flash_erase = sam3x_flash_erase; - target->flash_write = sam3x_flash_write; - target_add_commands(target, sam3x_cmd_list, "SAM3S"); - return true; - } - - target->idcode = adiv5_ap_mem_read(ap, SAM4S_CHIPID_CIDR); + + target->idcode = target_mem_read32(target, SAM3S_CHIPID_CIDR); + switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + case CHIPID_CIDR_ARCH_SAM3SxA | CHIPID_CIDR_EPROC_CM3: + case CHIPID_CIDR_ARCH_SAM3SxB | CHIPID_CIDR_EPROC_CM3: + case CHIPID_CIDR_ARCH_SAM3SxC | CHIPID_CIDR_EPROC_CM3: + target->driver = "Atmel SAM3S"; + target->xml_mem_map = sam3n_xml_memory_map; + target->flash_erase = sam3x_flash_erase; + target->flash_write = sam3x_flash_write; + target_add_commands(target, sam3x_cmd_list, "SAM3S"); + return true; + } + + target->idcode = target_mem_read32(target, SAM4S_CHIPID_CIDR); switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM4SxA | CHIPID_CIDR_EPROC_CM4: case CHIPID_CIDR_ARCH_SAM4SxB | CHIPID_CIDR_EPROC_CM4: @@ -210,18 +208,16 @@ bool sam3x_probe(struct target_s *target) static int sam3x_flash_cmd(struct target_s *target, uint32_t base, uint8_t cmd, uint16_t arg) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - DEBUG("%s: base = 0x%08x cmd = 0x%02X, arg = 0x%06X\n", __func__, base, cmd, arg); - adiv5_ap_mem_write(ap, EEFC_FCR(base), - EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8)); + target_mem_write32(target, EEFC_FCR(base), + EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8)); - while(!(adiv5_ap_mem_read(ap, EEFC_FSR(base)) & EEFC_FSR_FRDY)) + while (!(target_mem_read32(target, EEFC_FSR(base)) & EEFC_FSR_FRDY)) if(target_check_error(target)) return -1; - uint32_t sr = adiv5_ap_mem_read(ap, EEFC_FSR(base)); + uint32_t sr = target_mem_read32(target, EEFC_FSR(base)); return sr & EEFC_FSR_ERROR; } @@ -394,11 +390,10 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, static bool sam3x_cmd_gpnvm_get(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t base = sam3x_flash_base(t, 0, NULL); sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_GGPB, 0); - gdb_outf("GPNVM: 0x%08X\n", adiv5_ap_mem_read(ap, EEFC_FRR(base))); + gdb_outf("GPNVM: 0x%08X\n", target_mem_read32(t, EEFC_FRR(base))); return true; } diff --git a/src/samd.c b/src/samd.c index 2719763..68f5bc4 100644 --- a/src/samd.c +++ b/src/samd.c @@ -167,13 +167,12 @@ static const char samd_xml_memory_map[] = "" */ uint64_t samd_read_pid(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint64_t pid = 0; uint8_t i, j; /* Five PID registers to read LSB first */ for (i = 0, j = 0; i < 5; i++, j += 8) - pid |= (adiv5_ap_mem_read(ap, SAMD_DSU_PID(i)) & 0xFF) << j; + pid |= (target_mem_read32(target, SAMD_DSU_PID(i)) & 0xFF) << j; return pid; } @@ -182,13 +181,12 @@ uint64_t samd_read_pid(struct target_s *target) */ uint32_t samd_read_cid(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint64_t cid = 0; uint8_t i, j; /* Four CID registers to read LSB first */ for (i = 0, j = 0; i < 4; i++, j += 8) - cid |= (adiv5_ap_mem_read(ap, SAMD_DSU_CID(i)) & 0xFF) << j; + cid |= (target_mem_read32(target, SAMD_DSU_CID(i)) & 0xFF) << j; return cid; } @@ -200,8 +198,6 @@ uint32_t samd_read_cid(struct target_s *target) static void samd_reset(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - /** * SRST is not asserted here as it appears to reset the adiv5 * logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR. @@ -219,28 +215,28 @@ samd_reset(struct target_s *target) */ /* Read DHCSR here to clear S_RESET_ST bit before reset */ - adiv5_ap_mem_read(ap, CORTEXM_DHCSR); + target_mem_read32(target, CORTEXM_DHCSR); /* Request system reset from NVIC: SRST doesn't work correctly */ /* This could be VECTRESET: 0x05FA0001 (reset only core) * or SYSRESETREQ: 0x05FA0004 (system reset) */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, + target_mem_write32(target, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + target_mem_write32(target, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } /* Poll for release from reset */ - while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); + while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); /* Clear any target errors */ target_check_error(target); @@ -255,16 +251,15 @@ samd_reset(struct target_s *target) static void samd20_revB_detach(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); cortexm_detach(target); /* ---- Additional ---- */ /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, - SAMD_STATUSA_CRSTEXT); + target_mem_write32(target, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); } } @@ -277,16 +272,15 @@ samd20_revB_detach(struct target_s *target) static void samd20_revB_halt_resume(struct target_s *target, bool step) { - ADIv5_AP_t *ap = adiv5_target_ap(target); cortexm_halt_resume(target, step); /* ---- Additional ---- */ /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, - SAMD_STATUSA_CRSTEXT); + target_mem_write32(target, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); } } @@ -376,7 +370,6 @@ struct samd_descr samd_parse_device_id(uint32_t did) char variant_string[40]; bool samd_probe(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t cid = samd_read_cid(target); uint32_t pid = samd_read_pid(target); @@ -385,12 +378,13 @@ bool samd_probe(struct target_s *target) (pid & SAMD_PID_MASK) == SAMD_PID_CONST_VALUE) { /* Read the Device ID */ - uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID); + uint32_t did = target_mem_read32(target, SAMD_DSU_DID); /* If the Device ID matches */ if ((did & SAMD_DID_MASK) == SAMD_DID_CONST_VALUE) { - uint32_t ctrlstat = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT); + uint32_t ctrlstat = target_mem_read32(target, + SAMD_DSU_CTRLSTAT); struct samd_descr samd = samd_parse_device_id(did); /* Protected? */ @@ -442,11 +436,11 @@ bool samd_probe(struct target_s *target) if (!connect_assert_srst) { /* We'll have to release the target from * extended reset to make attach possible */ - if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) & SAMD_STATUSA_CRSTEXT) { /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + target_mem_write32(target, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_CRSTEXT); } } @@ -463,17 +457,15 @@ bool samd_probe(struct target_s *target) */ static void samd_lock_current_address(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - /* Issue the unlock command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK); + target_mem_write32(target, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK); } static void samd_unlock_current_address(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - /* Issue the unlock command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK); + target_mem_write32(target, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK); } /** @@ -481,23 +473,22 @@ static void samd_unlock_current_address(struct target_s *target) */ static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - addr &= ~(SAMD_ROW_SIZE - 1); len &= ~(SAMD_ROW_SIZE - 1); while (len) { /* Write address of first word in row to erase it */ /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ - adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, addr >> 1); + target_mem_write32(target, SAMD_NVMC_ADDRESS, addr >> 1); /* Unlock */ samd_unlock_current_address(target); /* Issue the erase command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW); + target_mem_write32(target, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW); /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -518,7 +509,6 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); - /* Find the size of our 32-bit data buffer */ uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; @@ -560,11 +550,11 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, samd_unlock_current_address(target); /* Issue the write page command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, + target_mem_write32(target, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE); } else { /* Write first word to set address */ - adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++; + target_mem_write32(target, addr, data[i]); addr += 4; i++; /* Unlock */ samd_unlock_current_address(target); @@ -583,7 +573,7 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, } /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(target)) return -1; @@ -599,18 +589,16 @@ static int samd_flash_write(struct target_s *target, uint32_t dest, */ static bool samd_cmd_erase_all(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Clear the DSU status bits */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + target_mem_write32(t, SAMD_DSU_CTRLSTAT, (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)); /* Erase all */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE); /* Poll for DSU Ready */ uint32_t status; - while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) & + while (((status = target_mem_read32(t, SAMD_DSU_CTRLSTAT)) & (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0) if(target_check_error(t)) return false; @@ -641,20 +629,19 @@ static bool samd_cmd_erase_all(target *t) */ static bool samd_set_flashlock(target *t, uint16_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t high = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH); - uint32_t low = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW); + uint32_t high = target_mem_read32(t, SAMD_NVM_USER_ROW_HIGH); + uint32_t low = target_mem_read32(t, SAMD_NVM_USER_ROW_LOW); /* Write address of a word in the row to erase it */ /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ - adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, SAMD_NVM_USER_ROW_LOW >> 1); + target_mem_write32(t, SAMD_NVMC_ADDRESS, SAMD_NVM_USER_ROW_LOW >> 1); /* Issue the erase command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEAUXROW); + target_mem_write32(t, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEAUXROW); /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(t)) return -1; @@ -662,12 +649,12 @@ static bool samd_set_flashlock(target *t, uint16_t value) high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000); /* Write back */ - adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_LOW, low); - adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_HIGH, high); + target_mem_write32(t, SAMD_NVM_USER_ROW_LOW, low); + target_mem_write32(t, SAMD_NVM_USER_ROW_HIGH, high); /* Issue the page write command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, - SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE); + target_mem_write32(t, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE); return true; } @@ -681,11 +668,9 @@ static bool samd_cmd_unlock_flash(target *t) } static bool samd_cmd_read_userrow(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_outf("User Row: 0x%08x%08x\n", - adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH), - adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW)); + target_mem_read32(t, SAMD_NVM_USER_ROW_HIGH), + target_mem_read32(t, SAMD_NVM_USER_ROW_LOW)); return true; } @@ -694,12 +679,10 @@ static bool samd_cmd_read_userrow(target *t) */ static bool samd_cmd_serial(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_outf("Serial Number: 0x"); for (uint32_t i = 0; i < 4; i++) { - gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD_NVM_SERIAL(i))); + gdb_outf("%08x", target_mem_read32(t, SAMD_NVM_SERIAL(i))); } gdb_outf("\n"); @@ -711,10 +694,8 @@ static bool samd_cmd_serial(target *t) */ static uint32_t samd_flash_size(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Read the Device ID */ - uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID); + uint32_t did = target_mem_read32(t, SAMD_DSU_DID); /* Mask off the device select bits */ uint8_t devsel = did & SAMD_DID_DEVSEL_MASK; @@ -727,21 +708,19 @@ static uint32_t samd_flash_size(target *t) */ static bool samd_cmd_mbist(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Write the memory parameters to the DSU */ - adiv5_ap_mem_write(ap, SAMD_DSU_ADDRESS, 0); - adiv5_ap_mem_write(ap, SAMD_DSU_LENGTH, samd_flash_size(t)); + target_mem_write32(t, SAMD_DSU_ADDRESS, 0); + target_mem_write32(t, SAMD_DSU_LENGTH, samd_flash_size(t)); /* Clear the fail bit */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_FAIL); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_FAIL); /* Write the MBIST command */ - adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_MBIST); + target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_CTRL_MBIST); /* Poll for DSU Ready */ uint32_t status; - while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) & + while (((status = target_mem_read32(t, SAMD_DSU_CTRLSTAT)) & (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0) if(target_check_error(t)) return false; @@ -755,7 +734,7 @@ static bool samd_cmd_mbist(target *t) /* Test the fail bit in Status A */ if (status & SAMD_STATUSA_FAIL) { gdb_outf("MBIST Fail @ 0x%08x\n", - adiv5_ap_mem_read(ap, SAMD_DSU_ADDRESS)); + target_mem_read32(t, SAMD_DSU_ADDRESS)); } else { gdb_outf("MBIST Passed!\n"); } @@ -767,13 +746,12 @@ static bool samd_cmd_mbist(target *t) */ static bool samd_cmd_ssb(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Issue the ssb command */ - adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB); + target_mem_write32(t, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB); /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) if(target_check_error(t)) return -1; diff --git a/src/stm32f1.c b/src/stm32f1.c index ca55fad..a746d5d 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -158,8 +158,7 @@ static const uint16_t stm32f1_flash_write_stub[] = { bool stm32f1_probe(struct target_s *target) { - - target->idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE) & 0xfff; + target->idcode = target_mem_read32(target, DBGMCU_IDCODE) & 0xfff; switch(target->idcode) { case 0x410: /* Medium density */ case 0x412: /* Low denisty */ @@ -189,7 +188,7 @@ bool stm32f1_probe(struct target_s *target) return true; } - target->idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE_F0) & 0xfff; + target->idcode = target_mem_read32(target, DBGMCU_IDCODE_F0) & 0xfff; switch(target->idcode) { case 0x444: /* STM32F03 RM0091 Rev.7 */ case 0x445: /* STM32F04 RM0091 Rev.7 */ @@ -223,33 +222,32 @@ bool stm32f1_probe(struct target_s *target) return false; } -static void stm32f1_flash_unlock(ADIv5_AP_t *ap) +static void stm32f1_flash_unlock(target *t) { - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY1); - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY2); + target_mem_write32(t, FLASH_KEYR, KEY1); + target_mem_write32(t, FLASH_KEYR, KEY2); } static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, size_t len, uint32_t pagesize) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; addr &= ~(pagesize - 1); len = (len + pagesize - 1) & ~(pagesize - 1); - stm32f1_flash_unlock(ap); + stm32f1_flash_unlock(target); while(len) { /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_PER); + target_mem_write32(target, FLASH_CR, FLASH_CR_PER); /* write address to FMA */ - adiv5_ap_mem_write(ap, FLASH_AR, addr); + target_mem_write32(target, FLASH_AR, addr); /* Flash page erase start instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_PER); + target_mem_write32(target, FLASH_CR, FLASH_CR_STRT | FLASH_CR_PER); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(target, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(target)) return -1; @@ -258,7 +256,7 @@ static int stm32f1_flash_erase(struct target_s *target, uint32_t addr, } /* Check for error */ - sr = adiv5_ap_mem_read(ap, FLASH_SR); + sr = target_mem_read32(target, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return -1; @@ -278,7 +276,6 @@ static int stm32md_flash_erase(struct target_s *target, uint32_t addr, size_t le static int stm32f1_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; if (words > 256) @@ -304,7 +301,7 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, while(!target_halt_wait(target)); /* Check for error */ - if (adiv5_ap_mem_read(ap, FLASH_SR) & SR_ERROR_MASK) + if (target_mem_read32(target, FLASH_SR) & SR_ERROR_MASK) return -1; return 0; @@ -312,21 +309,19 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, static bool stm32f1_cmd_erase_mass(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - stm32f1_flash_unlock(ap); + stm32f1_flash_unlock(t); /* Flash mass erase start instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_MER); - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; /* Check for error */ - uint16_t sr = adiv5_ap_mem_read(ap, FLASH_SR); + uint16_t sr = target_mem_read32(t, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return false; @@ -335,14 +330,12 @@ static bool stm32f1_cmd_erase_mass(target *t) static bool stm32f1_option_erase(target *t) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - /* Erase option bytes instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_OPTER | FLASH_CR_OPTWRE); - adiv5_ap_mem_write(ap, FLASH_CR, - FLASH_CR_STRT | FLASH_CR_OPTER | FLASH_CR_OPTWRE); + target_mem_write32(t, FLASH_CR, FLASH_CR_OPTER | FLASH_CR_OPTWRE); + target_mem_write32(t, FLASH_CR, + FLASH_CR_STRT | FLASH_CR_OPTER | FLASH_CR_OPTWRE); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; return true; @@ -350,15 +343,13 @@ static bool stm32f1_option_erase(target *t) static bool stm32f1_option_write_erased(target *t, uint32_t addr, uint16_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - if (value == 0xffff) return true; /* Erase option bytes instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_OPTPG | FLASH_CR_OPTWRE); - adiv5_ap_mem_write_halfword(ap, addr, value); + target_mem_write32(t, FLASH_CR, FLASH_CR_OPTPG | FLASH_CR_OPTWRE); + target_mem_write16(t, addr, value); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; return true; @@ -366,7 +357,6 @@ static bool stm32f1_option_write_erased(target *t, uint32_t addr, uint16_t value static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); uint16_t opt_val[8]; int i, index; @@ -375,7 +365,7 @@ static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value) return false; /* Retrieve old values */ for (i = 0; i < 16; i = i +4) { - uint32_t val = adiv5_ap_mem_read(ap, FLASH_OBP_RDP + i); + uint32_t val = target_mem_read32(t, FLASH_OBP_RDP + i); opt_val[i/2] = val & 0xffff; opt_val[i/2 +1] = val >> 16; } @@ -398,7 +388,6 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) { uint32_t addr, val; uint32_t flash_obp_rdp_key; - ADIv5_AP_t *ap = adiv5_target_ap(t); uint32_t rdprt; switch(t->idcode) { @@ -409,10 +398,10 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) break; default: flash_obp_rdp_key = FLASH_OBP_RDP_KEY; } - rdprt = (adiv5_ap_mem_read(ap, FLASH_OBR) & FLASH_OBR_RDPRT); - stm32f1_flash_unlock(ap); - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, KEY1); - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, KEY2); + rdprt = target_mem_read32(t, FLASH_OBR) & FLASH_OBR_RDPRT; + stm32f1_flash_unlock(t); + target_mem_write32(t, FLASH_OPTKEYR, KEY1); + target_mem_write32(t, FLASH_OPTKEYR, KEY2); if ((argc == 2) && !strcmp(argv[1], "erase")) { stm32f1_option_erase(t); @@ -432,7 +421,7 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) if (0 && flash_obp_rdp_key == FLASH_OBP_RDP_KEY_F3) { /* Reload option bytes on F0 and F3*/ - val = adiv5_ap_mem_read(ap, FLASH_CR); + val = target_mem_read32(t, FLASH_CR); val |= FLASH_CR_OBL_LAUNCH; stm32f1_option_write(t, FLASH_CR, val); val &= ~FLASH_CR_OBL_LAUNCH; @@ -441,7 +430,7 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[]) for (int i = 0; i < 0xf; i += 4) { addr = 0x1ffff800 + i; - val = adiv5_ap_mem_read(ap, addr); + val = target_mem_read32(t, addr); gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF); gdb_outf("0x%08X: 0x%04X\n", addr + 2, val >> 16); } diff --git a/src/stm32f4.c b/src/stm32f4.c index 58d1328..2a8bc21 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -162,7 +162,7 @@ bool stm32f4_probe(struct target_s *target) { uint32_t idcode; - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE); + idcode = target_mem_read32(target, DBGMCU_IDCODE); switch(idcode & 0xFFF) { case 0x411: /* Documented to be 0x413! This is what I read... */ case 0x413: /* F407VGT6 */ @@ -180,25 +180,24 @@ bool stm32f4_probe(struct target_s *target) return false; } -static void stm32f4_flash_unlock(ADIv5_AP_t *ap) +static void stm32f4_flash_unlock(target *t) { - if (adiv5_ap_mem_read(ap, FLASH_CR) & FLASH_CR_LOCK) { + if (target_mem_read32(t, FLASH_CR) & FLASH_CR_LOCK) { /* Enable FPEC controller access */ - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY1); - adiv5_ap_mem_write(ap, FLASH_KEYR, KEY2); + target_mem_write32(t, FLASH_KEYR, KEY1); + target_mem_write32(t, FLASH_KEYR, KEY2); } } static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; uint32_t cr; uint32_t pagesize; addr &= 0x07FFC000; - stm32f4_flash_unlock(ap); + stm32f4_flash_unlock(target); while(len) { if (addr < 0x10000) { /* Sector 0..3 */ @@ -215,12 +214,12 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le } cr |= FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER; /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, cr); + target_mem_write32(target, FLASH_CR, cr); /* write address to FMA */ - adiv5_ap_mem_write(ap, FLASH_CR, cr | FLASH_CR_STRT); + target_mem_write32(target, FLASH_CR, cr | FLASH_CR_STRT); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while(target_mem_read32(target, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(target)) return -1; @@ -229,7 +228,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le } /* Check for error */ - sr = adiv5_ap_mem_read(ap, FLASH_SR); + sr = target_mem_read32(target, FLASH_SR); if(sr & SR_ERROR_MASK) return -1; @@ -239,7 +238,6 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, size_t le static int stm32f4_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t offset = dest % 4; uint32_t words = (offset + len + 3) / 4; uint32_t data[2 + words]; @@ -264,7 +262,7 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest, while(!target_halt_wait(target)); /* Check for error */ - sr = adiv5_ap_mem_read(ap, FLASH_SR); + sr = target_mem_read32(target, FLASH_SR); if(sr & SR_ERROR_MASK) return -1; @@ -276,17 +274,15 @@ static bool stm32f4_cmd_erase_mass(target *t) const char spinner[] = "|/-\\"; int spinindex = 0; - ADIv5_AP_t *ap = adiv5_target_ap(t); - gdb_out("Erasing flash... This may take a few seconds. "); - stm32f4_flash_unlock(ap); + stm32f4_flash_unlock(t); /* Flash mass erase start instruction */ - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_MER); - adiv5_ap_mem_write(ap, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_MER); + target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_MER); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) { + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) { gdb_outf("\b%c", spinner[spinindex++ % 4]); if(target_check_error(t)) { gdb_out("\n"); @@ -296,7 +292,7 @@ static bool stm32f4_cmd_erase_mass(target *t) gdb_out("\n"); /* Check for error */ - uint16_t sr = adiv5_ap_mem_read(ap, FLASH_SR); + uint16_t sr = target_mem_read32(t, FLASH_SR); if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP)) return false; @@ -305,23 +301,21 @@ static bool stm32f4_cmd_erase_mass(target *t) static bool stm32f4_option_write(target *t, uint32_t value) { - ADIv5_AP_t *ap = adiv5_target_ap(t); - - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, OPTKEY1); - adiv5_ap_mem_write(ap, FLASH_OPTKEYR, OPTKEY2); + target_mem_write32(t, FLASH_OPTKEYR, OPTKEY1); + target_mem_write32(t, FLASH_OPTKEYR, OPTKEY2); value &= ~FLASH_OPTCR_RESERVED; - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return -1; /* WRITE option bytes instruction */ - adiv5_ap_mem_write(ap, FLASH_OPTCR, value); - adiv5_ap_mem_write(ap, FLASH_OPTCR, value | FLASH_OPTCR_OPTSTRT); + target_mem_write32(t, FLASH_OPTCR, value); + target_mem_write32(t, FLASH_OPTCR, value | FLASH_OPTCR_OPTSTRT); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY) + while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) if(target_check_error(t)) return false; - adiv5_ap_mem_write(ap, FLASH_OPTCR, value | FLASH_OPTCR_OPTLOCK); + target_mem_write32(t, FLASH_OPTCR, value | FLASH_OPTCR_OPTLOCK); return true; } @@ -329,8 +323,6 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[]) { uint32_t addr, val; - ADIv5_AP_t *ap = adiv5_target_ap(t); - if ((argc == 2) && !strcmp(argv[1], "erase")) { stm32f4_option_write(t, 0x0fffaaed); } @@ -344,7 +336,7 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[]) for (int i = 0; i < 0xf; i += 8) { addr = 0x1fffC000 + i; - val = adiv5_ap_mem_read(ap, addr); + val = target_mem_read32(t, addr); gdb_outf("0x%08X: 0x%04X\n", addr, val & 0xFFFF); } return true; diff --git a/src/stm32l0.c b/src/stm32l0.c index 028f2a1..28088a8 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -72,13 +72,13 @@ to regain control of the target after the option byte reload. stm32l0_option_write(t, 0x1ff80000, 0xffff0000); - adiv5_ap_mem_write(ap, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); + target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); stm32l0_option_write(t, 0x1ff80000, 0xff5500aa); - adiv5_ap_mem_write(ap, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); + target_mem_write32(target, STM32L0_NVM_PECR, STM32L0_NVM_PECR_OBL_LAUNCH); uint32_t sr; do { - sr = adiv5_ap_mem_read(ap, STM32L0_NVM_SR); + sr = target_mem_read32(target, STM32L0_NVM_SR); } while (sr & STM32L0_NVM_SR_BSY); o Errors. We probably should clear SR errors immediately after @@ -288,7 +288,7 @@ bool stm32l0_probe(struct target_s* target) #if defined(CONFIG_STM32L1) - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), + idcode = target_mem_read32(target, STM32L1_DBGMCU_IDCODE_PHYS) & 0xfff; switch (idcode) { case 0x416: /* CAT. 1 device */ @@ -306,7 +306,7 @@ bool stm32l0_probe(struct target_s* target) } #endif - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), + idcode = target_mem_read32(target, STM32L0_DBGMCU_IDCODE_PHYS) & 0xfff; switch (idcode) { default: @@ -327,42 +327,42 @@ bool stm32l0_probe(struct target_s* target) /** Lock the NVM control registers preventing writes or erases. */ -static void stm32lx_nvm_lock(ADIv5_AP_t* ap, uint32_t nvm) +static void stm32lx_nvm_lock(target *t, uint32_t nvm) { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); } /** Unlock the NVM control registers for modifying program or data flash. Returns true if the unlock succeeds. */ -static bool stm32lx_nvm_prog_data_unlock(ADIv5_AP_t* ap, uint32_t nvm) +static bool stm32lx_nvm_prog_data_unlock(target* t, uint32_t nvm) { /* Always lock first because that's the only way to know that the unlock can succeed on the STM32L0's. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY2); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); + target_mem_write32(t, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY1); + target_mem_write32(t, STM32Lx_NVM_PRGKEYR(nvm), STM32Lx_NVM_PRGKEY2); - return !(adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)) + return !(target_mem_read32(t, STM32Lx_NVM_PECR(nvm)) & STM32Lx_NVM_PECR_PRGLOCK); } /** Unlock the NVM control registers for modifying option bytes. Returns true if the unlock succeeds. */ -static bool stm32lx_nvm_opt_unlock(ADIv5_AP_t* ap, uint32_t nvm) +static bool stm32lx_nvm_opt_unlock(target *t, uint32_t nvm) { /* Always lock first because that's the only way to know that the unlock can succeed on the STM32L0's. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); - adiv5_ap_mem_write(ap, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY1); - adiv5_ap_mem_write(ap, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY2); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PELOCK); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY1); + target_mem_write32(t, STM32Lx_NVM_PEKEYR(nvm), STM32Lx_NVM_PEKEY2); + target_mem_write32(t, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY1); + target_mem_write32(t, STM32Lx_NVM_OPTKEYR(nvm), STM32Lx_NVM_OPTKEY2); - return !(adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)) + return !(target_mem_read32(t, STM32Lx_NVM_PECR(nvm)) & STM32Lx_NVM_PECR_OPTLOCK); } @@ -400,8 +400,7 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, while (!target_halt_wait(target)) ; { - ADIv5_AP_t* ap = adiv5_target_ap(target); - if (adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)) + if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_ERR_M) return -1; } @@ -477,8 +476,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, while (!target_halt_wait(target)) ; - if (adiv5_ap_mem_read(adiv5_target_ap(target), - STM32Lx_NVM_SR(nvm)) + if (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_ERR_M) return -1; } @@ -557,7 +555,6 @@ static int stm32lx_nvm_write(struct target_s* target, static int stm32lx_nvm_prog_erase(struct target_s* target, uint32_t addr, size_t len) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const size_t page_size = stm32lx_nvm_prog_page_size(target); const uint32_t nvm = stm32lx_nvm_phys(target); @@ -565,15 +562,15 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, len += (addr & 3); addr &= ~3; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_PROG); { - uint32_t pecr = adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)); + uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); if ((pecr & (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) != (STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_ERASE)) return -1; @@ -581,22 +578,22 @@ static int stm32lx_nvm_prog_erase(struct target_s* target, /* Clear errors. Note that this only works when we wait for the NVM block to complete the last operation. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); + target_mem_write32(target, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); while (len > 0) { /* Write first word of page to 0 */ - adiv5_ap_mem_write(ap, addr, 0); + target_mem_write32(target, addr, 0); len -= page_size; addr += page_size; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) return -1; if (sr & STM32Lx_NVM_SR_BSY) @@ -618,7 +615,6 @@ static int stm32lx_nvm_prog_write(struct target_s* target, const uint8_t* source_8, size_t size) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const uint32_t nvm = stm32lx_nvm_phys(target); const bool is_stm32l1 = stm32lx_is_stm32l1(target); @@ -629,7 +625,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, if ((destination & 3) || (size & 3)) return -1; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; const size_t half_page_size = stm32lx_nvm_prog_page_size(target)/2; @@ -639,7 +635,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, /* Wait for BSY to clear because we cannot write the PECR until the previous operation completes on STM32Lxxx. */ - while (adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)) + while (target_mem_read32(target, STM32Lx_NVM_SR(nvm)) & STM32Lx_NVM_SR_BSY) if (target_check_error(target)) { return -1; @@ -649,7 +645,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, // than a half page to write if (size < half_page_size || (destination & (half_page_size - 1))) { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), is_stm32l1 ? 0 : STM32Lx_NVM_PECR_PROG); @@ -666,7 +662,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, } // Or we are writing a half-page(s) else { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_PROG | STM32Lx_NVM_PECR_FPRG); @@ -679,11 +675,11 @@ static int stm32lx_nvm_prog_write(struct target_s* target, } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) { return -1; } @@ -706,7 +702,6 @@ static int stm32lx_nvm_prog_write(struct target_s* target, static int stm32lx_nvm_data_erase(struct target_s* target, uint32_t addr, size_t len) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const size_t page_size = stm32lx_nvm_data_page_size(target); const uint32_t nvm = stm32lx_nvm_phys(target); @@ -714,15 +709,15 @@ static int stm32lx_nvm_data_erase(struct target_s* target, len += (addr & 3); addr &= ~3; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; /* Flash data erase instruction */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA); { - uint32_t pecr = adiv5_ap_mem_read(ap, STM32Lx_NVM_PECR(nvm)); + uint32_t pecr = target_mem_read32(target, STM32Lx_NVM_PECR(nvm)); if ((pecr & (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) != (STM32Lx_NVM_PECR_ERASE | STM32Lx_NVM_PECR_DATA)) return -1; @@ -730,18 +725,18 @@ static int stm32lx_nvm_data_erase(struct target_s* target, while (len > 0) { /* Write first word of page to 0 */ - adiv5_ap_mem_write(ap, addr, 0); + target_mem_write32(target, addr, 0); len -= page_size; addr += page_size; } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) return -1; if (sr & STM32Lx_NVM_SR_BSY) @@ -764,22 +759,21 @@ static int stm32lx_nvm_data_write(struct target_s* target, const uint8_t* source_8, size_t size) { - ADIv5_AP_t* ap = adiv5_target_ap(target); const uint32_t nvm = stm32lx_nvm_phys(target); const bool is_stm32l1 = stm32lx_is_stm32l1(target); uint32_t* source = (uint32_t*) source_8; - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) + if (!stm32lx_nvm_prog_data_unlock(target, nvm)) return -1; - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(target, STM32Lx_NVM_PECR(nvm), is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA); while (size) { size -= 4; uint32_t v = *source++; - adiv5_ap_mem_write(ap, destination, v); + target_mem_write32(target, destination, v); destination += 4; if (target_check_error(target)) @@ -787,11 +781,11 @@ static int stm32lx_nvm_data_write(struct target_s* target, } /* Disable further programming by locking PECR */ - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(target, nvm); /* Wait for completion or an error */ while (1) { - uint32_t sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + uint32_t sr = target_mem_read32(target, STM32Lx_NVM_SR(nvm)); if (target_check_error(target)) return -1; if (sr & STM32Lx_NVM_SR_BSY) @@ -813,16 +807,15 @@ static int stm32lx_nvm_data_write(struct target_s* target, The return value is true if the write succeeded. */ static bool stm32lx_option_write(target *t, uint32_t address, uint32_t value) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); /* Erase and program option in one go. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_FIX); - adiv5_ap_mem_write(ap, address, value); + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_FIX); + target_mem_write32(t, address, value); uint32_t sr; do { - sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); } while (sr & STM32Lx_NVM_SR_BSY); return !(sr & STM32Lx_NVM_SR_ERR_M); @@ -839,29 +832,28 @@ static bool stm32lx_option_write(target *t, uint32_t address, uint32_t value) static bool stm32lx_eeprom_write(target *t, uint32_t address, size_t cb, uint32_t value) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); const bool is_stm32l1 = stm32lx_is_stm32l1(t); /* Clear errors. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); + target_mem_write32(t, STM32Lx_NVM_SR(nvm), STM32Lx_NVM_SR_ERR_M); /* Erase and program option in one go. */ - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), (is_stm32l1 ? 0 : STM32Lx_NVM_PECR_DATA) | STM32Lx_NVM_PECR_FIX); if (cb == 4) - adiv5_ap_mem_write(ap, address, value); + target_mem_write32(t, address, value); else if (cb == 2) - adiv5_ap_mem_write_halfword(ap, address, value); + target_mem_write16(t, address, value); else if (cb == 1) - adiv5_ap_mem_write_byte(ap, address, value); + target_mem_write8(t, address, value); else return false; uint32_t sr; do { - sr = adiv5_ap_mem_read(ap, STM32Lx_NVM_SR(nvm)); + sr = target_mem_read32(t, STM32Lx_NVM_SR(nvm)); } while (sr & STM32Lx_NVM_SR_BSY); return !(sr & STM32Lx_NVM_SR_ERR_M); @@ -888,11 +880,10 @@ static bool stm32lx_cmd_stubs(target* t, static bool stm32lx_cmd_option(target* t, int argc, char** argv) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); const size_t opt_size = stm32lx_nvm_option_size(t); - if (!stm32lx_nvm_opt_unlock(ap, nvm)) { + if (!stm32lx_nvm_opt_unlock(t, nvm)) { gdb_out("unable to unlock NVM option bytes\n"); return true; } @@ -900,7 +891,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) size_t cb = strlen(argv[1]); if (argc == 2 && !strncasecmp(argv[1], "obl_launch", cb)) { - adiv5_ap_mem_write(ap, STM32Lx_NVM_PECR(nvm), + target_mem_write32(t, STM32Lx_NVM_PECR(nvm), STM32Lx_NVM_PECR_OBL_LAUNCH); } else if (argc == 4 && !strncasecmp(argv[1], "raw", cb)) { @@ -934,7 +925,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) /* Report the current option values */ for(unsigned i = 0; i < opt_size; i += sizeof(uint32_t)) { uint32_t addr = STM32Lx_NVM_OPT_PHYS + i; - uint32_t val = adiv5_ap_mem_read(ap, addr); + uint32_t val = target_mem_read32(t, addr); gdb_outf("0x%08x: 0x%04x 0x%04x %s\n", addr, val & 0xffff, (val >> 16) & 0xffff, ((val & 0xffff) == ((~val >> 16) & 0xffff)) @@ -942,7 +933,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) } if (stm32lx_is_stm32l1(t)) { - uint32_t optr = adiv5_ap_mem_read(ap, STM32Lx_NVM_OPTR(nvm)); + uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm)); uint8_t rdprot = (optr >> STM32L1_NVM_OPTR_RDPROT_S) & STM32L1_NVM_OPTR_RDPROT_M; if (rdprot == STM32L1_NVM_OPTR_RDPROT_0) @@ -964,7 +955,7 @@ static bool stm32lx_cmd_option(target* t, int argc, char** argv) (optr & STM32L1_NVM_OPTR_nBFB2) ? 1 : 0); } else { - uint32_t optr = adiv5_ap_mem_read(ap, STM32Lx_NVM_OPTR(nvm)); + uint32_t optr = target_mem_read32(t, STM32Lx_NVM_OPTR(nvm)); uint8_t rdprot = (optr >> STM32L0_NVM_OPTR_RDPROT_S) & STM32L0_NVM_OPTR_RDPROT_M; if (rdprot == STM32L0_NVM_OPTR_RDPROT_0) @@ -997,17 +988,16 @@ usage: STM32Lx_NVM_OPT_PHYS + opt_size - sizeof(uint32_t)); done: - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(t, nvm); return true; } static bool stm32lx_cmd_eeprom(target* t, int argc, char** argv) { - ADIv5_AP_t* ap = adiv5_target_ap(t); const uint32_t nvm = stm32lx_nvm_phys(t); - if (!stm32lx_nvm_prog_data_unlock(ap, nvm)) { + if (!stm32lx_nvm_prog_data_unlock(t, nvm)) { gdb_out("unable to unlock EEPROM\n"); return true; } @@ -1061,6 +1051,6 @@ usage: + stm32lx_nvm_eeprom_size(t)); done: - stm32lx_nvm_lock(ap, nvm); + stm32lx_nvm_lock(t, nvm); return true; } diff --git a/src/stm32l1.c b/src/stm32l1.c index c72cccd..8e63347 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -87,7 +87,7 @@ bool stm32l1_probe(struct target_s *target) { uint32_t idcode; - idcode = adiv5_ap_mem_read(adiv5_target_ap(target), STM32L1_DBGMCU_IDCODE); + idcode = target_mem_read32(target, STM32L1_DBGMCU_IDCODE); switch(idcode & 0xFFF) { case 0x416: /* CAT. 1 device */ case 0x429: /* CAT. 2 device */ @@ -105,45 +105,44 @@ bool stm32l1_probe(struct target_s *target) return false; } -static void stm32l1_flash_unlock(ADIv5_AP_t *ap) +static void stm32l1_flash_unlock(target *t) { - adiv5_ap_mem_write(ap, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY1); - adiv5_ap_mem_write(ap, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY2); - adiv5_ap_mem_write(ap, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY1); - adiv5_ap_mem_write(ap, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY2); + target_mem_write32(t, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY1); + target_mem_write32(t, STM32L1_FLASH_PEKEYR, STM32L1_PEKEY2); + target_mem_write32(t, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY1); + target_mem_write32(t, STM32L1_FLASH_PRGKEYR, STM32L1_PRGKEY2); } static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; addr &= ~255; len &= ~255; - stm32l1_flash_unlock(ap); + stm32l1_flash_unlock(target); /* Flash page erase instruction */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_ERASE | STM32L1_FLASH_PECR_PROG); + target_mem_write32(target, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_ERASE | STM32L1_FLASH_PECR_PROG); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) + while(target_mem_read32(target, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) if(target_check_error(target)) return -1; while(len) { /* Write first word of page to 0 */ - adiv5_ap_mem_write(ap, addr, 0); + target_mem_write32(target, addr, 0); len -= 256; addr += 256; } /* Disable programming mode */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, 0); + target_mem_write32(target, STM32L1_FLASH_PECR, 0); /* Check for error */ - sr = adiv5_ap_mem_read(ap, STM32L1_FLASH_SR); + sr = target_mem_read32(target, STM32L1_FLASH_SR); if ((sr & STM32L1_FLASH_SR_ERROR_MASK) || !(sr & STM32L1_FLASH_SR_EOP)) return -1; @@ -153,7 +152,6 @@ static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, size_t le static int stm32l1_flash_write(struct target_s *target, uint32_t dest, const uint8_t *src, size_t len) { - ADIv5_AP_t *ap = adiv5_target_ap(target); uint16_t sr; /* Handle non word-aligned start */ @@ -164,7 +162,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, wlen = len; memcpy((uint8_t *)&data + (dest & 3), src, wlen); - adiv5_ap_mem_write(ap, dest & ~3, data); + target_mem_write32(target, dest & ~3, data); src += wlen; dest += wlen; len -= wlen; @@ -185,10 +183,10 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, /* Write half-pages */ if(len > 128) { /* Enable half page mode */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_FPRG | STM32L1_FLASH_PECR_PROG); + target_mem_write32(target, STM32L1_FLASH_PECR, STM32L1_FLASH_PECR_FPRG | STM32L1_FLASH_PECR_PROG); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) + while(target_mem_read32(target, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) if(target_check_error(target)) return -1; @@ -198,10 +196,10 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, len -= len & ~127; /* Disable half page mode */ - adiv5_ap_mem_write(ap, STM32L1_FLASH_PECR, 0); + target_mem_write32(target, STM32L1_FLASH_PECR, 0); /* Read FLASH_SR to poll for BSY bit */ - while(adiv5_ap_mem_read(ap, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) + while(target_mem_read32(target, STM32L1_FLASH_SR) & STM32L1_FLASH_SR_BSY) if(target_check_error(target)) return -1; } @@ -219,11 +217,11 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, uint32_t data = 0; memcpy((uint8_t *)&data, src, len); - adiv5_ap_mem_write(ap, dest, data); + target_mem_write32(target, dest, data); } /* Check for error */ - sr = adiv5_ap_mem_read(ap, STM32L1_FLASH_SR); + sr = target_mem_read32(target, STM32L1_FLASH_SR); if ((sr & STM32L1_FLASH_SR_ERROR_MASK) || !(sr & STM32L1_FLASH_SR_EOP)) return -1; -- cgit v1.2.3 From c3f798438a65b284adec281e7ddb4e8268ff4f4b Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 15 Mar 2015 17:12:31 -0700 Subject: Remove abstraction of adiv5_dp_write. Both implementations were identical. --- src/adiv5.c | 5 +++++ src/adiv5_jtagdp.c | 7 ------- src/adiv5_swdp.c | 9 +-------- src/include/adiv5.h | 7 +------ 4 files changed, 7 insertions(+), 21 deletions(-) (limited to 'src/include/adiv5.h') diff --git a/src/adiv5.c b/src/adiv5.c index 2179ca6..f2421ce 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -70,6 +70,11 @@ void adiv5_ap_unref(ADIv5_AP_t *ap) } } +void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) +{ + dp->low_access(dp, ADIV5_LOW_WRITE, addr, value); +} + void adiv5_dp_init(ADIv5_DP_t *dp) { uint32_t ctrlstat; diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index eb60caa..5049e3c 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -36,7 +36,6 @@ #define IR_DPACC 0xA #define IR_APACC 0xB -static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr); static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp); @@ -52,7 +51,6 @@ void adiv5_jtag_dp_handler(jtag_dev_t *dev) dp->dev = dev; dp->idcode = dev->idcode; - dp->dp_write = adiv5_jtagdp_write; dp->dp_read = adiv5_jtagdp_read; dp->error = adiv5_jtagdp_error; dp->low_access = adiv5_jtagdp_low_access; @@ -60,11 +58,6 @@ void adiv5_jtag_dp_handler(jtag_dev_t *dev) adiv5_dp_init(dp); } -static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) -{ - adiv5_jtagdp_low_access(dp, ADIV5_LOW_WRITE, addr, value); -} - static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr) { adiv5_jtagdp_low_access(dp, ADIV5_LOW_READ, addr, 0); diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index 3e775cc..9ac791a 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -33,7 +33,6 @@ #define SWDP_ACK_WAIT 0x02 #define SWDP_ACK_FAULT 0x04 -static void adiv5_swdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr); static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp); @@ -64,7 +63,6 @@ int adiv5_swdp_scan(void) return -1; } - dp->dp_write = adiv5_swdp_write; dp->dp_read = adiv5_swdp_read; dp->error = adiv5_swdp_error; dp->low_access = adiv5_swdp_low_access; @@ -78,11 +76,6 @@ int adiv5_swdp_scan(void) return target_list?1:0; } -static void adiv5_swdp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) -{ - adiv5_swdp_low_access(dp, ADIV5_LOW_WRITE, addr, value); -} - static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr) { if (addr & ADIV5_APnDP) { @@ -111,7 +104,7 @@ static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp) if(err & ADIV5_DP_CTRLSTAT_WDATAERR) clr |= ADIV5_DP_ABORT_WDERRCLR; - adiv5_swdp_write(dp, ADIV5_DP_ABORT, clr); + adiv5_dp_write(dp, ADIV5_DP_ABORT, clr); dp->fault = 0; return err; diff --git a/src/include/adiv5.h b/src/include/adiv5.h index 4bc3905..6896f6d 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -109,7 +109,6 @@ typedef struct ADIv5_DP_s { bool allow_timeout; - void (*dp_write)(struct ADIv5_DP_s *dp, uint16_t addr, uint32_t value); uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr); uint32_t (*error)(struct ADIv5_DP_s *dp); @@ -123,11 +122,6 @@ typedef struct ADIv5_DP_s { }; } ADIv5_DP_t; -static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value) -{ - dp->dp_write(dp, addr, value); -} - static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr) { return dp->dp_read(dp, addr); @@ -160,6 +154,7 @@ typedef struct ADIv5_AP_s { } ADIv5_AP_t; void adiv5_dp_init(ADIv5_DP_t *dp); +void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value); void adiv5_dp_ref(ADIv5_DP_t *dp); void adiv5_ap_ref(ADIv5_AP_t *ap); -- cgit v1.2.3 From d6225eec763bd49ef3cb8edac5138df9e524a073 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sat, 28 Feb 2015 20:53:25 -0800 Subject: Raise timeout exception when target is in WFI. Ignore the exception when polling for halt, and report the exception to the user if halting the target fails. Remove old allow_timeout flag in DP struct that's no longer needed.--- src/adiv5_jtagdp.c | 4 ++-- src/adiv5_swdp.c | 4 ++-- src/cortexm.c | 29 +++++++++++++++++++---------- src/include/adiv5.h | 4 ---- 4 files changed, 23 insertions(+), 18 deletions(-) (limited to 'src/include/adiv5.h') diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c index bb478d1..a460113 100644 --- a/src/adiv5_jtagdp.c +++ b/src/adiv5_jtagdp.c @@ -91,8 +91,8 @@ static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, ack = response & 0x07; } while(--tries && (ack == JTAGDP_ACK_WAIT)); - if (dp->allow_timeout && (ack == JTAGDP_ACK_WAIT)) - return 0; + if (ack == JTAGDP_ACK_WAIT) + raise_exception(EXCEPTION_TIMEOUT, "JTAG-DP ACK timeout"); if((ack != JTAGDP_ACK_OK)) raise_exception(EXCEPTION_ERROR, "JTAG-DP invalid ACK"); diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c index d5193ac..1a6b158 100644 --- a/src/adiv5_swdp.c +++ b/src/adiv5_swdp.c @@ -136,8 +136,8 @@ static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, ack = swdptap_seq_in(3); } while(--tries && ack == SWDP_ACK_WAIT); - if (dp->allow_timeout && (ack == SWDP_ACK_WAIT)) - return 0; + if (ack == SWDP_ACK_WAIT) + raise_exception(EXCEPTION_TIMEOUT, "SWDP ACK timeout"); if(ack == SWDP_ACK_FAULT) { dp->fault = 1; diff --git a/src/cortexm.c b/src/cortexm.c index a129a3c..f20f282 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -29,6 +29,7 @@ * There are way too many magic numbers used here. */ #include "general.h" +#include "exception.h" #include "jtagtap.h" #include "jtag_scan.h" #include "adiv5.h" @@ -467,12 +468,15 @@ cortexm_reset(struct target_s *target) static void cortexm_halt_request(struct target_s *target) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - - ap->dp->allow_timeout = false; - target_mem_write32(target, CORTEXM_DHCSR, - CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | - CORTEXM_DHCSR_C_DEBUGEN); + volatile struct exception e; + TRY_CATCH (e, EXCEPTION_TIMEOUT) { + target_mem_write32(target, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY | + CORTEXM_DHCSR_C_HALT | + CORTEXM_DHCSR_C_DEBUGEN); + } + if (e.type) { + gdb_out("Timeout sending interrupt, is target in WFI?\n"); + } } static int @@ -480,10 +484,16 @@ cortexm_halt_wait(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = ap->priv; - if (!(target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT)) - return 0; - ap->dp->allow_timeout = false; + uint32_t dhcsr = 0; + volatile struct exception e; + TRY_CATCH (e, EXCEPTION_TIMEOUT) { + /* If this times out because the target is in WFI then + * the target is still running. */ + dhcsr = target_mem_read32(target, CORTEXM_DHCSR); + } + if (e.type || !(dhcsr & CORTEXM_DHCSR_S_HALT)) + return 0; /* We've halted. Let's find out why. */ uint32_t dfsr = target_mem_read32(target, CORTEXM_DFSR); @@ -543,7 +553,6 @@ void cortexm_halt_resume(struct target_s *target, bool step) } target_mem_write32(target, CORTEXM_DHCSR, dhcsr); - ap->dp->allow_timeout = true; } static int cortexm_fault_unwind(struct target_s *target) diff --git a/src/include/adiv5.h b/src/include/adiv5.h index 6896f6d..12d3bf4 100644 --- a/src/include/adiv5.h +++ b/src/include/adiv5.h @@ -107,12 +107,8 @@ typedef struct ADIv5_DP_s { uint32_t idcode; - bool allow_timeout; - uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr); - uint32_t (*error)(struct ADIv5_DP_s *dp); - uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value); -- cgit v1.2.3