From ee3af96a736139b71678a0e590865f9ffafc2f35 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 15 Mar 2015 14:31:57 -0700 Subject: Consolidate target_mem_read* and target_mem_write* methods. There are now only mem_read and mem_write, that must handle all alignments. These methods return void, errors must be checked with target_check_error.--- src/adiv5.c | 224 ++++++++++++++++++--------------------------------- src/arm7tdmi.c | 8 +- src/cortexm.c | 9 +-- src/crc32.c | 9 +-- src/gdb_main.c | 19 +---- src/include/target.h | 39 ++------- src/lmi.c | 4 +- src/lpc11xx.c | 4 +- src/lpc43xx.c | 24 +++--- src/nrf51.c | 4 +- src/sam3x.c | 4 +- src/stm32f1.c | 4 +- src/stm32f4.c | 4 +- src/stm32l0.c | 27 +++---- src/stm32l1.c | 6 +- 15 files changed, 137 insertions(+), 252 deletions(-) diff --git a/src/adiv5.c b/src/adiv5.c index aee8471..8f99a9d 100644 --- a/src/adiv5.c +++ b/src/adiv5.c @@ -1,7 +1,7 @@ /* * This file is part of the Black Magic Debug project. * - * Copyright (C) 2011 Black Sphere Technologies Ltd. + * Copyright (C) 2015 Black Sphere Technologies Ltd. * Written by Gareth McMullin * * This program is free software: you can redistribute it and/or modify @@ -39,12 +39,10 @@ static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP"; static int ap_check_error(struct target_s *target); -static int ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len); -static int ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src, int len); -static int ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int len); -static int ap_mem_write_halfwords(struct target_s *target, uint32_t dest, const uint16_t *src, int len); -static int ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len); -static int ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, int len); +static void ap_mem_read(struct target_s *target, void *dest, uint32_t src, + size_t len); +static void ap_mem_write(struct target_s *target, uint32_t dest, + const void *src, size_t len); void adiv5_dp_ref(ADIv5_DP_t *dp) { @@ -147,12 +145,8 @@ void adiv5_dp_init(ADIv5_DP_t *dp) t->driver = adiv5_driver_str; t->check_error = ap_check_error; - t->mem_read_words = ap_mem_read_words; - t->mem_write_words = ap_mem_write_words; - t->mem_read_halfwords = ap_mem_read_halfwords; - t->mem_write_halfwords = ap_mem_write_halfwords; - t->mem_read_bytes = ap_mem_read_bytes; - t->mem_write_bytes = ap_mem_write_bytes; + t->mem_read = ap_mem_read; + t->mem_write = ap_mem_write; /* The rest sould only be added after checking ROM table */ cortexm_probe(t); @@ -167,88 +161,69 @@ ap_check_error(struct target_s *target) return adiv5_dp_error(ap->dp); } -static int -ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len) +enum align { + ALIGN_BYTE = 0, + ALIGN_HALFWORD = 1, + ALIGN_WORD = 2 +}; +#define ALIGNOF(x) (((x) & 3) == 0 ? ALIGN_WORD : \ + (((x) & 1) == 0 ? ALIGN_HALFWORD : ALIGN_BYTE)) +#undef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) + +/* Program the CSW and TAR for sequencial access at a given width */ +static void ap_mem_access_setup(ADIv5_AP_t *ap, uint32_t addr, enum align align) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t osrc = src; - - len >>= 2; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - while(--len) { - *dest++ = adiv5_dp_low_access(ap->dp, - ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - src += 4; - /* Check for 10 bit address overflow */ - if ((src ^ osrc) & 0xfffffc00) { - osrc = src; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - } - + uint32_t csw = ap->csw | ADIV5_AP_CSW_ADDRINC_SINGLE; + + switch (align) { + case ALIGN_BYTE: + csw |= ADIV5_AP_CSW_SIZE_BYTE; + break; + case ALIGN_HALFWORD: + csw |= ADIV5_AP_CSW_SIZE_HALFWORD; + break; + case ALIGN_WORD: + csw |= ADIV5_AP_CSW_SIZE_WORD; + break; } - *dest++ = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, - ADIV5_DP_RDBUFF, 0); - - return 0; + adiv5_ap_write(ap, ADIV5_AP_CSW, csw); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, addr); } -static int -ap_mem_read_halfwords(struct target_s *target, uint16_t *dest, uint32_t src, int len) +/* Extract read data from data lane based on align and src address */ +static void * extract(void *dest, uint32_t src, uint32_t val, enum align align) { - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t tmp; - uint32_t osrc = src; - - len >>= 1; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - while(--len) { - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, - ADIV5_AP_DRW, 0); - *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); - - src += 2; - /* Check for 10 bit address overflow */ - if ((src ^ osrc) & 0xfffffc00) { - osrc = src; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - } + switch (align) { + case ALIGN_BYTE: + *(uint8_t *)dest = (val >> ((src & 0x3) << 3) & 0xFF); + break; + case ALIGN_HALFWORD: + *(uint16_t *)dest = (val >> ((src & 0x2) << 3) & 0xFFFF); + break; + case ALIGN_WORD: + *(uint32_t *)dest = val; + break; } - tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); - *dest++ = (tmp >> ((src & 0x2) << 3) & 0xFFFF); - - return 0; + return (uint8_t *)dest + (1 << align); } -static int -ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len) +static void +ap_mem_read(struct target_s *target, void *dest, uint32_t src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t tmp; uint32_t osrc = src; + enum align align = MIN(ALIGNOF(src), ALIGNOF(len)); - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, src); + len >>= align; + ap_mem_access_setup(ap, src, align); adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - while(--len) { + while (--len) { tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0); - *dest++ = (tmp >> ((src & 0x3) << 3) & 0xFF); + dest = extract(dest, src, tmp, align); - src++; + src += (1 << align); /* Check for 10 bit address overflow */ if ((src ^ osrc) & 0xfffffc00) { osrc = src; @@ -259,77 +234,35 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len) } } tmp = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0); - *dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF); - - return 0; + extract(dest, src, tmp, align); } - -static int -ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src, int len) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t odest = dest; - - len >>= 2; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - while(len--) { - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, - ADIV5_AP_DRW, *src++); - dest += 4; - /* Check for 10 bit address overflow */ - if ((dest ^ odest) & 0xfffffc00) { - odest = dest; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - } - } - - return 0; -} - -static int -ap_mem_write_halfwords(struct target_s *target, uint32_t dest, const uint16_t *src, int len) +static void +ap_mem_write(struct target_s *target, uint32_t dest, const void *src, size_t len) { ADIv5_AP_t *ap = adiv5_target_ap(target); uint32_t odest = dest; - - len >>= 1; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - while(len--) { - uint32_t tmp = (uint32_t)*src++ << ((dest & 2) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, - ADIV5_AP_DRW, tmp); - dest += 2; - /* Check for 10 bit address overflow */ - if ((dest ^ odest) & 0xfffffc00) { - odest = dest; - adiv5_dp_low_access(ap->dp, - ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); + enum align align = MIN(ALIGNOF(dest), ALIGNOF(len)); + + len >>= align; + ap_mem_access_setup(ap, dest, align); + while (len--) { + uint32_t tmp = 0; + /* Pack data into correct data lane */ + switch (align) { + case ALIGN_BYTE: + tmp = ((uint32_t)*(uint8_t *)src) << ((dest & 3) << 3); + break; + case ALIGN_HALFWORD: + tmp = ((uint32_t)*(uint16_t *)src) << ((dest & 2) << 3); + break; + case ALIGN_WORD: + tmp = *(uint32_t *)src; + break; } - } - return 0; -} - -static int -ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, int len) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t odest = dest; - - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); - while(len--) { - uint32_t tmp = (uint32_t)*src++ << ((dest++ & 3) << 3); - adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, - ADIV5_AP_DRW, tmp); + src = (uint8_t *)src + (1 << align); + dest += (1 << align); + adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, tmp); /* Check for 10 bit address overflow */ if ((dest ^ odest) & 0xfffffc00) { @@ -338,11 +271,8 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i ADIV5_LOW_WRITE, ADIV5_AP_TAR, dest); } } - return 0; } - - uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr) { adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | diff --git a/src/arm7tdmi.c b/src/arm7tdmi.c index 1721787..afd623c 100644 --- a/src/arm7tdmi.c +++ b/src/arm7tdmi.c @@ -123,12 +123,8 @@ void arm7tdmi_jtag_handler(jtag_dev_t *dev) t->attach = arm7_attach; t->detach = (void *)do_nothing; t->check_error = (void *)do_nothing; - t->mem_read_words = (void *)do_nothing; - t->mem_write_words = (void *)do_nothing; - t->mem_read_halfwords = (void *)do_nothing; - t->mem_write_halfwords = (void *)do_nothing; - t->mem_read_bytes = (void *)do_nothing; - t->mem_write_bytes = (void *)do_nothing; + t->mem_read = (void *)do_nothing; + t->mem_write = (void *)do_nothing; t->regs_size = 16 * sizeof(uint32_t); t->regs_read = (void *)arm7_regs_read; t->regs_write = (void *)arm7_regs_write; diff --git a/src/cortexm.c b/src/cortexm.c index da48f8e..fcc6a9d 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -502,7 +502,7 @@ cortexm_halt_wait(struct target_s *target) * call. */ uint32_t pc = cortexm_pc_read(target); uint16_t bkpt_instr; - target_mem_read_bytes(target, (uint8_t *)&bkpt_instr, pc, 2); + target_mem_read(target, &bkpt_instr, pc, 2); if (bkpt_instr == 0xBEAB) { int n = cortexm_hostio_request(target); if (n > 0) { @@ -571,7 +571,7 @@ static int cortexm_fault_unwind(struct target_s *target) bool fpca = !(retcode & (1<<4)); /* Read stack for pre-exception registers */ uint32_t sp = spsel ? regs[REG_PSP] : regs[REG_MSP]; - target_mem_read_words(target, stack, sp, sizeof(stack)); + target_mem_read(target, stack, sp, sizeof(stack)); if (target_check_error(target)) return 0; regs[REG_LR] = stack[5]; /* restore LR to pre-exception state */ @@ -840,7 +840,7 @@ static int cortexm_hostio_request(target *t) uint32_t params[4]; target_regs_read(t, arm_regs); - target_mem_read_words(t, params, arm_regs[1], sizeof(params)); + target_mem_read(t, params, arm_regs[1], sizeof(params)); priv->syscall = arm_regs[0]; DEBUG("syscall 0x%x (%x %x %x %x)\n", priv->syscall, @@ -860,8 +860,7 @@ static int cortexm_hostio_request(target *t) uint32_t pflag = flags[params[1] >> 1]; char filename[4]; - target_mem_read_bytes(t, (uint8_t *)filename, - params[0], sizeof(filename)); + target_mem_read(t, filename, params[0], sizeof(filename)); /* handle requests for console i/o */ if (!strcmp(filename, ":tt")) { if (pflag == FILEIO_O_RDONLY) diff --git a/src/crc32.c b/src/crc32.c index 42d1d48..fffc04c 100644 --- a/src/crc32.c +++ b/src/crc32.c @@ -100,8 +100,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) uint8_t byte; while (len--) { - if (target_mem_read_bytes(target, &byte, base, 1) != 0) - return -1; + target_mem_read(target, &byte, base, 1); crc = crc32_calc(crc, byte); base++; @@ -119,8 +118,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) CRC_CR |= CRC_CR_RESET; while (len > 3) { - if (target_mem_read_words(target, &data, base, 4) != 0) - return -1; + target_mem_read(target, &data, base, 4); CRC_DR = __builtin_bswap32(data); base += 4; @@ -130,8 +128,7 @@ uint32_t generic_crc32(struct target_s *target, uint32_t base, int len) crc = CRC_DR; while (len--) { - if (target_mem_read_bytes(target, (uint8_t *)&data, base++, 1) != 0) - return -1; + target_mem_read(target, &data, base++, 1); crc ^= data << 24; for (i = 0; i < 8; i++) { diff --git a/src/gdb_main.c b/src/gdb_main.c index ab4fc8a..7bb788b 100644 --- a/src/gdb_main.c +++ b/src/gdb_main.c @@ -88,12 +88,7 @@ gdb_main(void) sscanf(pbuf, "m%" SCNx32 ",%" SCNx32, &addr, &len); DEBUG("m packet: addr = %" PRIx32 ", len = %" PRIx32 "\n", addr, len); uint8_t mem[len]; - if(((addr & 3) == 0) && ((len & 3) == 0)) - target_mem_read_words(cur_target, (void*)mem, addr, len); - else if(((addr & 1) == 0) && ((len & 1) == 0)) - target_mem_read_halfwords(cur_target, (void*)mem, addr, len); - else - target_mem_read_bytes(cur_target, (void*)mem, addr, len); + target_mem_read(cur_target, mem, addr, len); if(target_check_error(cur_target)) gdb_putpacketz("E01"); else @@ -116,12 +111,7 @@ gdb_main(void) DEBUG("M packet: addr = %" PRIx32 ", len = %" PRIx32 "\n", addr, len); uint8_t mem[len]; unhexify(mem, pbuf + hex, len); - if(((addr & 3) == 0) && ((len & 3) == 0)) - target_mem_write_words(cur_target, addr, (void*)mem, len); - else if(((addr & 1) == 0) && ((len & 1) == 0)) - target_mem_write_halfwords(cur_target, addr, (void*)mem, len); - else - target_mem_write_bytes(cur_target, addr, (void*)mem, len); + target_mem_write(cur_target, addr, mem, len); if(target_check_error(cur_target)) gdb_putpacketz("E01"); else @@ -244,10 +234,7 @@ gdb_main(void) ERROR_IF_NO_TARGET(); sscanf(pbuf, "X%" SCNx32 ",%" SCNx32 ":%n", &addr, &len, &bin); DEBUG("X packet: addr = %" PRIx32 ", len = %" PRIx32 "\n", addr, len); - if(((addr & 3) == 0) && ((len & 3) == 0)) - target_mem_write_words(cur_target, addr, (void*)pbuf+bin, len); - else - target_mem_write_bytes(cur_target, addr, (void*)pbuf+bin, len); + target_mem_write(cur_target, addr, pbuf+bin, len); if(target_check_error(cur_target)) gdb_putpacketz("E01"); else diff --git a/src/include/target.h b/src/include/target.h index 5db79a7..b48e054 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -48,24 +48,11 @@ target *target_attach(target *t, target_destroy_callback destroy_cb); (target)->check_error(target) /* Memory access functions */ -#define target_mem_read_words(target, dest, src, len) \ - (target)->mem_read_words((target), (dest), (src), (len)) - -#define target_mem_write_words(target, dest, src, len) \ - (target)->mem_write_words((target), (dest), (src), (len)) - -#define target_mem_read_halfwords(target, dest, src, len) \ - (target)->mem_read_halfwords((target), (dest), (src), (len)) - -#define target_mem_write_halfwords(target, dest, src, len) \ - (target)->mem_write_halfwords((target), (dest), (src), (len)) - -#define target_mem_read_bytes(target, dest, src, len) \ - (target)->mem_read_bytes((target), (dest), (src), (len)) - -#define target_mem_write_bytes(target, dest, src, len) \ - (target)->mem_write_bytes((target), (dest), (src), (len)) +#define target_mem_read(target, dest, src, len) \ + (target)->mem_read((target), (dest), (src), (len)) +#define target_mem_write(target, dest, src, len) \ + (target)->mem_write((target), (dest), (src), (len)) /* Register access functions */ #define target_regs_read(target, data) \ @@ -135,20 +122,10 @@ struct target_s { int (*check_error)(struct target_s *target); /* Memory access functions */ - int (*mem_read_words)(struct target_s *target, uint32_t *dest, uint32_t src, - int len); - int (*mem_write_words)(struct target_s *target, uint32_t dest, - const uint32_t *src, int len); - - int (*mem_read_halfwords)(struct target_s *target, uint16_t *dest, uint32_t src, - int len); - int (*mem_write_halfwords)(struct target_s *target, uint32_t dest, - const uint16_t *src, int len); - - int (*mem_read_bytes)(struct target_s *target, uint8_t *dest, uint32_t src, - int len); - int (*mem_write_bytes)(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); + void (*mem_read)(struct target_s *target, void *dest, uint32_t src, + size_t len); + void (*mem_write)(struct target_s *target, uint32_t dest, + const void *src, size_t len); /* Register access functions */ int regs_size; diff --git a/src/lmi.c b/src/lmi.c index 9359458..8c5e143 100644 --- a/src/lmi.c +++ b/src/lmi.c @@ -159,9 +159,9 @@ int lmi_flash_write(struct target_s *target, uint32_t dest, data[1] = len >> 2; memcpy(&data[2], src, len); DEBUG("Sending stub\n"); - target_mem_write_words(target, 0x20000000, (void*)lmi_flash_write_stub, 0x30); + target_mem_write(target, 0x20000000, (void*)lmi_flash_write_stub, 0x30); DEBUG("Sending data\n"); - target_mem_write_words(target, 0x20000030, data, len + 8); + target_mem_write(target, 0x20000030, data, len + 8); DEBUG("Running stub\n"); target_pc_write(target, 0x20000000); target_halt_resume(target, 0); diff --git a/src/lpc11xx.c b/src/lpc11xx.c index b6309c2..eca3daf 100644 --- a/src/lpc11xx.c +++ b/src/lpc11xx.c @@ -170,7 +170,7 @@ lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned par /* fill out the remainder of the parameters and copy the structure to RAM */ param->opcodes[0] = 0xbe00; param->opcodes[1] = 0x0000; - target_mem_write_words(target, IAP_RAM_BASE, (void *)param, param_len); + target_mem_write(target, IAP_RAM_BASE, param, param_len); /* set up for the call to the IAP ROM */ target_regs_read(target, regs); @@ -191,7 +191,7 @@ lpc11x_iap_call(struct target_s *target, struct flash_param *param, unsigned par while (!target_halt_wait(target)); /* copy back just the parameters structure */ - target_mem_read_words(target, (void *)param, IAP_RAM_BASE, sizeof(struct flash_param)); + target_mem_read(target, param, IAP_RAM_BASE, sizeof(struct flash_param)); } static int flash_page_size(struct target_s *target) diff --git a/src/lpc43xx.c b/src/lpc43xx.c index eca7338..0ae9418 100644 --- a/src/lpc43xx.c +++ b/src/lpc43xx.c @@ -224,7 +224,7 @@ static bool lpc43xx_cmd_reset(target *target, int argc, const char *argv[]) static const uint32_t reset_val = 0x05FA0004; /* System reset on target */ - target_mem_write_words(target, AIRCR, &reset_val, sizeof(reset_val)); + target_mem_write(target, AIRCR, &reset_val, sizeof(reset_val)); return true; } @@ -340,12 +340,12 @@ static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, /* Pet WDT before each IAP call, if it is on */ lpc43xx_wdt_pet(target); - target_mem_read_words(target, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry)); + target_mem_read(target, &iap_entry, IAP_ENTRYPOINT_LOCATION, sizeof(iap_entry)); /* fill out the remainder of the parameters and copy the structure to RAM */ param->opcode = ARM_THUMB_BREAKPOINT; /* breakpoint */ param->pad0 = 0x0000; /* pad */ - target_mem_write_words(target, IAP_RAM_BASE, (void *)param, param_len); + target_mem_write(target, IAP_RAM_BASE, param, param_len); /* set up for the call to the IAP ROM */ target_regs_read(target, regs); @@ -362,7 +362,7 @@ static void lpc43xx_iap_call(struct target_s *target, struct flash_param *param, while (!target_halt_wait(target)); /* copy back just the parameters structure */ - target_mem_read_words(target, (void *)param, IAP_RAM_BASE, sizeof(struct flash_param)); + target_mem_read(target, param, IAP_RAM_BASE, sizeof(struct flash_param)); } static int lpc43xx_flash_prepare(struct target_s *target, uint32_t addr, int len) @@ -429,7 +429,7 @@ static int lpc43xx_flash_erase(struct target_s *target, uint32_t addr, size_t le static void lpc43xx_set_internal_clock(struct target_s *target) { const uint32_t val2 = (1 << 11) | (1 << 24); - target_mem_write_words(target, 0x40050000 + 0x06C, &val2, sizeof(val2)); + target_mem_write(target, 0x40050000 + 0x06C, &val2, sizeof(val2)); } static int lpc43xx_flash_write(struct target_s *target, @@ -477,9 +477,9 @@ static int lpc43xx_flash_write(struct target_s *target, } /* copy buffer into target memory */ - target_mem_write_words(target, + target_mem_write(target, IAP_RAM_BASE + offsetof(struct flash_program, data), - (uint32_t*)flash_pgm.data, sizeof(flash_pgm.data)); + flash_pgm.data, sizeof(flash_pgm.data)); /* set the destination address and program */ flash_pgm.p.command = IAP_CMD_PROGRAM; @@ -541,7 +541,7 @@ static void lpc43xx_wdt_set_period(struct target_s *target) { uint32_t wdt_mode = 0; /* Check if WDT is on */ - target_mem_read_words(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); + target_mem_read(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); /* If WDT on, we can't disable it, but we may be able to set a long period */ if (wdt_mode && !(wdt_mode & LPC43XX_WDT_PROTECT)) @@ -549,7 +549,7 @@ static void lpc43xx_wdt_set_period(struct target_s *target) const uint32_t wdt_period = LPC43XX_WDT_PERIOD_MAX; - target_mem_write_words(target, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period)); + target_mem_write(target, LPC43XX_WDT_CNT, &wdt_period, sizeof(wdt_period)); } } @@ -557,7 +557,7 @@ static void lpc43xx_wdt_pet(struct target_s *target) { uint32_t wdt_mode = 0; /* Check if WDT is on */ - target_mem_read_words(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); + target_mem_read(target, &wdt_mode, LPC43XX_WDT_MODE, sizeof(wdt_mode)); /* If WDT on, pet */ if (wdt_mode) @@ -566,7 +566,7 @@ static void lpc43xx_wdt_pet(struct target_s *target) const uint32_t feed2 = 0x55;; - target_mem_write_words(target, LPC43XX_WDT_FEED, &feed1, sizeof(feed1)); - target_mem_write_words(target, LPC43XX_WDT_FEED, &feed2, sizeof(feed2)); + target_mem_write(target, LPC43XX_WDT_FEED, &feed1, sizeof(feed1)); + target_mem_write(target, LPC43XX_WDT_FEED, &feed2, sizeof(feed2)); } } diff --git a/src/nrf51.c b/src/nrf51.c index 55c9a58..a4396bb 100644 --- a/src/nrf51.c +++ b/src/nrf51.c @@ -233,8 +233,8 @@ static int nrf51_flash_write(struct target_s *target, uint32_t dest, return -1; /* Write stub and data to target ram and set PC */ - target_mem_write_words(target, 0x20000000, (void*)nrf51_flash_write_stub, 0x28); - target_mem_write_words(target, 0x20000028, data, len + 8); + target_mem_write(target, 0x20000000, nrf51_flash_write_stub, 0x28); + target_mem_write(target, 0x20000028, data, len + 8); target_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/sam3x.c b/src/sam3x.c index 7141cb5..211fc92 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -326,7 +326,7 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, size_t len) memset(buf, 0xff, sizeof(buf)); /* Only do this once, since it doesn't change. */ - target_mem_write_words(target, addr, (void*)buf, SAM3_PAGE_SIZE); + target_mem_write(target, addr, buf, SAM3_PAGE_SIZE); while (len) { if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_EWP, chunk)) @@ -384,7 +384,7 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest, src += page_size; } - target_mem_write_words(target, dest, (void*)buf, page_size); + target_mem_write(target, dest, buf, page_size); if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_WP, chunk)) return -1; } diff --git a/src/stm32f1.c b/src/stm32f1.c index 405bc1a..ca55fad 100644 --- a/src/stm32f1.c +++ b/src/stm32f1.c @@ -293,8 +293,8 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Write stub and data to target ram and set PC */ - target_mem_write_words(target, 0x20000000, (void*)stm32f1_flash_write_stub, 0x2C); - target_mem_write_words(target, 0x2000002C, data, sizeof(data)); + target_mem_write(target, 0x20000000, stm32f1_flash_write_stub, 0x2C); + target_mem_write(target, 0x2000002C, data, sizeof(data)); target_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/stm32f4.c b/src/stm32f4.c index fac097a..58d1328 100644 --- a/src/stm32f4.c +++ b/src/stm32f4.c @@ -253,8 +253,8 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest, memcpy((uint8_t *)&data[2] + offset, src, len); /* Write stub and data to target ram and set PC */ - target_mem_write_words(target, 0x20000000, (void*)stm32f4_flash_write_stub, 0x30); - target_mem_write_words(target, 0x20000030, data, sizeof(data)); + target_mem_write(target, 0x20000000, stm32f4_flash_write_stub, 0x30); + target_mem_write(target, 0x20000030, data, sizeof(data)); target_pc_write(target, 0x20000000); if(target_check_error(target)) return -1; diff --git a/src/stm32l0.c b/src/stm32l0.c index 2e30035..028f2a1 100644 --- a/src/stm32l0.c +++ b/src/stm32l0.c @@ -380,17 +380,17 @@ static int stm32lx_nvm_prog_erase_stubbed(struct target_s* target, info.page_size = stm32lx_nvm_prog_page_size(target); /* Load the stub */ - target_mem_write_words(target, STM32Lx_STUB_PHYS, - (void*) &stm32l0_nvm_prog_erase_stub[0], - sizeof(stm32l0_nvm_prog_erase_stub)); + target_mem_write(target, STM32Lx_STUB_PHYS, + &stm32l0_nvm_prog_erase_stub[0], + sizeof(stm32l0_nvm_prog_erase_stub)); /* Setup parameters */ info.destination = addr; info.size = size; /* Copy parameters */ - target_mem_write_words(target, STM32Lx_STUB_INFO_PHYS, - (void*) &info, sizeof(info)); + target_mem_write(target, STM32Lx_STUB_INFO_PHYS, + &info, sizeof(info)); /* Execute stub */ target_pc_write(target, STM32Lx_STUB_PHYS); @@ -434,9 +434,9 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, info.page_size = page_size; /* Load the stub */ - target_mem_write_words(target, STM32Lx_STUB_PHYS, - (void*) &stm32l0_nvm_prog_write_stub[0], - sizeof(stm32l0_nvm_prog_write_stub)); + target_mem_write(target, STM32Lx_STUB_PHYS, + &stm32l0_nvm_prog_write_stub[0], + sizeof(stm32l0_nvm_prog_write_stub)); while (size > 0) { @@ -458,8 +458,7 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, info.size = cb; /* Copy data to write to flash */ - target_mem_write_words(target, info.source, (void*) source, - info.size); + target_mem_write(target, info.source, source, info.size); /* Move pointers early */ destination += cb; @@ -467,8 +466,8 @@ static int stm32lx_nvm_prog_write_stubbed(struct target_s* target, size -= cb; /* Copy parameters */ - target_mem_write_words(target, STM32Lx_STUB_INFO_PHYS, - (void*) &info, sizeof(info)); + target_mem_write(target, STM32Lx_STUB_INFO_PHYS, + &info, sizeof(info)); /* Execute stub */ target_pc_write(target, STM32Lx_STUB_PHYS); @@ -661,7 +660,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, c = size; size -= c; - target_mem_write_words(target, destination, source, c); + target_mem_write(target, destination, source, c); source += c/4; destination += c; } @@ -673,7 +672,7 @@ static int stm32lx_nvm_prog_write(struct target_s* target, size_t c = size & ~(half_page_size - 1); size -= c; - target_mem_write_words(target, destination, source, c); + target_mem_write(target, destination, source, c); source += c/4; destination += c; } diff --git a/src/stm32l1.c b/src/stm32l1.c index 86298e5..c72cccd 100644 --- a/src/stm32l1.c +++ b/src/stm32l1.c @@ -176,7 +176,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, if(xlen > len) xlen = len & ~3; - target_mem_write_words(target, dest, (uint32_t*)src, xlen); + target_mem_write(target, dest, src, xlen); src += xlen; dest += xlen; len -= xlen; @@ -192,7 +192,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, if(target_check_error(target)) return -1; - target_mem_write_words(target, dest, (uint32_t*)src, len & ~127); + target_mem_write(target, dest, src, len & ~127); src += len & ~127; dest += len & ~127; len -= len & ~127; @@ -208,7 +208,7 @@ static int stm32l1_flash_write(struct target_s *target, uint32_t dest, /* Handle non-full page at the end */ if(len >= 4) { - target_mem_write_words(target, dest, (uint32_t*)src, len & ~3); + target_mem_write(target, dest, src, len & ~3); src += len & ~3; dest += len & ~3; len -= len & ~3; -- cgit v1.2.3