From bc89217e3f96ae60f4c8dfc6a94cc8e64fb426ed Mon Sep 17 00:00:00 2001 From: Florian Larysch Date: Mon, 30 Mar 2015 18:25:13 +0200 Subject: sam3x: add SAM3U support --- src/sam3x.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/sam3x.c b/src/sam3x.c index 63b0991..0566718 100644 --- a/src/sam3x.c +++ b/src/sam3x.c @@ -65,6 +65,18 @@ static const char sam3n_xml_memory_map[] = "" " " ""; +static const char sam3u_xml_memory_map[] = "" +/* ""*/ + "" + " " + " 0x100" + " " + " " + " " + ""; + static const char sam4s_xml_memory_map[] = "" /* "" /* Enhanced Embedded Flash Controller (EEFC) Register Map */ #define SAM3N_EEFC_BASE 0x400E0A00 #define SAM3X_EEFC_BASE(x) (0x400E0A00+((x)*0x400)) +#define SAM3U_EEFC_BASE(x) (0x400E0800+((x)*0x200)) #define SAM4S_EEFC_BASE(x) (0x400E0A00+((x)*0x200)) #define EEFC_FMR(base) ((base)+0x00) #define EEFC_FCR(base) ((base)+0x04) @@ -111,6 +124,7 @@ static const char sam4s_xml_memory_map[] = "" #define SAM3X_CHIPID_CIDR 0x400E0940 #define SAM3N_CHIPID_CIDR 0x400E0740 #define SAM3S_CHIPID_CIDR 0x400E0740 +#define SAM3U_CHIPID_CIDR 0x400E0740 #define SAM4S_CHIPID_CIDR 0x400E0740 #define CHIPID_CIDR_VERSION_MASK (0x1F << 0) @@ -126,6 +140,8 @@ static const char sam4s_xml_memory_map[] = "" #define CHIPID_CIDR_NVPSIZ2_MASK (0x0F << 12) #define CHIPID_CIDR_SRAMSIZ_MASK (0x0F << 16) #define CHIPID_CIDR_ARCH_MASK (0xFF << 20) +#define CHIPID_CIDR_ARCH_SAM3UxC (0x80 << 20) +#define CHIPID_CIDR_ARCH_SAM3UxE (0x81 << 20) #define CHIPID_CIDR_ARCH_SAM3XxC (0x84 << 20) #define CHIPID_CIDR_ARCH_SAM3XxE (0x85 << 20) #define CHIPID_CIDR_ARCH_SAM3XxG (0x86 << 20) @@ -189,6 +205,18 @@ bool sam3x_probe(target *t) return true; } + t->idcode = target_mem_read32(t, SAM3U_CHIPID_CIDR); + switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { + case CHIPID_CIDR_ARCH_SAM3UxC | CHIPID_CIDR_EPROC_CM3: + case CHIPID_CIDR_ARCH_SAM3UxE | CHIPID_CIDR_EPROC_CM3: + t->driver = "Atmel SAM3U"; + t->xml_mem_map = sam3u_xml_memory_map; + t->flash_erase = sam3x_flash_erase; + t->flash_write = sam3x_flash_write; + target_add_commands(t, sam3x_cmd_list, "SAM3U"); + return true; + } + t->idcode = target_mem_read32(t, SAM4S_CHIPID_CIDR); switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) { case CHIPID_CIDR_ARCH_SAM4SxA | CHIPID_CIDR_EPROC_CM4: @@ -248,6 +276,21 @@ sam3x_flash_base(target *t, uint32_t addr, uint32_t *offset) } } + /* The SAM3U has a constant split between both banks */ + if (strcmp(t->driver, "Atmel SAM3U") == 0) { + if (addr >= 0x100000) { + if(offset) + *offset = addr - 0x100000; + + return SAM3U_EEFC_BASE(1); + } else { + if(offset) + *offset = addr - 0x80000; + + return SAM3U_EEFC_BASE(0); + } + } + if (strcmp(t->driver, "Atmel SAM4S") == 0) { uint32_t half = -1; switch (t->idcode & CHIPID_CIDR_NVPSIZ_MASK) { -- cgit v1.2.3