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authorFrantisek Burian2014-02-13 18:21:16 +0100
committerFrantisek Burian2014-02-13 18:21:16 +0100
commit12aeaad441a251e91ecb48528c6446a7461b435a (patch)
treee60b6d1c26bcba844f0106714636847c670d4ca1 /src/platforms/swlink/platform.c
parent690e99c6b269bb555d41d0f3f1bfeee0189b8156 (diff)
[locm3] Use the new clock-enabling mechanisms in locm3.
Diffstat (limited to 'src/platforms/swlink/platform.c')
-rw-r--r--src/platforms/swlink/platform.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/src/platforms/swlink/platform.c b/src/platforms/swlink/platform.c
index ea88dcb..28db60f 100644
--- a/src/platforms/swlink/platform.c
+++ b/src/platforms/swlink/platform.c
@@ -47,11 +47,11 @@ int platform_init(void)
rcc_clock_setup_in_hse_8mhz_out_72mhz();
/* Enable peripherals */
- rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN);
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
- rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_CRCEN);
+ rcc_periph_clock_enable(RCC_USB);
+ rcc_periph_clock_enable(RCC_GPIOA);
+ rcc_periph_clock_enable(RCC_GPIOB);
+ rcc_periph_clock_enable(RCC_AFIO);
+ rcc_periph_clock_enable(RCC_CRC);
/* Unmap JTAG Pins so we can reuse as GPIO */
data = AFIO_MAPR;
@@ -135,10 +135,9 @@ const char *platform_target_voltage(void)
void disconnect_usb(void)
{
/* Disconnect USB cable by resetting USB Device and pulling USB_DP low*/
- rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN);
- rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1ENR_USBEN);
- rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USBEN);
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
+ rcc_periph_reset_pulse(RST_USB);
+ rcc_periph_clock_enable(RCC_USB);
+ rcc_periph_clock_enable(RCC_GPIOA);
gpio_clear(GPIOA, GPIO12);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ,
GPIO_CNF_OUTPUT_OPENDRAIN, GPIO12);
@@ -147,7 +146,7 @@ void disconnect_usb(void)
void assert_boot_pin(void)
{
uint32_t crl = GPIOA_CRL;
- rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
+ rcc_periph_clock_enable(RCC_GPIOA);
/* Enable Pull on GPIOA1. We don't rely on the external pin
* really pulled, but only on the value of the CNF register
* changed from the reset value